Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: the specification does not describe the connections shown in figure 2. The specification recites, “The third power line M1_R3 may be a conduction path, to which the drain voltage VDD is provided,” in paragraph 26 on page 6. The examiner notes that figure 2 shows the third power line M1_R3 connected to VSS.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 11 recites the limitation “wherein a first upper side surface of the first buffer layer is vertically aligned to and directly contacts a side surface of the first spacer,” on page 7 lines 11-12. This limitation introduces new matter because the specification does not disclose a first upper side surface of the first buffer layer is vertically aligned to and directly contacts a side surface of the first spacer. The examiner notes that the specification discloses a first upper side USW1 of the first buffer layer BFL1 is vertically aligned to a side surface of the first spacer GS1 or a side surface of the first buffer layer BFL1 directly contacts the first spacer GS1. The examiner notes that the first upper side surface USW1 of the first buffer layer BFL1 vertically aligned to an outer surface of the first spacer GS1 is shown in figure 6A and described in paragraph 110. The examiner next notes that the first spacer directly contacting a side surface of the first buffer layer BFL1 is mentioned in paragraph 107, which further refers to figure 7. The examiner notes that figure 7 is a plan view of a semiconductor device obtained by planarizing the semiconductor device to a level of the first semiconductor pattern SP1 of the first channel pattern CH1. See paragraph 113. The examiner now points out that figure 7 does not show the first GS1 spacer directly contacting an upper side surface USW1 of the first buffer layer BFL1 or an alignment between an upper side surface USW1 of the first buffer layer BFL1 and a side surface of the first spacer GS1 because an upper side surface of the first buffer layer is not shown. The examiner further points out figure 7 is a plan view corresponding to a line L-L’ of figure 5A and that figure 5A appears to show an upper side surface of the first buffer layer and a side surface of the first space vertically aligned but does not show the first GS1 spacer directly contacting the upper side surface of the first buffer layer BFL1. Therefore, this limitation introduces new matter because wherein a first upper side surface of the first buffer layer is vertically aligned to and directly contacts a side surface of the first spacer is not disclosed.
Claims 12-15 also contain new matter because claims 12-15 depend from claim 11.
Claim 11 recites the limitation “wherein a second upper side surface of the second buffer layer is vertically aligned to and directly contacts a side surface of the first spacer,” on page 7 lines 13-14. This limitation introduces new matter because the specification does not disclose a second upper side surface of the second buffer layer is vertically aligned to and directly contacts a side surface of the first spacer. The examiner notes that the specification discloses a second upper side USW2 of the second buffer layer BFL2 is vertically aligned to a side surface of the first spacer GS1. The examiner notes that the second upper side surface USW2 of the second buffer layer BFL2 vertically aligned to an outer surface of the first spacer GS1 is shown in figure 6B and described in paragraph 111. The examiner next notes that the first spacer directly contacting a side surface of the first buffer layer BFL1 is mentioned in paragraph 107, however, this paragraph does not mention the first space directly contacting a side surface of the second buffer layer BFL2. The examiner also notes out that figure 7 does not show the second buffer layer BFL2. Therefore, this limitation introduces new matter because wherein a second upper side surface of the second buffer layer is vertically aligned to and directly contacts a side surface of the first spacer is not disclosed.
Claims 12-15 also contain new matter because claims 12-15 depend from claim 11.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 10, and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantially” in claims 5 and 12 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “substantially” renders claims 5 and 12 indefinite because the relationship between a first horizontal distance between the gate insulating layer and a first upper side surface of the first buffer layer and a second horizontal distance between the gate insulating layer and a second upper side surface of the second buffer layer is unclear. For examination purposes, a first horizontal distance between the gate insulating layer and a first upper side surface of the first buffer layer and a second horizontal distance between the gate insulating layer and a second upper side surface of the second buffer layer will be treated as being equal distances.
The term “about” in claim 10 is a relative term which renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “about” renders claim 10 indefinite because upper endpoint of a range for a ratio of a thickness of the side portion of the first buffer layer to a thickness of a center portion of the first buffer layer is unclear. For examination purposes, the range of a ratio of thickness will be treated as being from 0.7 to 1.
The term “about” in claim 10 is a relative term which renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “about” renders claim 10 indefinite because endpoints of a range for a ratio of a thickness of the side portion of the first buffer layer to a thickness of a center portion of the first buffer layer is unclear. For examination purposes, the range of a ratio of thickness will be treated as being from 0.7 to 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US2022/0367622).
Regarding Claim 11:
Lin discloses a semiconductor device, comprising:
a substrate (substrate, See figs. 1-6, 22A, ref. no. 50, paragraphs 13-14, 16, and 19-20) comprising a p-type metal-oxide-semiconductor (MOS) field-effect transistor (FET) (PMOSFET) region (p-type region, See figs. 2-6, 22A, ref. no. 50P and paragraph 20) and an n-type MOSFET (NMOSFET) region (n-type region, See fig. 2-6, 22A, ref. no. 50N and paragraph 20);
a first active pattern on the PMOSFET region (fins and adjacent STI regions on p-type region, See fig. 4, ref. no. 50P, 62, 70 and paragraph 29);
a second active pattern on the NMOSFET region (fins and adjacent STI regions on n-type region, See fig. 4, ref. nos. 50N, 62, 70 and paragraph 29);
a first channel pattern (nanostructures acting as channel regions in p-type region, See figs. 1, 6, 22A, ref. no. 66 and paragraph 14) and a first source/drain pattern on the first active pattern (source/drain regions in the p-type region, See figs. 1, 11A, 22A, ref. no. 98, paragraphs 15-16, 49-50, and 80), the first channel pattern connected to the first source/drain pattern (See figs. 11A, 22A, ref. nos. 66, 98);
a second channel pattern (nanostructures acting as channel regions in n-type region, See figs. 1, 6, 22A, ref. no. 66 and paragraph 14) and a second source/drain pattern on the second active pattern (source/drain regions in the n-type region, See figs. 1, 11A, 22A, ref. no. 98, paragraphs 15-16, 49-50, and 80), the second channel pattern connected to the second source/drain pattern (See figs. 11A, 22A, ref. nos. 66, 98);
a gate electrode (gate electrode, See figs. 1, 22A, ref. no. 124 and paragraphs 15-16) on the first channel pattern and the second channel pattern;
a gate insulating layer (gate dielectric, See figs. 1, 22A, ref. no. 122 and paragraphs 15-16) between the gate electrode and each of the first and second channel patterns; and
a gate spacer (gate spacer and contact etch stop layer, See fig. 22A, ref. nos. 88, 102, paragraphs 40 and 70) on a side surface of the gate electrode,
wherein the gate spacer comprises a first spacer (contact etch stop layer, See fig. 22A, ref. no. 102), a second spacer (a layer of dielectric material of the gate space furthest from the gate dielectric, See fig. 22A, ref. nos. 88, 122, and paragraph 40), and a third spacer (a layer of dielectric material of the gate spacer closest to the gate dielectric, See fig. 22A, ref. no. 88, 122 and paragraph 40), (The examiner notes that Lin discloses the gate spacer may have two layers of dielectric material because Lin discloses the gate spacer may be formed by conformally depositing one or more dielectric materials and the disclosure conformally depositing one or more dielectric materials explicitly discloses conformally depositing two dielectric materials. See paragraph 40)
wherein the first spacer contacts the gate insulating layer (the contact etch stop layer is in contact with the gate dielectric through the layer of dielectric material of the gate spacer furthest from the gate dielectric and the layer of dielectric material of the gate spacer closest to the gate dielectric, See fig. 22A, ref. no. 88, 122 and paragraph 40),
wherein the second spacer is between the first spacer and the third spacer (the layer of dielectric material furthest from the gate dielectric is between the contact etch stop layer and the layer of dielectric material closest to the gate dielectric, See fig. 22A, ref. no. 88, 122 and paragraph 40),
wherein the first source/drain pattern comprises a first buffer layer (liner layer of source/drain regions in the p-type region, See figs. 11A, 22A, ref. no. 98B and paragraph 53) and a first main layer (main layer of source/drain regions in the p-type region, See figs. 11A, 22A, ref. no. 98C and paragraph 53) on the first buffer layer,
wherein the second source/drain pattern comprises a second buffer layer (liner layer of source/drain regions in the n-type region, See figs. 11A, 22A, ref. no. 98B and paragraph 53) and a second main layer (main layer of source/drain regions in the n-type region, See figs. 11A, 22A, ref. no. 98C and paragraph 53) on the second buffer layer,
wherein a first upper side surface (right top surface of the liner layer in the p-type region, See fig. 22A, ref. no. 98B) of the first buffer layer is vertically aligned to and directly contacts a side surface (bottom surface of the contact etch stop layer, See fig. 22A, ref. no. 102) of the first spacer (The right top surface of the liner layer is vertically aligned to the bottom surface of the contact etch stop layer because the edge the right top surface of the liner layer and the right edge of the contact etch stop layer are along the same line in a vertical direction. Also, the right top surface of the liner layer is shown directly contacting to the bottom surface of the contact etch stop layer. See fig. 22A, ref. nos. 98B, 102.), and
wherein a second upper side surface (right top surface of the liner layer in the n-type region, See fig. 22A, ref. no. 98B) of the second buffer layer is vertically aligned to and directly contacts the side surface (bottom surface of the contact etch stop layer, See fig. 22A, ref. no. 102) of the first spacer (The right top surface of the liner layer is vertically aligned to the bottom surface of the contact etch stop layer because the edge the right top surface of the liner layer and the right edge of the contact etch stop layer are along the same line in a vertical direction. Also, the right top surface of the liner layer is shown directly contacting to the bottom surface of the contact etch stop layer. See fig. 22A, ref. nos. 98B, 102.).
Regarding Claim 12:
Lin wherein a first horizontal distance (a distance between the gate dielectric and the top right surface of the liner layer in the p-type region, See figs. 22A, ref. nos. 98B, 122) between the gate insulating layer and the first upper side surface of the first buffer layer is substantially equal to a second horizontal distance (a distance between the gate dielectric and the top right surface of the liner layer in the n-type region, See figs. 22A, ref. nos. 98B, 122) between the gate insulating layer and the second upper side surface of the second buffer layer (The examiner notes that the structure shown in FIG. 22A is applicable to nano-FETs formed in the p-type region and nano-FETS formed in the n-type region, thus, the distance between the gate dielectric and the top right surface of the liner layer in the p-type region will be equal to the distance between the gate dielectric and the top right surface of the line layer in the n-type region. See paragraph 39.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US2022/0367622) in view of Hasan et al. (US 2023/0197855).
Regarding Claim 13:
Lin discloses the above stated semiconductor device. Lin further discloses wherein each of the first buffer layer and the second buffer layer comprises silicon-germanium (boron-doped silicon germanium for liner layer in p-type region and phosphorous-doped silicon germanium for liner layer in n-type region, See paragraphs 53-54).
Lin does not disclose wherein a germanium concentration in each of the first buffer layer and the second buffer layer is in a range between from 2 at% to 30 at%.
Hasan discloses wherein a germanium concentration in each of the first buffer layer and the second buffer layer is in a range from 2 at% to 30 at% (a silicon germanium layer includes approximately 30% germanium and approximately 70% silicon, See paragraph 36).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the nano-FETS of Lin to include wherein a germanium concentration in each of the first buffer layer and the second buffer layer is in a range from 2 at% to 30 at% as taught by Hasan so that fabrication techniques that form the source/drain regions with fewer defects can be used to fabricate the nano-FETS.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US2022/0367622) in view of Hasan et al. (US 2023/0197855) further in view of Lee et al. (US 2022/0238713).
Regarding Claim 14:
The above stated combination of Lin and Hasan discloses the above stated semiconductor device. Lin further discloses the first main layer comprises silicon-germanium (the main layer in the p-type region is formed boron-doped silicon germanium, See paragraphs 53-55).
The above state combination of Lin and Hasan does not disclose wherein a germanium concentration in the first main layer is higher than the germanium concentration in the first buffer layer.
Lee discloses wherein a germanium concentration in the first main layer is higher than the germanium concentration in the first buffer layer (the germanium concentration of epitaxial layers 142 are less than the germanium concentration of epitaxial layer 144, See fig. 1A, ref. no. 142A, 142B, 144A, 144B and paragraph 24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the nano-FETS of the above stated combination of Lin and Hasan to include wherein a germanium concentration in the first main layer is higher than the germanium concentration in the first buffer layer as taught by Lee in order to enhance the performance of the nano-FETs. (See Lee paragraph 12)
Regarding Claim 15:
The above stated combination of Lin, Hasan, and Lee discloses the above stated semiconductor device. Lin further discloses the second main layer comprises silicon (the main layer in the n-type region is formed phosphorous-doped silicon germanium, See paragraphs 53-55).
The above stated combination of Lin, Hasan, and Lee does not disclose wherein the germanium concentration in the second buffer layer is higher than the germanium concentration in the second main layer.
Lee discloses wherein the germanium concentration in the second buffer layer is higher than the germanium concentration in the second main layer (epitaxial layer of n-doped silicon, See fig. 1B, ref. no. 144C and paragraph 26. The examiner notes that the epitaxial layer of n-doped silicon does not contain germanium.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the nano-FETS of the above stated combination of Lin, Hasan, and Lee to include wherein the germanium concentration in the second buffer layer is higher than the germanium concentration in the second main layer as taught by Lee in order to enhance the performance of the nano-FETs. (See Lee paragraph 12)
Allowable Subject Matter
Claims 1-4, 6-8, and 16-20 are allowable. Claims 5 and 10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for allowance: with respect to claim 1, the disclosures and illustrations of Wang and/or Mochizuki fail to teach or suggest wherein a germanium concentration of the first source/drain pattern increases in a first direction that is away from the substrate and wherein a germanium concentration in the second source/drain pattern decreases in the first direction. The prior art also fails to provide other relevant disclosures which are properly combinable with Wang and/or Mochizuki to teach or suggest the limitations of claim 1. Therefore, claims 1-4 and 6-8 are allowable and claims 5 and 10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for allowance: with respect to claim 16, the disclosures and illustrations of Wang disclose a semiconductor device, comprising: a substrate (substrate, See figs. 1-17C and 19A-19D, ref. no. 50 and paragraphs 19-20) comprising an n-type metal-oxide-semiconductor (MOS) field-effect transistor (FET) (NMOSFET) region (n-type region, See figs. 1-6, ref. no. 50N and paragraph 20); an active pattern (fins and adjacent STI regions on n-type region, See fig. 4, ref. nos. 50N, 54, 60 and paragraphs 29-31) on the NMOSFET region; a channel pattern (channel regions in the n-type region, See fig. 6 ref. no. 56B, fig. 19A, ref. no. 68, and paragraphs 38-39) on the active pattern, the channel pattern comprising a plurality of semiconductor patterns (three semiconductor layers that act as channel regions See fig. 6 ref. no. 56B, fig. 19A, ref. no. 68, and paragraphs 38-39), spaced apart from each other; a source/drain pattern (source/drain regions in the n-type region, See figs. 9A-9C, 19A, ref. no. 92, paragraphs 39, and 46-47) on the active pattern; a gate electrode (gate electrode of the gate structure, See figs. 1, 19A, ref. nos. 100, 104, fig. 18, ref. no. 100, paragraphs 15 and 78-79) on the channel pattern, the gate electrode comprising: an inner electrode (portion of the gate electrode between the bottom semiconductor layer and the portion of the gate electrode between the middle semiconductor layer and the top semiconductor layer, See fig. 19A, ref. nos. 56B and 104) between adjacent semiconductor patterns of the plurality of semiconductor patterns; and an outer electrode (potion of the gate electrode above the top semiconductor layer, See fig. 19A, ref. nos. 56B and 104) on a uppermost semiconductor pattern of the plurality of semiconductor patterns; a gate insulating layer (gate dielectric, See figs. 13A-13B, 19A, ref. no. 102, paragraphs 39 and 57-58) between the gate electrode and each of the plurality of semiconductor patterns; a gate spacer (gate spacer, See figs. 7A-7B and 19A, ref. no. 80 and paragraph 40) on a side surface of the outer electrode; a gate capping pattern (second interlayer dielectric, See fig. 19A, ref. no. 122 and a paragraph 79) on a top surface of the outer electrode; an interlayer insulating layer (one or more stacked dielectric layers, See figs. 21, ref.no. 144, paragraph 83-84 and 86) on the gate capping pattern and the source/drain pattern; a gate contact (conductive features connected to gate contacts, See fig. 21, ref. nos. 124, 142, and paragraph 86) penetrating the interlayer insulating layer and the gate capping pattern, the gate contact connected to the gate electrode; an active contact (conductive features connected to source/drain contacts, See fig. 21, ref. nos. 126, 142, and paragraph 86) penetrating the interlayer insulating layer and connected to the source/drain pattern; and wherein the source/drain pattern comprises a buffer layer and a main layer on the buffer layer (the epitaxial source/drain regions 92 may include one or more semiconductor material layers, See paragraphs 39 and 51. The examiner notes that the disclosing that the epitaxial source/drain regions may include one or more semiconductor material layers one or more semiconductor material layers discloses the epitaxial source/drain regions 92 may include two semiconductor material layers. The examiner also notes the Wang discloses subsequent semiconductor material layers that form the epitaxial source/drain regions may be deposit over previously deposited semiconductor material layers that make up the epitaxial source/drain regions.).
Wang fails to teach or suggest a first metal layer on the interlayer insulating layer, the first metal layer comprising a plurality of first interconnection lines respectively connected to the gate contact and the active contact; and a second metal layer on the first metal layer, wherein the second metal layer comprises a plurality of second interconnection lines connected to the first metal layer, wherein the main layer comprises an upper portion comprising at least one facet surface, wherein the at least one facet surface is a { 111} plane, and wherein the buffer layer at least partially covers the at least one facet surface. The prior art also fails to provide other relevant disclosures which are properly combinable with Wang to teach or suggest these limitations of claim 16. Therefore, claims 16-20 are allowable.
Response to Arguments
Applicant’s arguments filed on January 26, 2026 with respect to the rejection of claims 5 and 12 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph have been fully considered by they are not persuasive. The examiner notes that the term “substantially” modifies a target, implicitly requiring boundaries at some maximum value above the target and at some minimum value below the target beyond which one is no longer within the “substantially” range. As the Applicant has not provided a definition for these boundaries in the originally filed claims or the originally filed specification, it is unclear whether substantially equal must be within some small percentage of deviation of equal to (such as 0.01%, 0.1%, 1%, 10%, etc.) or within a certain number of units of (such as 1nm, 10nm, 100nm, 1µm, etc.) and specifically which of these possible values defines the boundaries. Therefore, the term is subjective and therefore unclear, and so the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention.
Applicant’s arguments with respect to claims 11-15 have been considered but are moot because the new ground of rejection does not rely on Hasan et al. for teaching vertical alignment and direct contact between buffer layers and a first spacer. Additionally, the examiner notes that applicant’s arguments seem to refer to alignment and direct contact between a third semiconductor pattern and upper side surfaces of buffer layers.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./ Examiner, Art Unit 2899