Detailed Action
1. This office action is in response to communication filed May 13, 2026. Claims 1-3, 5-9, and 11-20 are currently pending and claims 1, 8, and 14 are the independent claims. The application is a divisional application from the original application 17/581,734 dated January 21, 2022.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
3. This Final Office Action is in response to the applicant’s remarks and arguments filed on May 13, 2026.
Claims 1, 3, 5, 7-9, 11, and 13-14 are amended. Claims 4 and 10 have been cancelled. Claims 18-20 are new. Claims 1-3, 5-9, and 11-20 remain pending in the application. Original claims 2, 6, 12, and 15-17 filed on July 27, 2023 are being considered on the merits along with amended claims 1, 3, 5, 7-9, 11, and 13-14 and new claims 18-20.
Response to Arguments
4. Applicant’s arguments, see Remarks, filed June 5, 2026, with respect to the rejections of claims 1-17 under 35 U.S.C. 112, 102, and 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. The rejections made under 35 U.S.C. 101 have been considered, but were not persuasive. However, upon further consideration, a new grounds of rejection is made in view of 35 U.S.C. 103.
On page 6 of the Remarks under section labeled Rejection(s) under 35 U.S.C. 112, the Applicant respectfully submitted that the amendments to independent claim 1 overcome the rejections made in the Non-Final Rejection to claims 1-7.
The Examiner respectfully agrees with the Applicant and has withdrawn the rejections made to claims 1-7 under 35 U.S.C. 112.
On pages 6-8 of the Remarks under section labeled Rejection(s) under 35 U.S.C. 101, the Applicant respectfully submitted that the independent claim limitations do not recite an abstract idea and the independent claims limitations that are additional elements integrate the abstract idea into a practical application.
The Examiner respectfully disagrees with the Applicant regarding the independent claim limitations not reciting an abstract idea. The Examiner has maintained the previous rejections including adding additional rejections for new claims 18-20. The limitation “mapping each logical memory channel in the predetermined number of logical memory channels to a corresponding physical memory channel” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind. The mapping of logical memory channels to corresponding physical memory channels can be done in the human mind or via the support of making a chart on pen and paper. Thus, the Examiner has maintained the rejection in regards to the abstract idea submitted in the independent claims.
The Examiner respectfully disagrees with the Applicant regarding the additional elements integrating the abstract idea into a practical application. Following the amendments to the independent claims, the Applicant asserts the claim as a whole provides an improvement to the technical field of memory systems. Regarding the improvement to the field based on the logical to physical mapping technique for memory systems, the Examiner suggests further amendments to the claims to make this logical to physical mapping technique to truly regard an improvement to the technological field based on the Examiner finding proper prior art to reject the claim with.
On page 8 of the Remarks under section labeled Rejection(s) under 35 U.S.C. 102, the Applicant respectfully submitted that the amendments to independent claims 1 and 8 with some of the subject matter from dependent claims 3 and 4 overcomes the current rejections.
The Examiner respectfully agrees with the Applicant and has withdrawn the rejections made under 35 U.S.C. 102. The Examiner has updated the rejections to be made under 35 U.S.C. 103 following amendments to the independent claims.
On pages 9-11 of the Remarks under section labeled Rejection(s) under 35 U.S.C. 103, the Applicant respectfully submitted that the amendments to independent claims 1 and 8 with some of the subject matter from dependent claims 3 and 4 overcomes the previous rejections.
The Examiner respectfully agrees with the Applicant regarding the previous rejections being overcome by the amendments to the claims by the Applicant. With that being said, the Examiner has updated the rejections made to now include prior art Qiu et al. (U.S. Pub. No. 2023/0133490). The updated rejections appear below in section 5. The Examiner has updated the rejections to overcome the concerns presented by the Applicant such that the combination of Ould-Ahmed-Vall in view of Bellofatto and Qiu disclose all the limitations presented in claims 1-16 and 18-20. The combination of Ould-Ahmed-Vall in view of Bellofatto and Qiu further in view of Loh disclose all the limitations presented in claim 17. Thus, claims 1-20 remain rejected under 35 U.S.C. 103. This Office Action is final.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
5. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As per claim 1, the claim recites “A method comprising: identifying a predetermined number of logical memory channels; identifying a mapping from a logical processor to a corresponding physical processor within an array of physical processors; and mapping each logical memory channel in the predetermined number of logical memory channels to a corresponding physical memory channel, wherein physical memory channels for the corresponding physical processor that are determined to be functional are mapped to logical memory channels for the logical processor that is mapped to the corresponding physical processor.”
Under Step 2A, Prong I, the limitation “identifying a predetermined number of logical memory channels” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person may make a judgement on the number of logical memory channels attached to each logical processor. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Step 2A, Prong I, the limitation “identifying a mapping from a logical processor to a corresponding physical processor within an array of physical processors” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person may make a judgement on the mapping of logical processors to a grouping of physical processors with the help of pen and paper to create a chart representing the mappings for example. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Step 2A, Prong I, the limitation “mapping each logical memory channel in the predetermined number of logical memory channels to a corresponding physical memory channel” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person may map logical memory channels to corresponding physical memory channels via evaluation of memory channel pairings with the help of pen and paper to create a chart representing the mappings for example. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Step 2A, Prong I, the limitation “wherein physical memory channels for the corresponding physical processor that are determined to be functional are mapped to logical memory channels for the logical processor that is mapped to the corresponding physical processor” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person may map logical processors/memory channels to corresponding physical processors/memory channels via evaluation of memory channel pairings with the help of pen and paper to create a chart representing the mappings for example. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular under step 2A Prong II, claim 1 recites the additional elements “physical memory channels” and “physical processors”. The additional elements represent generic computer elements of physical processors and physical memory channels which are recited at a high-level of generality (i.e., as a generic processor performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Under Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract ideas into a practical application, the additional elements amount to mere instructions to apply an exception of receiving data, storing data in memory, gathering specific data from the original data, and applying the exception to perform an action based on the specific data, as discussed above, does not amount to significantly more, and is thus, not an inventive concept. Accordingly, the claim does not appear to be patent eligible under 35 U.S.C. 101. See MPEP 2106.05(f).
As per claim 2, it incorporates the deficiencies of independent claim 1 upon which it depends, and further recites “wherein the physical memory channels include memory tiles on memory dies stacked on a processor die”, which conceptually, with broadest reasonable interpretation, merely provides further clarification as to how the physical memory is physically stacked on top of the processor, which does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 2 fails to correct the deficiencies of claim 1 and is rejected for similar reasoning as claim 1, above.
As per claim 3, it incorporates the deficiencies of independent claim 1 upon which it depends, and further recites “wherein identifying the mapping comprises: determining a predetermined number of functional physical memory channels for the corresponding physical processor; and mapping the predetermined number of functional physical memory channels to the predetermined number of logical memory channels for the logical processor”, which conceptually, with broadest reasonable interpretation, merely provides further clarification as to how logical processors are mapped to physical processors and further how the functional physical memory channels are mapped to the logical memory channels for the logical processor, which does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 3 fails to correct the deficiencies of claim 1 and is rejected for similar reasoning as claim 1, above.
As per claim 5, it incorporates the deficiencies of dependent claim 3 upon which it depends, and further recites “wherein in response to determining that a number of functional physical memory channels within a physical memory location above the corresponding physical processor is less than the predetermined number of functional physical memory channels to be mapped, additional functional physical memory channels within neighboring physical memory locations are mapped to remaining logical memory channels for the logical processor that is mapped to the corresponding physical processor”, which conceptually, with broadest reasonable interpretation, merely provides further clarification as to how the neighboring functional physical memory channels are mapped to the leftover logical memory channels to max out the logical processor’s memory channels, which does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 5 fails to correct the deficiencies of claim 3 and is rejected for similar reasoning as claim 3, above.
As per claim 6, it incorporates the deficiencies of dependent claim 5 upon which it depends, and further recites “wherein the functional physical memory channels within the neighboring physical memory locations that are not currently mapped to other logical memory channels are mapped before the functional physical memory channels within the neighboring physical memory locations that are currently mapped to other logical memory channels”, which conceptually, with broadest reasonable interpretation, merely provides further clarification as to how the neighboring functional physical memory channels without a match are mapped to the logical memory channels without a match before removing mappings between logical/physical memory channels, which does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 6 fails to correct the deficiencies of claim 5 and is rejected for similar reasoning as claim 5, above.
As per claim 7, it incorporates the deficiencies of independent claim 1 upon which it depends, and further recites “comprising storing results of the mapping of the logical memory channel to the corresponding physical memory channel in a table (analyzed under Step 2A Prong II & Step 2B as additional element)”, which conceptually, with broadest reasonable interpretation, merely provides further clarification as to how the mappings of the physical memory channels to the logical memory channels are stored in a table, which does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 7 fails to correct the deficiencies of claim 1 and is rejected for similar reasoning as claim 1, above.
Claim 8 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim recites the same claimed language as claim 1 above other than being a non-transitory computer-readable storage medium claim rather than a method claim. Claim 8 is rejected under 35 U.S.C. 101 for the same reasons as claim 1 above.
Claim 9 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim recites the same claimed language as claim 3 above other than being a non-transitory computer-readable storage medium claim rather than a method claim. Claim 9 is rejected under 35 U.S.C. 101 for the same reasons as claim 3 above.
Claim 11 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim recites the same claimed language as claim 5 above other than being a non-transitory computer-readable storage medium claim rather than a method claim. Claim 11 is rejected under 35 U.S.C. 101 for the same reasons as claim 5 above.
Claim 12 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim recites the same claimed language as claim 6 above other than being a non-transitory computer-readable storage medium claim rather than a method claim. Claim 12 is rejected under 35 U.S.C. 101 for the same reasons as claim 6 above.
Claim 13 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim recites the same claimed language as claim 7 above other than being a non-transitory computer-readable storage medium claim rather than a method claim. Claim 13 is rejected under 35 U.S.C. 101 for the same reasons as claim 7 above.
Claim 14 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim recites the same claimed language as claims 1 and 3 above other than being a system claim rather than a method claim. Claim 14 is rejected under 35 U.S.C. 101 for the same reasons as claims 1 and 3 above.
As per claim 15, it incorporates the deficiencies of independent claim 14 upon which it depends, and further recites “wherein the plurality of hardware processors includes one or more streaming multiprocessors”, which conceptually, with broadest reasonable interpretation, merely provides further clarification as to how the processor(s) include streaming multiprocessor(s), which does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 15 fails to correct the deficiencies of claim 14 and is rejected for similar reasoning as claim 14, above.
As per claim 16, it incorporates the deficiencies of independent claim 14 upon which it depends, and further recites “wherein the plurality of hardware processors includes one or more central processing units (CPUs)”, which conceptually, with broadest reasonable interpretation, merely provides further clarification as to how the processor(s) include CPU(s), which does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 16 fails to correct the deficiencies of claim 14 and is rejected for similar reasoning as claim 14, above.
As per claim 17, it incorporates the deficiencies of independent claim 14 upon which it depends, and further recites “wherein each of the data storage entities includes a memory block comprising an individual memory sub-array located in a stacked configuration per-layer on top of one of the plurality of hardware processors”, which conceptually, with broadest reasonable interpretation, merely provides further clarification as to how the memory is physically stacked on top of the hardware processors, which does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 17 fails to correct the deficiencies of claim 14 and is rejected for similar reasoning as claim 14, above.
As per claim 18, it incorporates the deficiencies of independent claim 1 upon which it depends, and further recites “wherein the physical memory channels for the corresponding physical processor are configured to access a memory coupled to the corresponding physical processor”, which conceptually, with broadest reasonable interpretation, merely provides further clarification as to the physical memory channels that are attached to processors and memory to handle the dispersion of data back and forth between the processor or memory, which does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 18 fails to correct the deficiencies of claim 1 and is rejected for similar reasoning as claim 1, above.
As per claim 19, it incorporates the deficiencies of independent claim 1 upon which it depends, and further recites “testing the physical memory channels for the corresponding physical processor to determine that the physical memory channels for the corresponding physical processor are functional”, which conceptually, with broadest reasonable interpretation, merely provides further clarification as to confirming the physical memory channel’s functionality to ensure usage of memory channels is not hindered, which does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 19 fails to correct the deficiencies of claim 1 and is rejected for similar reasoning as claim 1, above.
As per claim 20, it incorporates the deficiencies of independent claim 1 upon which it depends, and further recites “receiving a request for a memory access; and implementing the memory access based on the mapping of the logical memory channels to the physical memory channels”, which conceptually, with broadest reasonable interpretation, merely provides further clarification as to the handling of memory access requests via the mappings between logical and physical memory channels, which does not integrate the abstract idea/mental process into a practical application and is not significantly more than the judicial exception. Therefore, claim 20 fails to correct the deficiencies of claim 1 and is rejected for similar reasoning as claim 1, above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ould-Ahmed-Vall et al. (U.S. Pub. No. 2020/0364823) – hereinafter “Ould-Ahmed-Vall”, in view of Bellofatto et al. (U.S. Pub. No. 2013/0031418) – hereinafter “Bellofatto” and Qiu et al. (U.S. Pub. No. 2023/0133490) – hereinafter “Qiu”.
Regarding independent claim 1, Ould-Ahmed-Vall discloses a method comprising:
identifying a predetermined number of logical memory channels; and ([0060] “In one embodiment the memory crossbar 216 can use virtual channels to separate traffic streams between the clusters 214A-214N and the partition units 220A-220N.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual memory channels exist to separate traffic between the clusters and partition units.
mapping each of the predetermined number of logical memory channels to a corresponding physical memory channel, (Claim 10, “The apparatus of claim 1 wherein a memory interface comprises a physical memory channel, and wherein one or more virtual memory channels are to be associated with a physical memory channel.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual memory channels are mapped/associated with the corresponding physical memory channel.
wherein physical memory channels … are mapped to logical memory channels for the logical processor that is mapped to the corresponding physical processor. ([0088] “As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to a particular memory 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the “effective address” space) is distributed among all of the various physical memories. For example, processor memories 401-402 may each comprise 64 GB of the system memory address space and GPU memories 420-423 may each comprise 32 GB of the system memory address space (resulting in a total of 256 GB addressable memory in this example).” and Claim 10, “The apparatus of claim 1 wherein a memory interface comprises a physical memory channel, and wherein one or more virtual memory channels are to be associated with a physical memory channel.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the physical memory channels are associated with the corresponding physical memory and are mapped/associated with the corresponding virtual memory channel.
Ould-Ahmed-Vall does not explicitly disclose:
identifying a mapping from the logical processor to a corresponding physical processor within an array of physical processors;
wherein physical memory channels for the corresponding physical processor that are determined to be functional …
However, Bellofatto discloses:
identifying a mapping from the logical processor to a corresponding physical processor within an array of physical processors; (Fig. 4 and [0057] “FIG. 4 illustrates how the encoded information (e.g., test results of processor cores) is used. The information encoded in the on-chip non-volatile memory device (or, if present, the information encoded in the external non-volatile storage device in FIG. 2B) is read, e.g., by the on-chip logic, to identify failed processor core(s), if any. In the example of FIG. 4, the "N+1" processors on a multiprocessor semiconductor chip includes a series of tested-good processors (i.e., processors that have passed all the tests) (301) and includes a failed processor (302), schematically identified by an `X`”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the physical processor core IDs 300 are mapped to the logical processor core IDS 310.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add identifying a mapping from the logical processor to a corresponding physical processor within an array of physical processors as seen in Bellofatto's invention into Ould-Ahmed-Vall's invention because these modifications allow the simple substitution of one known element for another to obtain predictable results such that logical processors are mapped to physical processors in the same manner that logical memory channels are mapped to physical memory channels.
In addition, Qiu discloses:
wherein physical memory channels for the corresponding physical processor that are determined to be functional … (Fig. 1 wherein memory channels attach memory chips to corresponding cores of a processor and [0105] “After completing memory training for the memory channel 1, the memory chip 0, and the memory chip 1, the core 0 may further perform memory testing on the memory channel 1, the memory chip 0, and the memory chip 1, to verify a memory training result. Generally, memory testing includes operations such as margin testing, eye scan, storage testing, and storage cleanup.” and [0142] “An instruction included in the training function information corresponds to a memory training related operation, and the second processor core 321-1 may perform memory training on the memory channel 1 by running the training function information. An instruction included in the testing function information corresponds to a memory testing related operation, and the second processor core 321-1 performs memory testing on the memory channel 1 by running the testing function information.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the memory channels are tested to verify the functionality of the connections between memory channels, memory chips, and cores.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein physical memory channels for the corresponding physical processor that are determined to be functional as seen in Qiu's invention into Ould-Ahmed-Vall's invention because these modifications allow combining prior art elements according to known methods to yield predictable results such that the memory channels are tested to verify their functionality before use to retool the allocations of memory channels if any are not functional.
Regarding claim 2, Ould-Ahmed-Vall discloses the method of claim 1, wherein the physical memory channels include memory tiles on memory dies stacked on a processor die. ([0087] “By way of example, and not limitation, the processor memories 401-402 and GPU memories 420-423 may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), Graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or High Bandwidth Memory (HBM) and/or may be non-volatile memories such as 3D XPoint or Nano-Ram”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the processor/GPU memories include stacked DRAMs.
Regarding claim 3, Ould-Ahmed-Vall discloses the method of claim 1, comprising:
determining a predetermined number of functional physical memory channels for the corresponding physical processor; and ([0088] “As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to a particular memory 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the “effective address” space) is distributed among all of the various physical memories. For example, processor memories 401-402 may each comprise 64 GB of the system memory address space and GPU memories 420-423 may each comprise 32 GB of the system memory address space (resulting in a total of 256 GB addressable memory in this example).” and Claim 10, “The apparatus of claim 1 wherein a memory interface comprises a physical memory channel, and wherein one or more virtual memory channels are to be associated with a physical memory channel.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the physical memory channels are associated with the corresponding physical memory and their coupled processors.
mapping the predetermined number of functional physical memory channels to the predetermined number of logical memory channels for the logical processor. (Claim 10, “The apparatus of claim 1 wherein a memory interface comprises a physical memory channel, and wherein one or more virtual memory channels are to be associated with a physical memory channel.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual memory channels are mapped/associated with the corresponding physical memory channel.
Regarding claim 5, Ould-Ahmed-Vall discloses the method of claim 3, wherein … additional functional physical memory channels within neighboring physical memory locations are mapped to remaining logical memory channels for the logical processor that is mapped to the corresponding physical processor. (Claim 10, “The apparatus of claim 1 wherein a memory interface comprises a physical memory channel, and wherein one or more virtual memory channels are to be associated with a physical memory channel.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual memory channels are mapped/associated with the corresponding physical memory channel.
Ould-Ahmed-Vall does not explicitly disclose:
… wherein in response to determining that a number of functional physical [processors] … is less than the predetermined number of functional physical [processors] to be mapped, additional functional [processors] within neighboring physical memory locations are mapped to remaining logical [processors] … that is mapped to the corresponding physical processor.
However, Bellofatto discloses:
… wherein in response to determining that a number of functional physical [processors] … is less than the predetermined number of functional physical [processors] to be mapped, additional functional [processors] within neighboring physical memory locations are mapped to remaining logical [processors] … that is mapped to the corresponding physical processor. (Fig. 7B and [0072] “FIGS. 7A-7B illustrate two alternative extensions of the system and method in one embodiment, e.g., by implementing dual redundancies--i.e. where two of the physical processor cores are redundant processor cores, so that the multiprocessor semiconductor chip can allow two processor cores to fail. The scheme of FIG. 7A divides the multiprocessor semiconductor chip in two sections, with one redundant processor core for each section. Each section independently implements the previously described scheme of FIG. 4. FIG. 7B illustrates a scheme that applies the dual redundancy globally, i.e. across all processor cores on the semiconductor chip. The scheme shown in FIG. 7B is more flexible, and will generally result in better yield than the scheme of FIG. 7A, at the cost of more logic complexity in the on-chip logic.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the physical processor core IDs are mapped to logical processor core IDs only if they are found to not be faulty as those are shut down.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein in response to determining that a number of functional physical [processors] … is less than the predetermined number of functional physical [processors] to be mapped, additional functional [processors] within neighboring physical memory locations are mapped to remaining logical [processors] … that is mapped to the corresponding physical processor as seen in Bellofatto's invention into Ould-Ahmed-Vall's invention because these modifications allow the use of a known technique to improve similar devices in the same way such that the mapping of physical processors to logical processors based on locality can be implemented in the same manner for mapping physical memory channels to logical memory channels.
Regarding claim 6, Ould-Ahmed-Vall discloses the method of claim 5, wherein the functional physical memory channels … are mapped to other logical memory channels. (Claim 10, “The apparatus of claim 1 wherein a memory interface comprises a physical memory channel, and wherein one or more virtual memory channels are to be associated with a physical memory channel.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual memory channels are mapped/associated with the corresponding physical memory channel.
Ould-Ahmed-Vall does not explicitly disclose:
… wherein the functional physical [processors] within the neighboring physical memory locations that are not currently mapped to other logical [processors] are mapped before the functional physical [processors] within the neighboring physical memory locations that are currently mapped to other logical [processors].
However, Bellofatto discloses:
… wherein the functional physical [processors] within the neighboring physical memory locations that are not currently mapped to other logical [processors] are mapped before the functional physical [processors] within the neighboring physical memory locations that are currently mapped to other logical [processors]. (Fig. 7B and [0072] “FIGS. 7A-7B illustrate two alternative extensions of the system and method in one embodiment, e.g., by implementing dual redundancies--i.e. where two of the physical processor cores are redundant processor cores, so that the multiprocessor semiconductor chip can allow two processor cores to fail. The scheme of FIG. 7A divides the multiprocessor semiconductor chip in two sections, with one redundant processor core for each section. Each section independently implements the previously described scheme of FIG. 4. FIG. 7B illustrates a scheme that applies the dual redundancy globally, i.e. across all processor cores on the semiconductor chip. The scheme shown in FIG. 7B is more flexible, and will generally result in better yield than the scheme of FIG. 7A, at the cost of more logic complexity in the on-chip logic.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the physical processor core IDs are mapped to logical processor core IDs only if they are found to not be faulty as those are shut down rather than replacing others.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein the functional physical [processors] within the neighboring physical memory locations that are not currently mapped to other logical [processors] are mapped before the functional physical [processors] within the neighboring physical memory locations that are currently mapped to other logical [processors] as seen in Bellofatto's invention into Ould-Ahmed-Vall's invention because these modifications allow the use of a known technique to improve similar devices in the same way such that the mapping of physical processors to logical processors based on unmapped physical processors getting precedent over currently mapped processors and can be implemented in the same manner for mapping physical memory channels to logical memory channels.
Regarding claim 7, Ould-Ahmed-Vall discloses the method of claim 1, comprising:
… the mapping of the logical memory channel to the corresponding physical memory channel … (Claim 10, “The apparatus of claim 1 wherein a memory interface comprises a physical memory channel, and wherein one or more virtual memory channels are to be associated with a physical memory channel.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual memory channels are mapped/associated with the corresponding physical memory channel.
Ould-Ahmed-Vall does not explicitly disclose:
comprising storing results of the mapping … in a table.
However, Bellofatto discloses:
comprising storing results of the mapping of the logical [processor] to the corresponding physical [processor] in a table. ([0020] “In a further embodiment, the on-chip non-volatile memory device in the multiprocessor semiconductor chip includes a set of multiple registers. Each register in the on-chip non-volatile memory device stores a different physical-to-logical mapping of IDs of the primary processor cores and the redundant processor cores.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the set of registers store the mappings in a table.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add comprising storing results of the mapping of the logical memory channel to the corresponding physical memory channel in a table as seen in Bellofatto's invention into Ould-Ahmed-Vall's invention because these modifications allow the simple substitution of one known element for another to obtain predictable results such that the storing of logical processor to physical processor mappings are substituted for logical memory channel to physical memory channel mappings to be referenced by the working system.
Regarding claim 8, it is a non-transitory computer-readable storage medium claim having the same limitations as cited in method claim 1. Thus, claim 8 is also rejected under the same rationale as addressed in the rejection of claim 1 above.
Regarding claim 9, it is a non-transitory computer-readable storage medium claim having the same limitations as cited in method claim 3. Thus, claim 9 is also rejected under the same rationale as addressed in the rejection of claim 3 above.
Regarding claim 11, it is a non-transitory computer-readable storage medium claim having the same limitations as cited in method claim 5. Thus, claim 11 is also rejected under the same rationale as addressed in the rejection of claim 5 above.
Regarding claim 12, it is a non-transitory computer-readable storage medium claim having the same limitations as cited in method claim 6. Thus, claim 12 is also rejected under the same rationale as addressed in the rejection of claim 6 above.
Regarding claim 13, it is a non-transitory computer-readable storage medium claim having the same limitations as cited in method claim 7. Thus, claim 13 is also rejected under the same rationale as addressed in the rejection of claim 7 above.
Regarding claim 14, it is a system claim having the same limitations as cited in method claim 1. Thus, claim 14 is also rejected under the same rationale as addressed in the rejection of claim 1 above.
Regarding claim 15, Ould-Ahmed-Vall discloses the system of claim 14, wherein the plurality of hardware processors includes one or more streaming multiprocessors. (Abstract, “Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple precisions.”)
Regarding claim 16, Ould-Ahmed-Vall discloses the system of claim 14, wherein the plurality of hardware processors includes one or more central processing units (CPUs). ([0083] “[0083] Persons skilled in the art will understand that the architecture described in FIG. 1, 2A-2D, and 3A-3B are descriptive and not limiting as to the scope of the present embodiments. Thus, the techniques described herein may be implemented on any properly configured processing unit, including, without limitation, one or more mobile application processors, one or more desktop or server central processing units (CPUs) including multi-core CPUs, one or more parallel processing units, such as the parallel processing unit 202 of FIG. 2A, as well as one or more graphics processors or special purpose processing units, without departure from the scope of the embodiments described herein.”)
Regarding claim 18, Ould-Ahmed-Vall discloses the method of claim 1, but does not explicitly disclose:
wherein the physical memory channels for the corresponding physical processor are configured to access a memory coupled to the corresponding physical processor.
However, Qiu discloses:
wherein the physical memory channels for the corresponding physical processor are configured to access a memory coupled to the corresponding physical processor. (Fig. 1 wherein memory channels attach memory chips to corresponding cores of a processor and [0086] “In an embodiment, as shown in FIG. 1, the memory controller 102 may include at least one memory channel, for example, a memory channel 1 to a memory channel M, where M is an integer greater than or equal to 1. Each memory channel may be connected to at least one memory chip, and each memory channel can control at least one memory chip connected to the memory channel.” and [0092] “The core 0 may sequentially initialize, in a preset order, the M memory channels in the memory controller 102 and the memory chip 0 to the memory chip L−1. For example, the core 0 may first initialize the memory channel 1, the memory chip 0, and the memory chip 1, then initialize the memory channel 2, a memory chip 2, and a memory chip 3, . . . , and finally initialize the memory channel M, the memory chip L−2, and the memory chip L−1.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the memory channels included with the memory controller are connected to memory chips and processor core(s) to access memory for the processor.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein the physical memory channels for the corresponding physical processor are configured to access a memory coupled to the corresponding physical processor as seen in Qiu's invention into Ould-Ahmed-Vall's invention because these modifications allow combining prior art elements according to known methods to yield predictable results such that the physical memory channels paired to physical processor carry the memory access request to the processor.
Regarding claim 19, Ould-Ahmed-Vall discloses the method of claim 1, but does not explicitly disclose:
testing the physical memory channels for the corresponding physical processor to determine that the physical memory channels for the corresponding physical processor are functional.
However, Qiu discloses:
testing the physical memory channels for the corresponding physical processor to determine that the physical memory channels for the corresponding physical processor are functional. (Fig. 1 wherein memory channels attach memory chips to corresponding cores of a processor and [0105] “After completing memory training for the memory channel 1, the memory chip 0, and the memory chip 1, the core 0 may further perform memory testing on the memory channel 1, the memory chip 0, and the memory chip 1, to verify a memory training result. Generally, memory testing includes operations such as margin testing, eye scan, storage testing, and storage cleanup.” and [0142] “An instruction included in the training function information corresponds to a memory training related operation, and the second processor core 321-1 may perform memory training on the memory channel 1 by running the training function information. An instruction included in the testing function information corresponds to a memory testing related operation, and the second processor core 321-1 performs memory testing on the memory channel 1 by running the testing function information.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the memory channels are tested to verify the functionality of the connections between memory channels, memory chips, and cores.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add testing the physical memory channels for the corresponding physical processor to determine that the physical memory channels for the corresponding physical processor are functional as seen in Qiu's invention into Ould-Ahmed-Vall's invention because these modifications allow combining prior art elements according to known methods to yield predictable results such that the memory channels are tested to verify their functionality before use to retool the allocations of memory channels if any are not functional.
Regarding claim 20, Ould-Ahmed-Vall discloses the method of claim 1, further comprising:
receiving a request for a memory access; and ([0058] “Each of the one or more instances of the parallel processing unit 202 can couple with parallel processor memory 222. The parallel processor memory 222 can be accessed via the memory crossbar 216, which can receive memory requests from the processing cluster array 212 as well as the I/O unit 204.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the processor memory requests are received from the processing cluster array or I/O unit.
implementing the memory access based on the mapping of the logical memory channels to the physical memory channels. ([0058] “The memory crossbar 216 can access the parallel processor memory 222 via a memory interface 218. The memory interface 218 can include multiple partition units (e.g., partition unit 220A, partition unit 220B, through partition unit 220N) that can each couple to a portion (e.g., memory unit) of parallel processor memory 222.” and Claim 10, “The apparatus of claim 1 wherein a memory interface comprises a physical memory channel, and wherein one or more virtual memory channels are to be associated with a physical memory channel.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual memory channels are mapped/associated with the corresponding physical memory channel and as such implement the memory access via a memory interface.
7. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ould-Ahmed-Vall et al. (U.S. Pub. No. 2020/0364823) – hereinafter “Ould-Ahmed-Vall”, in view of Bellofatto et al. (U.S. Pub. No. 2013/0031418) – hereinafter “Bellofatto” and Qiu et al. (U.S. Pub. No. 2023/0133490) – hereinafter “Qiu”, and further in view of Loh (NPL - 3D-Stacked Memory Architectures for Multi-Core Processors).
Regarding claim 3, Ould-Ahmed-Vall discloses the method of claim 14, but does not explicitly disclose:
wherein each of the data storage entities includes a memory block comprising an individual memory sub-array located in a stacked configuration per-layer on top of one of the plurality of hardware processors.
However, Loh discloses:
wherein each of the data storage entities includes a memory block comprising an individual memory sub-array located in a stacked configuration per-layer on top of one of the plurality of hardware processors. (Section 1 Introduction, “It is well known that DRAM access latencies have not decreased at the same rate as microprocessor cycle times. This leads to the situation where the relative memory access time (in CPU cycles) keeps increasing from one generation to the next. This problem is popularly referred to as the Memory Wall [41]. Three-dimensional (3D) die-stacking has received a great deal of recent attention in the computer architecture community [5, 20, 26, 27, 29, 32]. 3D stacking enables the construction of circuits using multiple layers of active silicon bonded with low-latency, high-bandwidth and very dense vertical interconnects [8, 14]. 3D stacking also enables mixing dissimilar process technologies such as highspeed CMOS with high-density DRAM. Stacking DRAM directly on top of a processor is a natural way to attack the Memory Wall problem.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the hardware processor includes stacking memory in a layer on top of a core to achieve low latency, high bandwidth, and very dense vertical interconnects.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein each of the data storage entities includes a memory block comprising an individual memory sub-array located in a stacked configuration per-layer on top of one of the plurality of hardware processors as seen in Loh's invention into Ould-Ahmed-Vall's invention because these modifications allow combining prior art elements according to known methods to yield predictable results such that hardware processors have memory blocks physically stacked on top of the processors to specifically achieve low latency, high bandwidth, and very dense vertical interconnects.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Such prior art includes Mohan et al. (U.S. Pub. No. 2016/0019160) which discloses mapping logical addresses to physical addresses residing on a memory channel and Lai et al. (U.S. Pub. No. 2019/0361627) which discloses memory channels handling mapping table commands.
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
When responding to this Office action, applicant is advised to provide the line and page numbers in the application and/or reference(s) cited to assist in locating the appropriate paragraphs.
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/D.T./Examiner, Art Unit 2198
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
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