DETAILED ACTION
This Office Action is in response to the Request for Continued Examination and Amendments filed 13 May 2026. Claims 1, 5-20 are pending in this applications. Claims 1, 5-10, 19 are examined in this Office Action, and Claim 11-18, 20 remain withdrawn from consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 13 May 2026 has been entered.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-6. 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et. al (US 2023/0268346 A1) (of record) in view of Zhang et. al (US 2023/0126267 A1) (of record).
Regarding Claim 1, Chiu discloses (as shown in Fig. 6) A semiconductor structure ([0011] Referring to FIGS. 1-6, FIGS. 1-6 illustrate a method for fabricating a semiconductor device) comprising:
A middle/high voltage device region ([0011] a high voltage (HV) region 14) including a flat top surface (See Fig. 6, showing a flat surface in the HV region 14);
A low voltage device region ([0011] a low-voltage (LV) region 16) including a plurality of fin structures ([0012] a plurality of fin-shaped structures 20 are formed on the substrate 12 of the LV region 16) therein,
wherein the plurality of fin structures comprises a first fin structure (See An. Fig. 6, showing the first fin structure) closest to the middle/high voltage device region (14), (See An. Fig. 6)
and the semiconductor structure further comprises two insulating layers ([0020] STI 32) adjacent to two opposite sides of the first fin structure, (See An. Fig. 6, first fin structure)
wherein widths of the two insulating layers (32) on the two opposite sides of the first fin structure (See An. Fig. 6, first fin structure) are different; (See An. Fig. 6, showing the STI region 32 closer to the HV region 14 is wider than the STI region 32 farther from the HV region 14)
a protruding part (See An. Fig. 6, Protruding Portion) located at the boundary of the middle/high voltage device (14) region, (See An. Fig. 6)
wherein a top surface of the protruding part (See An. Fig. 6, Protruding Portion) is flat, (See An. Fig. 6)
and the top surface of the protruding part (See An. Fig. 6, Protruding Portion) is aligned with the flat top surface of the middle/high voltage device region (14); (See An. Fig. 6)
and a deep trench ([0018] At this stage, the remaining insulating layer 36 around the base 18 on the HV region 14 preferably becomes a STI 38) located in the middle/high voltage device region (14) and adjacent to the protruding part (See An. Fig. 6, Protruding Portion). (See An. Fig. 6, showing the STI 38 is deeper than the STI 32. Furthermore, An, Fig. 6 shows that an STI 38 is located on the side of the protruding portion close to the HV region 14)
wherein a depth of the deep trench (38) is greater than a depth of each of the two insulating layers (32), ([0017] on the HV region 14 to form a plurality of trenches 34 as the depth of the trenches 34 is substantially greater than the depth of the trenches between the fin-shaped structures 20.)
and a top surface of the deep trench (38) is higher than a top surface of each of the two insulating layers (32). ([0018] the top surfaces of the STI 38 and the STI 32 on the LV region 16 are coplanar… [0020] Next, as shown in FIG. 6, it would be desirable to first remove the hard mask 26 and liners 22, 24 on the HV region 14 and LV region 16 and part of the STI 32 on the LV region 16) (See An. Fig. 6, showing the top surface of the STI 32 below the top surface of the STI 38)
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However, Chiu fails to disclose that the protruding portion (See An. Fig. 14, Protruding Portion) is also at the boundary of the low voltage region (16).
Chiu does not disclose the arrangement of the HV region (14) and the LV region (16) relative to each other. Furthermore, Chiu shows a break between the disclosed HV region (14) and the LV region (16) (See Fig. 14). Therefore, it is not obvious that the protruding portion would be adjacent to the boundary of the low voltage region (16)
Zhang discloses (as shown in Fig. 4P) A semiconductor structure ([0076] Refer to FIGS. 4A-4P, a semiconductor device is further provided by the present disclosure) comprising:
a middle/high voltage device region ([0077] the substrate 10 may include a first region (region A) … wherein the region A includes a high-voltage device region) including a flat top surface; (See Fig. 4P, showing the top surface of the substrate 10 in the high-voltage device region A has a flat top surface)
a low voltage device region ([0077] the substrate 10 may include … a second region (region B) … the region B includes a low-voltage device region (the devices therein having an operating voltage lower than that of the devices in the high-voltage device region)) including a plurality of fin structures therein; ([0074] the low-voltage device region further includes the first low-voltage zone b1 and the second low-voltage zone b2. For a better illustration of the device structures formed in the first low-voltage zone b1 and the second low-voltage zone b2, refer to FIG. 4P, the FinFET in the first low-voltage zone and the FinFET in the second low-voltage zone)
and a protruding part (See Ann. Fig. 4P; Protruding Portion) is located at the boundary of the middle/high voltage device (A) region and the low voltage device region (B), (See Ann. Fig. 4P, showing a portion of the substrate 10 separating the high-voltage device region A from the low voltage device B region between isolation trenches 13A and 13b1)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the teachings of Chiu and Zhang in order to have the high voltage region (14) and low voltage region (16) of Chiu adjacent to each other such that the protruding portion is between the high voltage region (14) and low voltage region (16). This design minimizes the footprint of the devices by minimizing the space used.
Regarding Claim 5, Chiu further discloses (as shown in Fig. 6) wherein a bottom surface of each fin structure (20) is aligned with a bottom surface of each of the two insulating layers (32). (See Fig. 6)
Regarding Claim 6, Chiu further discloses (as shown in Fig. 6) wherein a width of the protruding part (See An. Fig. 6, Protruding Portion) is larger than a width of each fin structure (20) when viewed from a sectional view. (See Fig. 6)
Regarding Claim 19, Chiu discloses (as shown in Fig. 6) A semiconductor structure comprising:
a planar device region ([0011]a high voltage (HV) region 14) ([0012] [0012] Next, a base 18 is formed on the HV region 14) including a flat top surface (See Fig. 6, showing a flat surface in the HV region 14);
a fin structure device region ([0011] a low-voltage (LV) region 16), which contains a plurality of fin structures ([0012] a plurality of fin-shaped structures 20 are formed on the substrate 12 of the LV region 16),
wherein the plurality of fin structures comprises a first fin structure (See An. Fig. 6, showing the first fin structure) closest to the planar device region (14), (See An. Fig. 6)
and the semiconductor structure further comprises two insulating layers ([0020] STI 32) adjacent to two opposite sides of the first fin structure, (See An. Fig. 6, first fin structure)
wherein widths of the two insulating layers (32) on the two opposite sides of the first fin structure (See An. Fig. 6, first fin structure) are different; (See An. Fig. 6, showing the STI region 32 closer to the HV region 14 is wider than the STI region 32 farther from the HV region 14)
a protruding part (See An. Fig. 6, Protruding Portion) located at the boundary of the planar device region (14), (See An. Fig. 6)
wherein a top surface of the protruding part (See An. Fig. 6, Protruding Portion) is flat (See An. Fig. 6)
and is aligned with the flat top surface of the planar device region (14); (See An. Fig. 6)
and a deep trench ([0018] At this stage, the remaining insulating layer 36 around the base 18 on the HV region 14 preferably becomes a STI 38) located adjacent to the protruding part (See An. Fig. 6, Protruding Portion). (See An. Fig. 6, showing the STI 38 is deeper than the STI 32. Furthermore, An, Fig. 6 shows that an STI 38 is located on the side of the protruding portion close to the HV region 14)
wherein a depth of the deep trench (38) is greater than a depth of each of the two insulating layers (32), ([0017] on the HV region 14 to form a plurality of trenches 34 as the depth of the trenches 34 is substantially greater than the depth of the trenches between the fin-shaped structures 20.)
and a top surface of the deep trench (38) is higher than a top surface of each of the two insulating layers (32). ([0018] the top surfaces of the STI 38 and the STI 32 on the LV region 16 are coplanar… [0020] Next, as shown in FIG. 6, it would be desirable to first remove the hard mask 26 and liners 22, 24 on the HV region 14 and LV region 16 and part of the STI 32 on the LV region 16) (See An. Fig. 6, showing the top surface of the STI 32 below the top surface of the STI 38)
However, Chiu fails to disclose that the protruding portion (See An. Fig. 14, Protruding Portion) is also at the boundary of the low voltage region (16).
Chiu does not disclose the arrangement of the HV region (14) and the LV region (16) relative to each other. Furthermore, Chiu shows a break between the disclosed HV region (14) and the LV region (16) (See Fig. 14). Therefore, it is not obvious that the protruding portion would be adjacent to the boundary of the low voltage region (16)
Zhang discloses (as shown in Fig. 4P) A semiconductor structure ([0076] Refer to FIGS. 4A-4P, a semiconductor device is further provided by the present disclosure) comprising:
a middle/high voltage device region ([0077] the substrate 10 may include a first region (region A) … wherein the region A includes a high-voltage device region) including a flat top surface; (See Fig. 4P, showing the top surface of the substrate 10 in the high-voltage device region A has a flat top surface)
a low voltage device region ([0077] the substrate 10 may include … a second region (region B) … the region B includes a low-voltage device region (the devices therein having an operating voltage lower than that of the devices in the high-voltage device region)) including a plurality of fin structures therein; ([0074] the low-voltage device region further includes the first low-voltage zone b1 and the second low-voltage zone b2. For a better illustration of the device structures formed in the first low-voltage zone b1 and the second low-voltage zone b2, refer to FIG. 4P, the FinFET in the first low-voltage zone and the FinFET in the second low-voltage zone)
and a protruding part (See Ann. Fig. 4P; Protruding Portion) is located at the boundary of the middle/high voltage device (A) region and the low voltage device region (B), (See Ann. Fig. 4P, showing a portion of the substrate 10 separating the high-voltage device region A from the low voltage device B region between isolation trenches 13A and 13b1)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the teachings of Chiu and Zhang in order to have the high voltage region (14) and low voltage region (16) of Chiu adjacent to each other such that the protruding portion is between the high voltage region (14) and low voltage region (16). This design minimizes the footprint of the devices by minimizing the space used.
Claim(s) 7, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chui in view of Zhang as applied to claim 1 above, and further in view of Phao et. al (US 2017/0025533 A1) (of record).
Regarding Claim 7, Chui further discloses (as shown in Fig. 6) the low voltage device region (16) contains a plurality of second elements, ([0012] a plurality of fin-shaped structures 20 are formed on the substrate 12 of the LV region 16)
Zhang further discloses (as shown in Fig. 4P) wherein the middle/high voltage device (A) region contains a plurality of first elements ([0077] wherein the region A includes a high-voltage device region and may be used to form planar transistor in accordance with the implementation of the present disclosure, and the region B includes a low-voltage device region (the devices therein having an operating voltage lower than that of the devices in the high-voltage device region)),
and the low voltage device region (B) contains a plurality of second elements, ([0077] the region B includes a low-voltage device region (the devices therein having an operating voltage lower than that of the devices in the high-voltage device region)) ([0062] so that the portion of the substrate 10 protruding from two adjacent trench isolation structures 13B′ functions as a fin for FinFET in the region B, i.e., the semiconductor protrusion 10B in the region B functions as the fin for FinFET.)
However, Chui and Zhang fail to disclose each of the first elements has a driving voltage greater than 10 volts, each of the second elements has a driving voltage less than 1.5 volts.
Phoa discloses (as shown in Fig. 4E) a semiconductor device ([0036] FIG. 4A-4E, which are cross-sectional views of a high voltage FET and a FinFET) comprising
a middle/high voltage region ([0034] high voltage FET 102) and a low voltage region ([0020] FinFET gate stack operable for controlling conductance of the FinFET at low gate voltages)
wherein the middle/high voltage device region contains a first element ([0034] high voltage FET 102),
each of the first elements (102) has a driving voltage greater than 10 volts, ([0028] These geometries along with arbitrarily thick gate dielectric, allow high voltage transistor 102 to have any desired high voltage operating point (e.g., with gate-drain breakdown voltage exceeding 10V))
and the low voltage device region contains a plurality of second elements ([0028] FinFET 103),
each of the second elements (103) has a driving voltage less than 1.5 volts. ([0028] a minimum design rule FinFET 103 that has a low voltage operating point (e.g., gate-drain breakdown voltage well below 5V).)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application, based on the teachings of Phoa, to have the driving voltage of the second elements (FinFET 103) be less than 1.5 V. Phoa teaches that the gate-drain breakdown voltage of the FinFET is well below 5V ([0028]). This overlaps with the claimed range of <1.5 V. Furthermore, Phoa teaches that the FinFET 103 is a minimum design rule FET ([0028] while remaining completely compatible with a minimum design rule FinFET 103); minimum design rule FinFETs typically have a driving voltage below 1.5 V.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the teachings of Chui in view of Zhang and Phoa. Chui in view of Zhang teaches a design for a combination of high-voltage and low-voltage transistor regions. Phoa also teaches a device having high-voltage and low-voltage transistor regions. Zhang does not disclose the driving voltages of the high-voltage and low-voltage regions. Phoa teaches operating the high-voltage device at a voltage greater than 10 V ([0028]) and operating the FinFET at the minimum design rule voltage. Therefore, it would be obvious for the high-voltage device and low-voltage devices of Zhang to be operated at the same voltages as the high-voltage and low-voltage devices of Phoa.
Regarding Claim 10, Chui fails to disclose wherein each of the first elements and each of the second elements are fabricated by nanometer processes with different precisions.
Zhang further discloses (as shown in Fig. 4P) wherein each of the first elements (planar transistor) and each of the second elements (FinFET) are fabricated by nanometer processes with different precisions. ([0034] when scaled down to 22 nm, may cause severe short channel effect in the planar transistor structures and affect device performance badly. To solve this problem, a Fin Field-Effect Transistor (FinFET) is used instead in the existing low-voltage device region, while the planar transistor is still used in the high-voltage device region due to the great difficulty of the process of forming FinFET satisfying the performance requirements of the high-voltage device region.)
Chui and Zhang are both directed to a combination of high voltage and low voltage regions. Chui fails to disclose the size of the first (planar transistor) and second (FinFET transistor) elements. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to use nanometer processes, as shown in Zhang, in order to minimize the size, and thereby footprint, of the first and second elements.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chui in view of Zhang and Phao as applied to claim 7 above, and further in view of Syue et al (US 2023/0420504 A1) (of record).
Regarding Claim 8, Chui in view of Zhang and Phao fails to disclose wherein each of the first elements (planar transistors) comprises a display driving chip.
Syue discloses that each of the first elements comprises a display driving chip ([0017] High-voltage fin-based transistors may be used in applications such as integrated circuit (IC) drivers, power ICs, image sensors, power management, display driver ICs (DDICs), bipolar complementary metal oxide semiconductor (CMOS) diffused metal oxide semiconductor (DMOS) ICs (BCD ICs), and/or image signal processing (ISP) ICs, among other examples.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application, based on the teachings of Phoa, to have each of the first elements (planar transistors) comprises a display driving chip. Phoa teaches that the high-voltage transistor can be used in any number of application, including a display driver IC. ([0017]) Therefore, it would have been obvious for the high-voltage device to be a display driver chip.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the teachings of Chui in view of Zhang and Phoa with Syue. Zhang teaches that the combination of high and low voltage transistors is a memory device ([0076] The semiconductor device may be fabricated by the method described above, and may be used as a peripheral circuit of a memory device. Particularly, the memory device may be an NAND chip.) Syue teaches that the high-voltage device in a combination of high voltage and low voltage transistors can serve a number of function, including a display driver chip ([0017] High-voltage fin-based transistors may be used in applications such as integrated circuit (IC) drivers, power ICs, image sensors, power management, display driver ICs (DDICs)) Based on the teachings of Syue, it would have been obvious to use the combination of high and low voltage transistors for a purpose other than memory, such as a device with the high-power transistor serving as a display driving chip.
Regarding Claim 9, Chui in view of Zhang and Phao fails to disclose wherein each of the second elements (FinFET) comprises a transistor element for logic operation.
Syue discloses wherein each of the second elements comprises a transistor element for logic operation. ([0017] Low-voltage fin-based transistors may be used in applications such as logic circuits (e.g., processors), memory (e.g., static random access memory (SRAM), and/or input/output (I/O) circuits, among other examples.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application, based on the teachings of Phoa, to have each of the second elements (FinFET) comprises a transistor for logic operation. Phoa teaches that the low-voltage transistor can be used in any number of application, including a logic circuit. ([0017] Low-voltage fin-based transistors may be used in applications such as logic circuits (e.g., processors), memory (e.g., static random access memory (SRAM), and/or input/output (I/O) circuits, among other examples.) Therefore, it would have been obvious for the low-voltage device to be a transistor for logic operation.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 19 (on Pages 6-8 of Applicant’s Remarks) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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