Attorney Docket Number: 010348-23024A-US
Filing Date: 07/28/2023
Claimed Priority Date: 07/29/2022 (DE 10 2022 119 084.6)
Inventors: Buchert et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the election filed on 12/08/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Elections/Restrictions
Applicant’s election of Invention I, reading on a semiconductor device, and Species 3, reading on figure 4, in the reply filed on 12/08/2025, is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). The applicant indicated that claims 1-3, 5, and 7-11 read on the elected species. The examiner agrees. Accordingly, claims 4 and 6 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected invention and/or species, there being no allowable generic or linking claim.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the features canceled from the claims. No new matter should be entered.
“the solder pad being in electrical contact via a solder layer with an associated solder pad of the circuit board”, as recited in claim 1
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the following claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o).
“Wherein the electrical component has a high-voltage potential applied to an underside of the electrical component via the at least one via and the metallization layer”, as recited in claim 8
Appropriate correction is required. No new matter should be added.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-3, 5, and 7-11 are rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1, line 15, recites the limitation “wherein a solder resist is partially arranged on the solder pad such that the at least one via, applied to the solder pad, is shielded from the solder”. Two distinct “solder pads” are previously recited in the claim: a solder pad arranged on the upper side of the electrical module and an associated solder pad of the circuit board. Accordingly, this limitation in the claim is indefinite as it is unclear to which of the two distinct solder pads the limitation “wherein a solder resist is partially arranged on the solder pad such that the at least one via, applied to the solder pad…” is intended to refer.
Claim 1 recites the limitation “such that the at least one via… is shielded from the solder”. Numerous elements are previously recited in the claim that relate to solder or could be interpreted to be potentially composed of solder (e.g., a solder pad arranged on the upper side of the electrical module, a solder layer, an associated solder pad of the circuit board, etc.). Accordingly, this limitation in the claim is indefinite as it is unclear to which of the various distinct “solder” elements previously recited in the claim the limitation “the solder” is intended to refer.
Claim 2 recites the limitations “wherein the solder resist is arranged as a strip on the solder pad” and “wherein the strip made of the solder resist extends over an entire width of the solder pad and subdivides the solder pad into two regions”. Two distinct “solder pads” are previously recited: a solder pad arranged on the upper side of the electrical module and an associated solder pad of the circuit board. Accordingly, this limitation in the claim is indefinite as it is unclear to which of the two distinct solder pads the limitations are intended to refer.
Claim 2 recites the limitation “a first region of the two regions being a region on which the solder is applied”. No “solder” has been previously sufficiently recited in the claim or in any parental claim to be applied to any solder pad. Accordingly, there is insufficient antecedent basis for this limitation in the claim. Furthermore, in the case that “the solder” is intended to be a previously recited element, numerous elements are previously recited in the claim that relate to solder or could be interpreted to be potentially composed of solder (e.g., a solder pad arranged on the upper side of the electrical module, a solder layer, an associated solder pad of the circuit board, etc.). In such an instance, this limitation in the claim is indefinite as it is unclear to which of the various distinct “solder” elements previously recited in the claim the limitation “the solder” is intended to refer.
Claim 3 recites the limitations “wherein the solder resist is arranged along a frame on the solder pad” and “wherein the frame of solder resist subdivides the solder pad”. Two distinct “solder pads” are previously recited: a solder pad arranged on the upper side of the electrical module and an associated solder pad of the circuit board. Accordingly, this limitation in the claim is indefinite as it is unclear to which of the two distinct solder pads the limitations are intended to refer.
Claim 3 recites the limitation “wherein the solder resist is arranged along a frame on the solder pad, which surrounds the at least one via”. It is unclear to what specific element the term “which” is precisely referring to as surrounding the at least one via, e.g., the solder resist, the frame, or the solder pad. Accordingly, this limitation in the claim is indefinite as it is unclear which precise element or elements previously recited in the claim are intended to be “surround[ing] the at least one via”.
Claim 7 recites the limitation “wherein the solder pad is rectangular”. Two distinct “solder pads” are previously recited: a solder pad arranged on the upper side of the electrical module and an associated solder pad of the circuit board. Accordingly, this limitation in the claim is indefinite as it is unclear to which of the two distinct solder pads the limitation is intended to refer.
Claims 2-3, 5, and 7-11 depend from claim 1 and thus inherit the deficiencies identified supra.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Yorita (WO 2015083249 A1) in view of Li (US 8,012,874) and Fujii (US 2007/0158838).
Regarding claim 1, Yorita (see, e.g., figs. 1 and 3) shows most aspects of the instant invention, including a circuit board arrangement comprising:
a circuit board 110 that has an upper side (side of 110 closest to 106) and an underside (side of 110 farthest from 106); and
an electrical module 109 having an upper side (side of 109 farthest from 105) and an underside (side of 109 closest to 105), the electrical module being arranged with the upper side of the electrical module on the underside of the circuit board
wherein the electrical module comprises:
a solder pad 126a or 118a arranged on the upper side of the electrical module, the solder pad being in electrical contact via a solder layer 200 with an associated solder pad 126b or 118b of the circuit board (see, e.g., pars.0029-0031);
a conductive layer 103 located at a distance from the upper side of the electrical module (see, e.g., par.0042);
an electrical component 105 that is arranged on the conductive layer and is electrically connected to the conductive layer (see, e.g., pars.0040-0042 and 0122/ll.3-6);
at least one via 102 extending from the solder pad on the upper side of the electrical module up to the conductive layer; and
wherein:
a solder resist 117 is partially arranged on the solder pad arranged on the upper side of the electrical module such that the at least one via 102, applied to the solder pad arranged on the upper side of the electrical module, is shielded from the solder layer 200 (see, e.g., pars.0051 and 0059/ll.1-3)
Although Yorita teaches most aspects of the invention, and further teaches that Yorita’s device includes a conductive layer 103 electrically connected to various other components of Yorita’s circuit board arrangement (see, e.g., pars.0040-0042 and 0122/ll.3-6), Yorita fails to explicitly specify that Yorita’s conductive layer is a metallization layer. Li, in the same field of endeavor, teaches metallization layers to be suitable and appropriate for electrically interconnecting boards and electrical modules to various other electrical components (see, e.g., Li: col.5/ll.13-18). Fujii, also in the same field of endeavor, further teaches that certain metallization layers can yield joints with low resistance, thereby making excellent connections between electrical components and achieving devices with high yield and high reliability (see, e.g., Fujii: par.0045).
Li is evidence showing that one of ordinary skill in the art would appreciate that a metallization conductive layer would be equivalent to a conductive layer of any other type, and that such differences would result in no unexpected changes in the performance of the device of Yorita. That is, the conductive layers of both Yorita and Li would yield the predictable result of providing a suitable conductive pathway capable of electrically connecting electrical modules to various other conductive structures of a circuit board arrangement.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a conductive layer formed as a metallization layer, as taught by Li, or a different yet still conductive layer, as taught by Yorita, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of predictable result of providing a suitable conductive pathway capable of electrically connecting electrical modules to various other conductive structures of a circuit board arrangement. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, Li and Fujii are evidence that at the time of filing the invention it would have been obvious that one of ordinary skill in the art would find particular incentive to have Yorita’s conductive layer comprise a metallization layer, as taught by Li and Fujii, so as to have Yorita’s conductive layer comprise a provenly suitable material capable of electrical interconnection with various electrical components, including boards and electrical modules, as taught by Yorita to already be included in Yorita’s circuit board arrangement, whilst simultaneously yielding joints with low resistance, thereby making an excellent connection between Yorita’s electrical components and achieving a device with high yield and high reliability.
With regards to other language recited in claim 1, see the comments stated above in paragraphs 9-10.
Regarding claim 5, Yorita (see, e.g., fig. 3) shows that each via 102 of the at least one via 102 is surrounded by solder resist 117 over an angular range of 360°.
Regarding claim 9, Yorita/Li/Fujii shows most aspects of the instant invention (see paragraphs 19-24 above). Yorita, however, fails to explicitly specify that Yorita’s electrical component is a semiconductor component. Li, in the same field of endeavor, teaches that electrical components may be semiconductor components, and that semiconductor components may be adapted to be any of a myriad of different types of diverse circuit devices, such as microprocessors, memory devices, and graphics processors (see, e.g., Li: par.0033/ll.1-7).
Therefore, it would have been obvious at the time of filing the invention to have Yorita’s electrical component be a semiconductor component, as taught by Li, in order to take advantage of the wide variety of semiconductor device types available for implementation as electrical components, thereby expanding the variety, option, and circuitry choice of Yorita’s device.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yorita/Li/Fujii in view of Gross (US 10,624,208).
Regarding claim 7, Yorita/Li/Fujii shows most aspects of the instant invention (see paragraphs 19-24 above). Yorita further teaches that components of Yorita’s circuit board arrangement may be rectangular even if not explicitly illustrated as such (see, e.g., par.0152). However, Yorita fails to explicitly specify that Yorita’s solder pad arranged on the upper side of the electrical module is rectangular. However, it is noted that the specification fails to provide teachings about the criticality of having rectangular solder pads, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the solder pad shape disclosed by Yorita as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular solder pad shape claimed by Applicant is nothing more than one of numerous solder pad shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Furthermore, the claimed rectangular solder pad is known in the art: Gross, in the same field of endeavor teaches that the shape of solder pads can be rectangular (see, e.g., Gross: cols.3/ll.12-13 and 24-26). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the shape of rectangles in the structure of Yorita, because rectangular solder pads are known in the semiconductor art for their use as interconnection structures capable of supporting solder, as suggested by Gross, and implementing a known structure shape for its conventional use/purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With regards to other language recited in claim 7, see the comments stated above in paragraphs 15-16.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yorita/Li/Fujii in view of Ehrmann (US 2016/0192493).
Regarding claim 10, Regarding claim 7, Yorita/Li/Fujii shows most aspects of the instant invention (see paragraphs 19-24 and 26-27). Furthermore, Yorita/Li teaches that Yorita’s electrical component is a semiconductor component (see the comments stated above in paragraphs 26-27, which are considered to be repeated here). However, despite Yorita teaching that Yorita’s circuit board arrangement may include a power device (see, e.g., Yorita: par.0122/ll.6) and Li teaching that semiconductor components may be adapted to be any of a myriad of different types of diverse circuit devices (see, e.g., Li: par.0033/ll.1-7), Yorita/Li/Fujii fails to explicitly specify that the semiconductor component is a power semiconductor. Ehrmann, in the same field of endeavor, teaches that semiconductor components may be power semiconductors, and that power semiconductors perform well at regulating high currents, voltages, and levels of power, particularly at high clock frequencies (see, e.g., Ehrmann: par.0031).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the semiconductor component of Yorita/Li/Fujii (see the comments stated above in paragraphs 26-27, which are considered to be repeated here) be a power semiconductor, as taught by Ehrmann, so as to expand the functionality and operability of the device of Yorita/Li/Fujii at high current and voltage ranges, for example, at high clock frequencies and high levels of power.
Allowable Subject Matter
Claims 2-3, 8, and 11 are rejected under 35 U.S.C. 112(b) and objected to as being dependent upon a rejected base claim, but would be allowable if rewritten (1) to properly overcome the 35 U.S.C. 112(b) rejections set forth in this Office action and (2) in independent form including all the limitations of the base claim and any intervening claims.
Conclusion
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814