Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed January 20, 2026. Claims 1, 2, 4, 7, 8, 10, 13, 14, 16, 17, 19, and 20 are amended. Claims 3 and 15 are cancelled. The Examiner notes that claims 1-2, 4-14, and 16-20 are examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 4-14, and 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 and 14 recite the limitation “wherein each of the first heat dissipation substrate or the second heat dissipation substrates comprises sequentially disposed a metal wiring layer, an insulating material layer, and a heat dissipation metal layer.” This claim is indefinite because “each” means both heat dissipation structures require the claimed structure while “or” means only one. For the purposes of this Action, the limitations will be interpreted to say “wherein each of the first heat dissipation substrate and the second heat dissipation substrates comprises sequentially disposed a metal wiring layer, an insulating material layer, and a heat dissipation metal layer.”
Dependent claims 2, 4-13, and 16-20 are rejected at least on the same basis as the claims from which they depend.
Claim Rejections - 35 USC § 103
Claims 1-2, 4-14, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (University of Arkansas Graduate Theses and Dissertations, 2021) in view of Woo (2016 IEEE 66th Electronic Components and Technology Conference)
With respect to claim 1, Huang teaches in Fig. 2.1(b) on page 17:
A semiconductor module comprising:
a circuit board (low temperature co-fired ceramic substrate LTCC) having a first surface (top) and a second surface (bottom);
a first semiconductor device (MOSFET bare die on top) mounted on the first surface of the circuit board;
a second semiconductor device (MOSFET bare die on bottom) mounted on the second surface of the circuit board;
a first heat dissipation substrate (top DBC) placed on a top of the first semiconductor device,
wherein the first heat dissipation substrate (top DBC, page 16 “The power module consists of two direct bond copper (DBC) substrates at top and bottom, which act as die attachment substrates and also provide vertical double-sided cooling”) is coupled to a second surface of the first semiconductor device (top surface of top MOSFET bare die);
a second heat dissipation substrate (bottom DBC) placed on the top (bottom in Fig. 2.1, would be top if device is flipped) of the second semiconductor device (bottom MOSFET bare die),
wherein the second heat dissipation substrate (bottom DBC) is coupled to a second surface (bottom surface) of the second semiconductor device; and
wherein each of the first heat dissipation substrates or the second heat dissipation substrate (direct bonded copper substrates DBC as described in section 3.1.3 on page 50) comprises sequentially disposed a metal wiring layer (bottom Cu sheet in top DBC, top Cu sheet in bottom DBC);
an insulating material layer (alumina or aluminum nitride, see page 50);
and a heat dissipation metal layer (top Cu sheet in top DBC and bottom Cu sheet in bottom DBC).
Huang fails to teach:
a conductive clip being mounted on the circuit board,
wherein the conductive clip comprises:
a body portion disposed either between the first semiconductor device and the first heat dissipation substrate or between the second semiconductor device and the second heat dissipation substrate;
and at least two inclined branched connection portions electrically to connect the body portion to the circuit board.
Huang modified by Fig. 1C of Woo to include the copper clips around all of the first and second devices and encapsulation around the clips and devices teaches:
a conductive clip (copper clip of Woo) mounted on the circuit board (ceramic substrate of Woo, LTCC of Huang),
wherein the conductive clip (copper clip) comprises:
a body portion (see annotated Fig. 1c below) disposed either between the first semiconductor device (SiC) and the first heat dissipation substrate (DBC of Huang, heat spreader of Woo) or between the second semiconductor device and the second heat dissipation substrate;
and at least two inclined branched connection portions (see annotated Fig. 1c below) electrically to connect the body portion to the circuit board (ceramic substrate of Woo, LTCC of Huang).
Huang discloses the claimed invention except for the conductive clips. Woo teaches that it is known to use copper clips to connect the top of a flip chip to a substrate while improving heat dissipation characteristics. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huang to include copper clips as taught by Woo, since Woo states in the abstract that such a modification would enable efficient double-sided heat dissipation in a device that endures at high temperatures. See MPEP 2144.
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With respect to claim 2, Huang/Woo further teaches:
the conductive clip (copper clip of Woo) is either between the first semiconductor device (SiC of Woo, top MOSFET bare die of Huang) and the first heat dissipation substrate (top DBC of Huang which serves and equivalent purpose to the top heat spreader of Woo) to cover the first surface of the first semiconductor device (SiC of Woo) and to support the first heat dissipation substrate (top DBC of Huang, equivalent to the top heat spreader that is physically supported by the copper clips in Woo)
or is between the second semiconductor device and the second heat dissipation substrate to cover the second surface of the second semiconductor device and to support the second heat dissipation substrate.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Huang in view of Woo as explained above.
With respect to claim 4, Huang further teaches:
wherein the first semiconductor device (top MOSFET bare die) and the second semiconductor device (bottom MOSFET bare die), each comprises at least one or more of bumps (copper balls), and,
wherein a thickness of each of the bumps is determined according to a thickness of the first semiconductor device or the second semiconductor device to which each of the bumps is connected.
The Examiner determines that the limitation relating to the thickness of the bumps is a product-by-process limitation. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). The process of determining how thick to make the bumps does not hold patentable weight as the limitation is broad and does not imply any additional structure.
With respect to claim 5, Huang further teaches:
wherein the first semiconductor device (top MOSFET bare die) includes a first bump (copper balls under top MOSFET bare die) disposed between a first surface of the first semiconductor device (bottom of top MOSFET bare die) and the first surface of the circuit board (top of LTCC) to electrically connect a first electrode of the first semiconductor device to the circuit board (page 16 “the gate and source pads on top of the MOSFET bare die are routed through Cu balls and conductive traces on LTCC interposer to the outer terminals, while the drain pad at back of the bare die is soldered to the DBC substrates on which power terminals are attached on.” The gate, source, and drain pads are considered to be electrodes because they provide electrical connections to the bare die.),
and wherein the second semiconductor device (bottom MOSFET bare die) includes a second bump (copper balls above bottom MOSFET bare die) disposed between a first surface of the second semiconductor device (top of bottom MOSFET bare die) and the second surface of the circuit board (bottom of LTCC) to electrically connect a first electrode of the second semiconductor device to the circuit board (page 16 “the gate and source pads on top of the MOSFET bare die are routed through Cu balls and conductive traces on LTCC interposer to the outer terminals, while the drain pad at back of the bare die is soldered to the DBC substrates on which power terminals are attached on.” The gate, source, and drain pads are considered to be electrodes because they provide electrical connections to the bare die.)
With respect to claim 6, Woo further teaches:
wherein the conductive clip (copper clip in Fig. 1c) at least partially covers the top of the first semiconductor device (SiC) or the top of the second semiconductor device.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Huang in view of Woo as explained above.
With respect to claim 7, Woo further teaches:
wherein an electrode of the first semiconductor device or the second semiconductor device is electrically connected to the circuit board through the conductive clip (For the drain interconnection, copper clips are attached using high temperature endurable interconnection materials),
and wherein the electrode comprises at least one of gate electrode, a source electrode electrically isolated from the gate electrode, or a drain electrode.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Huang in view of Woo as explained above.
With respect to claim 8, Huang/Woo further teaches:
wherein a set of the first heat dissipation substrate (top DBC of Huang),
the first semiconductor device (top MOSFET bare die of Huang),
and the first bump (copper balls below top MOSFET bare die of Huang)
and a set of the second heat dissipation substrate (bottom DBC of Huang),
the second semiconductor device (bottom MOSFET bare die),
and the second bump are structured (copper balls above bottom MOSFET bare die)
symmetrically with respect to the circuit board (see Fig. 2.1 of Huang, device has mirror symmetry about a line through LTCC).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Huang in view of Woo as explained above.
With respect to claim 9, Huang/Woo further teaches:
a molding member (encapsulation, see Fig. 1C of Woo, which is a Silica filled HT epoxy according to table II of Woo) to hold the conductive clip,
wherein the molding member is formed in a space between the circuit board and the first heat dissipation substrate or a space between the circuit board and the second heat dissipation substrate (see Fig. 1C of Woo, encapsulation is between the circuit board (ceramic substrate) and the top heat spreader which is analogous to the DBC of Huang).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Huang in view of Woo as explained above.
With respect to claim 10, Woo further teaches:
wherein the conductive clip (copper clip) includes at least four inclined branched connection portions electrically to connect the body portion to the circuit board (see Fig. 2a of Woo, each clip has multiple include branched connection potions on each side including at least four)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Huang in view of Woo as explained above.
With respect to claim 11, Huang further teaches:
wherein the first and second semiconductor devices include a power semiconductor device or a microcontroller unit (MCU) (caption of Fig. 2.1 recites that the module is a “stack power module structure”).
With respect to claim 12, Huang further teaches:
wherein the first and second heat dissipation substrates (direct bonded copper substrates DBC as described in section 3.1.3 on page 50) include:
an insulating material layer (alumina or aluminum nitride, see page 50);
a metal wiring layer formed on one surface of the insulating material layer and facing the circuit board (bottom Cu sheet in top DBC, top Cu sheet in bottom DBC);
and a heat dissipation metal layer formed on another surface of the insulating material layer (top Cu sheet in top DBC and bottom Cu sheet in bottom DBC).
With respect to claim 13, Huang further teaches:
a lead frame (AC terminal (pink portion of Fig. 2.1(a) and (b)) having one end connected to the circuit board (left end) and another end opened exposed to an outside (right end).
With respect to claim 14, Huang teaches:
A method for fabricating a semiconductor module comprising:
placing a circuit board (low temperature co-fired ceramic substrate LTCC) having a first surface (top) and a second surface (bottom);
mounting a first semiconductor device (MOSFET bare die on top) on the first surface of the circuit board;
mounting a second semiconductor device (MOSFET bare die on bottom) on the second surface of the circuit board;
placing a first heat dissipation substrate (top DBC) on the top of a first semiconductor device,
and placing a second heat dissipation substrate (bottom DBC) on a top (bottom in Fig. 2.1, would be top if device is flipped) of the second semiconductor device (bottom MOSFET bare die),
wherein each of the first heat dissipation substrates or the second heat dissipation substrate (direct bonded copper substrates DBC as described in section 3.1.3 on page 50) comprises sequentially disposed a metal wiring layer (bottom Cu sheet in top DBC, top Cu sheet in bottom DBC);
an insulating material layer (alumina or aluminum nitride, see page 50);
and a heat dissipation metal layer (top Cu sheet in top DBC and bottom Cu sheet in bottom DBC).
Huang fails to teach:
mounting a first conductive clip on the circuit board to cover a surface of the first semiconductor device
mounting a second conductive clip on the circuit board to cover a surface of the second semiconductor device
placing a first heat dissipation substrate on the top of the first conductive clip,
and placing a second heat dissipation substrate on a top of the second copper clip,
wherein the first conductive clip and the second conductive clip, each at least partially covers the top of the first semiconductor device and the top of the second semiconductor device, respectively, and wherein the first and second conductive clips include a plurality of connection portions having an inclined surface.
wherein the conductive clip comprises:
a body portion disposed either between the first semiconductor device and the first heat dissipation substrate or between the second semiconductor device and the second heat dissipation substrate;
and at least two inclined branched connection portions electrically to connect the body portion to the circuit board.
Woo teaches in Fig. 1C:
mounting a conductive clip (copper clip) on the circuit board (ceramic substrate) to cover a surface of the first semiconductor device (SiC)
placing a heat dissipation substrate (heat spreader substrate) on a top of the first conductive clip (copper clip)
Huang modified by Fig. 1C of Woo to include the copper clips around all of the first and second devices and encapsulation around the clips and devices teaches:
mounting a first conductive clip (copper clip of Woo) on the circuit board (ceramic substrate of Woo, LTCC of Huang) to cover a surface of the first semiconductor device (SiC of Woo, top MOSFET bare die of Huang)
mounting a second conductive clip (copper clip of Woo) on the circuit board (ceramic substrate of Woo, LTCC of Huang) to cover a surface of the second semiconductor device (SiC of Woo, bottom MOSFET bare die of Huang) and the second heat dissipation substrate (bottom DBC of Huang which serves and equivalent purpose to the top heat spreader of Woo)
placing a first heat dissipation substrate (top DBC of Huang which serves and equivalent purpose to the top heat spreader of Woo) on a top of the first conductive clip (copper clip)
placing a second heat dissipation substrate (bottom DBC of Huang which serves and equivalent purpose to the top heat spreader of Woo) on a top of the second conductive clip (copper clip)
wherein the conductive clip (copper clip) comprises:
a body portion (see annotated Fig. 1c below) disposed either between the first semiconductor device (SiC) and the first heat dissipation substrate (DBC of Huang, heat spreader of Woo) or between the second semiconductor device and the second heat dissipation substrate;
and at least two inclined branched connection portions (see annotated Fig. 1c below) electrically to connect the body portion to the circuit board (ceramic substrate of Woo, LTCC of Huang).
Huang discloses the claimed invention except for the conductive clips. Woo teaches that it is known to use copper clips to connect the top of a flip chip to a substrate while improving heat dissipation characteristics. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huang to include copper clips as taught by Woo, since Woo states in the abstract that such a modification would enable efficient double-sided heat dissipation in a device that endures at high temperatures. See MPEP 2144.
With respect to claim 16, Huang/Woo further teaches:
forming a molding member (encapsulation, see Fig. 1C of Woo, which is a Silica filled HT epoxy according to table II of Woo) to hold the conductive clip in a space between the circuit board and the first heat dissipation substrate and a space between the circuit board and the second heat dissipation substrate (see Fig. 1C of Woo, encapsulation is between the circuit board (ceramic substrate) and the top heat spreader which is analogous to the DBC of Huang).
wherein the first and second conductive clips (copper clip) includes at least four inclined branched connection portions electrically to connect the body portion to the circuit board (see Fig. 2a of Woo, each clip has multiple include branched connection potions on each side including at least four)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Huang in view of Woo as explained above.
With respect to claim 17, Huang/Woo further teaches:
connecting a conductive frame (AC terminal) having one end connected to the circuit board (LTCC) and an other end opened toward an outside of the semiconductor module (right side of AC terminal as shown in Fig. 2.1(b) is exposed),
wherein a set of the first heat dissipation substrate (top DBC of Huang),
the first conductive clip (copper clip of Woo modified to cover MOSFET bare die of Huang),
and the first semiconductor device (top MOSFET bare die of Huang)
and a set of the second heat dissipation substrate (bottom DBC),
the second conductive clip (copper clip of Woo modified to cover bottom MOSFET bare die of Huang),
and the second semiconductor device (bottom MOSFET bare die) are structured symmetrically with respect to the circuit board (See Fig. 2.1 (b) of Huang, which has mirror symmetry about a horizontal line through LTCC).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Huang in view of Woo as explained above.
With respect to claim 18, Huang further teaches:
forming one or more bumps (copper balls) to connect with the first semiconductor device (top MOSFET bare die) and the second semiconductor device (bottom MOSFET bare die).
With respect to claim 19, Huang further teaches:
the first semiconductor device (top MOSFET bare die) is electrically connected to the first surface of the circuit board (top of LTCC) through one or more bumps (copper balls),
and the second semiconductor device (bottom MOSFET bare die) is electrically connected to the second surface of the circuit board (bottom of LTCC) through one or more bumps (copper balls),
and wherein, when a plurality of first and second semiconductor devices and one or more bumps are provided,
the thickness of each of the bumps is determined according to the thickness of the first semiconductor device or the second semiconductor device to which each of the bumps is connected (the Examiner notes that the preceding is a contingent limitation that depends on the limitation “when a plurality of first and second semiconductor devices and one or more bumps are provided” being met. “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. (MPEP 2111.04) In the instant case, it is not necessary for there to be a plurality of first and second semiconductor devices, therefore under broadest reasonable interpretation the limitation related to the thickness of the bumps is not required.)
With respect to claim 20, Huang further teaches:
further comprising:
forming an insulating material layer (alumina or aluminum nitride, see DBC Substrate Preparation section of page 50) on each of the first heat dissipation substrate (top DBC), and the second heat dissipation substrate (bottom DBC);
forming a metal wiring layer (Cu sheet) on one surface of each of the insulating material layer of the first heat dissipation substrate and the second heat dissipation substrate (sheet on inside of the device between insulating layer of DBC substrates and MOSFETs),
wherein the metal wiring layer faces the circuit board;
and forming a heat dissipation metal layer (Cu sheet on outside) on another surface of each of the insulating material layer of the first heat dissipation substrate and the second heat dissipation substrate (Cu sheet is on outside of insulating part of DBC, see Fig. 2.1).
Response to Arguments
Applicant’s arguments, see page 10, filed January 20, 2026, with respect to the claim objections are persuasive. All claim objections are withdrawn in view of amendments.
Applicant’s arguments with respect to claims 1, 14, and their dependent claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897