DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statements filed on 09/28/2023 has been considered.
Oath/Declaration
The oath or declaration filed on 07/29/2023 is acceptable.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 01/08/2024.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (410; Fig 4; [0048]) = (element 410; Figure No. 4; Paragraph No. [0048]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1 and 11 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Otremba; Ralf et al. (US 20140061669 A1) hereinafter Otremba.
1. Otremba teaches a power chip package (410; Fig 4; [0046] power attributes is construed from [0017, 0031]), comprising (see the entire document, Figs 4,3E along with the subject matters of relevant figures 1 to 3A-3D, 3F and 5, specifically, as cited below):
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Otremba Figure 4; Figure 3E
a metal cover (402; Fig 4; [0048], first cited as 102 in fig 1; [0025] as metal) comprising a recess (104/404 labelled as cavity in [0026]) formed on a side surface of the metal cover (402/102);
a power chip (106; Fig 3;[0029, 0031]) bonded ([0045]) on the metal cover and located in the recess (404/104); and
a thermal conductive material (112 (0033]) filling the recess (104/404) and surrounding the power chip (106), wherein at least one first electrode (326/) of the power chip (106) is exposed out of the thermal conductive material (112).
11. The power chip package of claim 1, Otremba further teaches, wherein the metal cover (102/402) comprises a connecting plate portion (underlying 318; [0027]) and a surrounding wall portion (adjacent to 316), the power chip (106) is bonded on the connecting plate portion, the surrounding wall portion is formed on an outer edge of the connecting plate portion, and the recess (104) of the metal cover is enclosed by the surrounding wall portion (316) and the connecting plate portion (318; Fig 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Otremba; Ralf et al. (US 20140061669 A1) hereinafter Otremba; in view of Deboy; Gerald et al. (US 20160079233 A1) hereinafter Deboy.
2.The power chip package of claim 1, while Otremba discloses, wherein the power chip (106; [0029]) comprises semiconductor die, but does not expressly disclose, a substrate and a semiconductor structure layer,
However, in the analogous art Debooy discloses [0006) “a power circuit includes a semiconductor die that includes a common substrate and a III-V semiconductor layer formed atop the common substrate” and further discloses ([0075] a III-V semiconductor layer 212 which is formed atop a single, common substrate 214 of a single semiconductor die 211; common substrate 214 made from Si, SiC, Sapphire, etc.).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to select configuration of Debooy for Otremba’s semiconductor die, and thereby, the combination of (Otremba and Debooy) will have a power chip (106; [0029]) comprises semiconductor die, a substrate (Debooy 214) and a semiconductor structure layer (Debooy 212).
The ordinary artisan would have been motivated to modify Otremba in the manner set forth above in order to, at least, because the he coupling structure is further configured to prevent current collapse in the III-V semiconductor layer by dynamically coupling the common substrate of the semiconductor die to the lowest potential. (Debooy [0032]).
The combination of (Otremba and Debooy) further discloses: wherein the substrate (Debooy 214 or 106) comprises a second electrode (108; [0029, 0031]) bonded on the metal cover (102/402), the semiconductor structure (Debooy 212) is disposed on the substrate (Debooy 214), and the at least one first electrode (326) is electrically connected to the semiconductor structure layer..
3. The power chip package of claim 2, the combination of (Otremba and Debooy) further teaches, wherein the substrate (Debooy 214 ) is made of one of silicon carbide, silicon, gallium oxide and gallium nitride (Debooy [0075]).
4. The power chip package of claim 1, the combination of (Otremba and Debooy; using the same rationale of claim 2, supra) wherein the power chip (106) comprises a silicon substrate (Debooy 214) and a semiconductor structure layer (Debooy 212), the silicon substrate (as a part of 106) is bonded on an inner side of the metal cover (102/402), an outer side of the metal cover is grounded, the semiconductor structure layer (Debooy 212) is disposed on the silicon substrate (Debooy 214) , the at least one first electrode (326) is connected to the semiconductor structure layer (Debooy 214 of 106), and the semiconductor structure layer (Debooy 214 of 106) is located between the at least one first electrode (326) and the silicon substrate (Debooy 214).
6. The power chip package of claim 2, the combination of (Otremba and Debooy) further teaches, wherein each of the at least one first electrode (326) comprises a primary portion (326; Fig 3E; [0045)) and an extension portion (326,327), the primary portion is located between the semiconductor structure layer ((Debooy 212 of 106) and the extension portion (336), a material of the extension portion is selected from a group consisting of (tin/silver/copper, tin/copper, tin/sliver, tin/bismuth, tin/antimony), silver, copper, and indium sliver ([0045]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Otremba; Ralf et al. (US 20140061669 A1) hereinafter Otremba; in view of Akre; Sunil M. et al. (US 9936579 B2) hereinafter Akre.
5. The power chip package of claim 1, while Otremba discloses, wherein the power chip (106; [0029]) but does not expressly disclose comprises a insulation substrate and a semiconductor structure layer, the insulation substrate is bonded on an inner side of the metal cover, the semiconductor structure layer is disposed on the insulation substrate, the at least one first electrode is connected to the semiconductor structure layer, and the semiconductor structure layer is located between the at least one first electrode and the insulation substrate.
However, in the analogous art, Akre teaches a power conversion system module and more particularly to packaging and assembly of a low profile power conversion system module. (Col 1. Lines 16-20), wherein ( Fig 1B, Col 5, Line 33- 67) power chip (100) comprises a insulation substrate (120 ceramic) and a semiconductor structure layer (140),.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to select configuration of Akre for Otremba’s powerchip, and thereby, the combination of (Otremba and Akre) will have a power chip (106; [0029]) comprises a substrate (Akre 120) and a semiconductor structure layer (Akre 140).
The ordinary artisan would have been motivated to modify Otremba in the manner set forth above , at least, because the insulation substrate will reduce noise and prevent short circuit with metal cover..
Claims 7-10 rejected under 35 U.S.C. 103 as being unpatentable over Otremba; Ralf et al. (US 20140061669 A1) hereinafter Otremba; in view of Hering; Ronald L et al. (US 20090098666 A1) hereinafter Hering.
7. The power chip package of claim 1, Otremba does not expressly disclose, wherein the thermal conductive material (of 112; Figs 1/4) extends to the at least one first electrode (326).
However, in the analogous art, Hering teaches integrated circuit (IC) chip packaging, and more particularly, to methods of assembling a chip package ([0002]). wherein (Figs 1A-1D; [0014) thermal interface material (TIM) 106 is disposed over chip 102 for thermally coupling the chip to a lid 110.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Hering TIM over Otremba’s Power chip 106, and thereby, the combination of (Otremba 112 and Herring 106) will extends the thermal conductive material (by combining 111 with Hering 106) to at least one first electrode (326), since this inclusion, at least, increase thermal transfer efficiency of thermal pads (Herring [0014]).
8. The power chip package of claim 7, the combination of (Otremba and Herring) further teaches, wherein an end surface of each of the at least one first electrode (326) is coplanar with an end surface of the thermal conductive material (Depicted in Fig 1A; for Herring 106).
9. The power chip package of claim 7, the combination of (Otremba and Herring) further teaches, wherein the at least one first electrode (326) is protruded out (as 336 ; fig 3E; [0045]) of an end surface of the thermal conductive material (Herring 106).
10. The power chip package of claim 1, the combination of (Otremba and Herring; using the same rationale of claim 7, supra) wherein the thermal conductive material (extended portion herring 106) is indirectly connected to an end surface of each of the at least one first electrode ([326]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Otremba; Ralf et al. (US 20140061669 A1) hereinafter Otremba; in view LIU; Yulei of et al. (US 20240085302 A1) hereinafter Liu.
12. The power chip package of claim 11, Otremba does not expressly disclose, wherein the metal cover (102/402)further portion comprises a rough, the rough portion is disposed on an inner side surface (316) of the surrounding wall portion.
However, in the analogous art, Liu teaches [0254], the rough cavity wall of the roughness of the cavity wall of the light trap cavity 331 the light trap cavity 331 can absorb the light better.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Otremba’s cavity wall 316 with the teaching of Liu and thereby, the combination of (Otremba and Liu will have the metal cover (102/402)further portion comprises a rough (Liu), the rough portion is disposed on an inner side surface (316) of the surrounding wall portion. since this modification , at least, increase the adhesion strength of thermal layer and metal layer.
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Otremba; Ralf et al. (US 20140061669 A1) hereinafter Otremba; in view of OBERST; Wieland et al. (US 20140233086 A1) hereinafter Oberst.
13. The power chip package of claim 11, Otremba does not expressly disclose, wherein the metal cover further comprises at least one stopper, the at least one stopper is protruded out of an inner side surface of the surrounding wall portion (102/402).
However, in the analogous art, Oberst teaches an electronic component ([0003]), wherein (Fig 1; [0016]) the metal cover (22) comprises at least one stopper (38), the at least one stopper (38)is protruded out of an inner side surface of the surrounding wall portion (22)
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Oberst over Otremba’s metal cover 103/402, and thereby, the combination of (Otremba and Oberst ) will metal cover comprises at least one stopper, the at least one stopper is protruded out of an inner side surface of the surrounding wall portion (102/402), since this inclusion, at least, reduce noise and increase efficieny.
14. The power chip package of claim 13, the combination of (Otremba and Oberst) further teaches, wherein the at least one stopper (Oberst 38) extends to an end surface of the surrounding wall portion (Oberst Fig 1).
15. The power chip package of claim 13, the combination of (Otremba and Oberst) further teaches, wherein the at least one stopper (38) is indirectly connected to an end surface of the surrounding wall portion (102/402).
16. The power chip package of claim 13, the combination of (Otremba and Oberst) further teaches, wherein a quantity of the at least one stopper (38) is more than two (fig 1), one of the at least one stopper is adjacent to and extends to an end surface of the surrounding wall portion (102/402), and another of the at least one stopper is indirectly connected to the end surface of the surrounding wall portion.
Claims 17-18 rejected under 35 U.S.C. 103 as being unpatentable over Otremba; Ralf et al. (US 20140061669 A1) hereinafter Otremba; in view of Eom; Joo-yang et al. (US 20090174044 A1) hereinafter Eom.
17. A power module, comprising: Otremba does not expressly disclose: a circuit board; a plurality of (while disclose) power chip packages (410) of claim 1 disposed on the circuit board; and a polymeric resin packaging the power chip packages on the circuit board.
However, in the analogous art, Eom teaches multi-chip power module package [0008], wherein (Fig 1; [00036-0037, 0044) a circuit board (PCB 110; [0044]; a plurality of (while disclose) power chip packages (121) of claim 1 disposed on the circuit board (110); and a polymeric resin (EMC 150; [0049]) packaging the power chip packages on the circuit board.
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EOM Figure 1
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate at least three Otremba (cited in claim1) power chip packages (410) into Eom PCB 110 and thereby, the combination of (Otremba and Eom) will have a circuit board (Eom 110); a plurality of (at least three of 121) power chip packages (410 in view of Eom 121) of claim 1 disposed on the circuit board Eom 110; and a polymeric resin (Eom 150) packaging the power chip packages (410 in view of Eom 121) on the circuit board (Eom 110)), since this usage will have a useful usage of Otremba teaches a power chip package (410).
18. The power module of claim 17, the combination of (Otremba and Eom) further teaches, wherein the power module (Eom 100)comprises : a heat dissipation fin (160) disposed on the metal covers (402 in view of 141) of the power chip packages (410); and an insulation thermal conductive material ([0009] an EMC having good thermal conductivity is used at a lower portion of the lead frame, and a heat sink formed of copper (Cu) is under the lead frame and is separated slightly therefrom, so that heat generated from a power circuit chip can be effectively released to the outside.) disposed on the metal covers of the power chip packages and located between the metal covers and the heat dissipation fin (160).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached on M-F: 8:30AM - 6:00 PM. EST.
Examiner interviews are available via telephone, in-person, and video The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moazzam Hossain whose telephone number is (571)270-7960. The examiner can normally be reached on Mon to Thursday 8.30 A.M -5.00 P.M. EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
September 26, 2025