Prosecution Insights
Last updated: May 29, 2026
Application No. 18/227,969

POWER DEVICES WITH IMPROVED ON-RESISTANCE

Non-Final OA §102§112
Filed
Jul 30, 2023
Priority
Jul 30, 2022 — provisional 63/393,834
Examiner
MAI, ANH D
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Purdue Research Foundation
OA Round
1 (Non-Final)
38%
Grant Probability
At Risk
1-2
OA Rounds
9m
Est. Remaining
48%
With Interview

Examiner Intelligence

Grants only 38% of cases
38%
Career Allowance Rate
262 granted / 697 resolved
-30.4% vs TC avg
Moderate +10% lift
Without
With
+9.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
29 currently pending
Career history
754
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
82.6%
+42.6% vs TC avg
§102
11.7%
-28.3% vs TC avg
§112
5.1%
-34.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 697 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Claims Applicant’s election without traverse of Species 1 in the reply filed on April 06, 2026 is acknowledged. Applicant identified claims 1-13 are readable on the elected Species. Non-elected Species, Claims 14-21 have been withdrawn from consideration. Claims 1-21 are pending. Action on merits of the Elected Species, claims 1-13 follows. Information Disclosure Statement The information disclosure statement (IDS) submitted on January 06, 2024 has been considered by the examiner. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: A MOS-BASE POWER DEVICE HAVING GATE ELECTRODE SEPARATED FROM A SEMICONDUCTOR REGION BY A SILICON DIOXIDE CONFIGURED TO WITHSTAND GREATER THAN 100V BETWEEN SOURCE AND DRAIN ELECTRODE Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. Claims 1-13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claim 1, lines 9-16 recites: “where the channel length has a range of between about 0.6 µm and about 0.5 µm, the silicon dioxide has a corresponding thickness range of between about 5 nm to about 30 nm, where the channel length has a range of between about 0.5 µm and about 0.4 µm, the silicon dioxide has a corresponding thickness range of between about 5 nm to about 25 nm, where the channel length has a range of between about 0.4 µm and about 0.3 µm, the silicon dioxide has a corresponding thickness range of between about 5 nm to about 20 nm, where the channel length has a range of between about 0.3 µm and about 0.2 µm, the silicon dioxide has a corresponding thickness range of between about 5 nm to about 15 nm” The above limitations appears to claim that one MOS device can have different “channel length” and different “silicon dioxide” thicknesses. How can a device has different “channel length” and different “silicon dioxide thicknesses”? Therefore, claim 1 fails to enable one skilled in the art to make and/or use the invention. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-13 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recite limitations, lines 9-16, as described above. However one device cannot have different “channel length” and different “silicon dioxide” thicknesses. Thus, claims 1-13 are indefinite. Claim 1 recites the limitation "where the channel length has a range of …" in lines 9, 11, 13 and 15, respectively. There is insufficient antecedent basis for this limitation in the claim. Therefore, claims 1-13 are indefinite. With respect to claim 8, It has been established that: A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112, second paragraph. In Ex parte Lyell, 17 USPQ2d, 1548 (BPAI. 1990), a claim directed to an automatic transmission work-stand and the method steps of using it was held to be ambiguous and properly rejected under 35 U.S.C. 112, second paragraph. A single claim which claims both an apparatus, the instant “the MOS-based power device of claim 7”, and the method steps of using the apparatus, the instant “wherein VGS is expressed as a function of the thickness of the dielectric material based on: Eins = (VGS – φGS - 2ψF)/tins …”, is indefinite under 35 U.S.C. 112, second paragraph. In Ex parte Lyell, 17 USPQ2d 1548 (BPAI 1990). The “MOS-based power device of claim 7,” is the apparatus claim. The “VGS is expressed as a function of the thickness of the dielectric material based on …” is the gate-source voltage being applied to the device, gate and source, during the operation. Thus, claim 8 claimed both an apparatus and a method step to operating the apparatus. Therefore, claim 8 is indefinite. With respect to claims 9-11, Claim 9 recites: the MOS-based power device of claim 1, wherein capacitance per unit area of the dielectric material is greater than about 6.90 x 10-8 F/cm2 and the channel length has a range of between about 0.6 µm and about 0.5 µm. Claim 10 recites: the MOS-based power device of claim 1, wherein capacitance per unit area of the dielectric material is greater than about 8.63 x 10-8 F/cm2 and the channel length has a range of between about 0.5 pm and about 0.4 pm. Claim 11 recites: the MOS-based power device of claim 1, wherein capacitance per unit area of the dielectric material is greater than about 1.15 x10-7 F/cm2 and the channel length has a range of between about 0.4 pm and about 0.3 pm. How can a same “dielectric material” has different “capacitance per unit area” ? Therefore, claims 9-11 are indefinite. The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claims 7-8 are rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 7 recites: The MOS-based power device of claim 1, wherein the electric field induced by the gate electrode is based on application of a gate-to-source voltage established based on the thickness of the dielectric material. “the electric field induced by the gate electrode” is inherently occur when the voltage is applied. Therefore, claim 7 fails to further limit claim 1. Claim 8 recites: The MOS-based power device of claim 7, wherein VGS is expressed as a function of the thickness of the dielectric material based on: Eins = (VGS – φGS - 2ψF)/tins … Claim 7 has already claimed: “wherein the electric field induced by the gate electrode is based on application of a gate-to-source voltage established based on the thickness of the dielectric material”. Note that, the “Eins is the electric field induced by the gate electrode”. Therefore, claim 8 fail to further limit claim 7. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SAGGIO et al. (US. Patent No. 8,344,449). With respect to claim 1, As best understood by the Examiner, SAGGIO teaches a metal oxide semiconductor (MOS)-based power device in 4H-SiC semiconductor, as claimed including: a semiconductor region (2); a drain electrode (30) and a source electrode (45); a gate electrode (31) separated from the semiconductor region (2) by silicon dioxide (23) as a dielectric material, wherein a load current passing through the drain and source electrodes is controlled by an electric field induced by the gate electrode into the semiconductor region thereby forming a conductive channel; where the channel length has a range of between about 0.6 µm and about 0.5 µm, the silicon dioxide (23) has a corresponding thickness range of between about 5 nm to about 30 nm, where the channel length has a range of between about 0.5 µm and about 0.4 µm, the silicon dioxide (23) has a corresponding thickness range of between about 5 nm to about 25 nm, where the channel length has a range of between about 0.4 µm and about 0.3 µm, the silicon dioxide (23) has a corresponding thickness range of between about 5 nm to about 20 nm, where the channel length has a range of between about 0.3 µm and about 0.2 µm, the silicon dioxide (23) has a corresponding thickness range of between about 5 nm to about 15 nm and wherein the device is configured to withstand greater than 100 V between the source (45) and the drain (30) electrodes while carrying the load current. (See FIG. 14). The term “wherein a load current passing through the drain and source electrodes is controlled by an electric field induced by the gate electrode into the semiconductor region thereby forming a conductive channel” is the function of the MOS-based power device. The term “configured to withstand greater than 100 V between the source (45) and the drain (30) electrodes while carrying the load current”, is the function of the MOS-based power device. Since the MOS-based power device of SAGGIO comprising the limitations as described above, the power device of SAGGIO is fully function as claimed. With respect to claim 2, material of the drain, source, and gate electrodes of SAGGIO comprises one or more of copper, silver, gold, carbon, graphite, nickel, titanium, aluminum, polysilicon, and graphene. With respect to claim 3, the semiconductor region (2) of SAGGIO comprises an N-type conductivity type and a P-type conductivity type. With respect to claim 4, the semiconductor region (2) of SAGGIO comprises a first semiconductor region, a second semiconductor region, and a third semiconductor region. With respect to claim 5, the first semiconductor region of SAGGIO has a dopant level higher than a dopant level of the second semiconductor region. With respect to claim 6, the third semiconductor region of SAGGIO has a dopant level higher than a dopant level of the second semiconductor region. With respect to claim 7, As best understood by the Examiner, the electric field induced by the gate electrode (31) of SAGGIO is based on application of a gate-to-source voltage (VGS) established based on the thickness of the dielectric material. The term “the electric field induced by the gate electrode”, is inherent result of the application of voltage VGS, regardless of the thicknesses of the gate dielectric. With respect to claim 8, As best understood by the Examiner, VGS of SAGGIO is expressed as a function of the thickness of the dielectric material based on: Eins = (VGS – φGS - 2ψF)/tins Eins is the electric field induced by the gate electrode, φGS is a work function difference between the gate material and the semiconductor in the channel region in volts, ψF is the bulk Fermi potential of the semiconductor material in the channel region (determined by its doping) in volts, and tins is the thickness of the dielectric material between the gate and the semiconductor in centimeters. The apparatus of SAGGIO can inherently be operated under the same VGS, as claimed. With respect to claim 9, As best understood by the Examiner, capacitance per unit area of the dielectric material (23) of SAGGIO is greater than about 6.90 x 10-8 F/cm2 and the channel length has a range of between about 0.6 µm and about 0.5 µm. The apparatus of SAGGIO comprises the same dielectric material with the same thickness. Thus, inherently has the same capacitance per unit area. With respect to claim 10, As best understood by the Examiner, capacitance per unit area of the dielectric material (23) of SAGGIO is greater than about 8.63 x 10-8 F/cm2 and the channel length has a range of between about 0.5 µm and about 0.4 µm. The apparatus of SAGGIO comprises the same dielectric material with the same thickness. Thus, inherently has the same capacitance per unit area. With respect to claim 11, As best understood by the Examiner, capacitance per unit area of the dielectric material (23) of SAGGIO is greater than about 1.15 x10-7 F/cm2 and the channel length has a range of between about 0.4 µm and about 0.3 µm. The apparatus of SAGGIO comprises the same dielectric material with the same thickness. Thus, inherently has the same capacitance per unit area. With respect to claim 12, the device of SAGGIO is a planar MOS field effect transistor (MOSFET). With respect to claim 13, the planar MOSFET of SAGGIO is a DMOSFET. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANH D MAI/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jul 30, 2023
Application Filed
May 08, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
38%
Grant Probability
48%
With Interview (+9.9%)
3y 7m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 697 resolved cases by this examiner. Grant probability derived from career allowance rate.

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