Prosecution Insights
Last updated: April 19, 2026
Application No. 18/228,231

SEMICONDUCTOR DEVICE INCLUDING 3D-STACKED FIELD-EFFECT TRANSISTORS HAVING ISOLATION STRUCTURE BETWEEN CONTACT PLUGS

Non-Final OA §102§103
Filed
Jul 31, 2023
Examiner
MALEK, MALIHEH
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
2y 11m
To Grant
82%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
460 granted / 584 resolved
+10.8% vs TC avg
Minimal +3% lift
Without
With
+3.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
28 currently pending
Career history
612
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
57.9%
+17.9% vs TC avg
§102
26.2%
-13.8% vs TC avg
§112
9.1%
-30.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 584 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restriction Applicant’s election of invention I, claims 1-16, with traverse in the reply filed on 10/22/2025 is acknowledged. The traversal is on the ground(s) that “the rule requires showing that the product can be made by a materially different method to restrict the invention. Using different materials and/or different deposition methods are, however, not materially different methods without additional contexts and basis are provided. Using different material compositions and/or using different deposition methods are commonly performed in the industry. It is often called recipe change or process optimization. For at least the reasons set out above, Applicant respectfully submits that the requirement for restriction of the Office Action does not meet the standard of MPEP § 806.05(f) and, therefore, is improper.” This is not found persuasive because although LPCVD, PECVD, ALD, and PVD are all known deposition techniques, substituting one for another is not a routine or interchangeable design choice. Each technique imposes drastically different manufacturing constraints that fundamentally alter masking strategies, etch processes, process sequencing, and integration complexity, thereby constituting distinct manufacturing inventions, even when the end device appears structurally similar. For example, LPCVD typically requires high temperatures, which necessitates adjustment in process sequencing to avoid thermal degradation of previously formed layers. PECVD enables lower-temperature deposition but often produces films with different hydrogen content, leading to modified etch selectivity or additional densification steps. ALD, with its self-limiting growth mechanism, requires different timing, cycle counts, and masking considerations due to its conformal nature, while PVD’s directional deposition can necessitate alternative mask designs or supplemental etch steps to achieve equivalent feature coverage. Furthermore, should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103(a) of the other invention. Additionally, it requires a different field of search; searching different classes/subclasses or electronic resources, or employing different search strategies or search queries, and the prior art applicable to one invention would not likely be applicable to another invention. The requirement is still deemed proper and is therefore made FINAL. DETAILED ACTION Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2, 4 and 10-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wu et al. (Pub. No. US 2023/0299205 A1, herein Wu). Regarding claim 1, Wu discloses a three-dimensionally-stacked field-effect transistor (3DSFET) device comprising: a 1st source/drain region 106 (Wu: paragraphs [0034], Figs. 7-8); a 2nd source/drain region 126, above the 1st source/drain region, having a smaller width than the 1st source/drain region (Wu: paragraphs [0060]-[0061], Figs. 7-8), the 2nd source/drain region being isolated from the 1st source/drain region by a 1st isolation structure 110/114 (Wu: paragraphs [0040]-[0042], Figs. 7-8); a 1st contact plug 130 on the 1st source/drain region; a 2nd contact plug 130 on the 2nd source/drain region (Wu: paragraphs [0063]-[0066], Figs. 7-8); and a 2nd isolation structure 122/124/128, between the 1st contact plug and the 2ndcontact plug, isolating the 2nd contact plug from the 1st contact plug, wherein the 2nd isolation structure is different and separate from the 1st isolation (Wu: paragraphs [0056]-[0063], Figs. 7-8). Regarding claim 2, Wu discloses the 3DSFET device of claim 1, wherein the 2nd isolation structure is extended to a space between the 1st contact plug and the 2nd source/drain region, and isolates the 1st contact plug from the 2nd source/drain region (Wu: paragraphs [0056]-[0063], Figs. 7-8). Regarding claims 4 and 10, Wu discloses the 3DSFET device of claim 1, wherein the 2nd isolation structure comprises a material different from a material forming the 1st isolation structure, wherein the 1st isolation structure comprises silicon nitride, and the 2nd isolation structure comprises silicon oxide (Wu: paragraphs [0036], [0042], Figs. 7-8). Regarding claim 11, Wu discloses the 3DSFET device of claim 1, wherein the 1st isolation structure contacts the 2nd isolation structure (Wu: paragraphs [0036], [0042], Figs. 7-8). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 5 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu. Regarding claims 5 and 12, Wu uses silicon nitride for spacers 110/114 and mainly oxide for dielectric layers 122/124/128. However, nitride and oxide are interchangeable isolation dielectrics routinely selected based on process integration consideration rather than device operation. A person of ordinary skill in the art would recognize that choice between nitride and oxide may be driven by manufacturing preferences, including: etch selectivity (nitride provides high selectivity against oxide), stress engineering, deposition method compatibility, defect and interface consideration, and integration with adjust dielectric layers. These considerations are process optimizations; substituting one for the other represents a predictable variation; the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sincalir & Carroll Co. v. International Corp., 325 U.S. 327, 65 USPQ 297 (1945). Therefore, Wu teaches the 3DSFET device of claim 1, wherein the 1st isolation structure comprises silicon oxide, and wherein an interface is formed between the 1st isolation structure and the 2nd isolation structure. Regarding claims 13 and 14, Wu does not specifically show the metal lines. However, back-end-of-line interconnects and backside metal lines are long-established and well-understood elements of semiconductor manufacturing. BEOL metal stacks, vias, and dielectrics have been used for decades to route signals and power above the device layer. Similarly, backside metal lines formed after wafer thinning are a known approach for providing power distribution, grounding, shielding, or thermal management. Both are routine process options within the industry, implemented using conventional materials and fabrication steps. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Hung (Pub. No. US 2021/0226021 A1). Regarding claim 6, Wu does not show wherein a bottom width of the 1St contact plug is greater than a top width of the 1st contact plug. However, in the same field of endeavor, Hung teaches a semiconductor device, wherein a bottom width 80 (72-74-78) of the 1st contact plug is greater than a top width 90 of the 1st contact plug (Hung: Fig. 21 and paragraphs [0033], [0039]) to decrease contact resistance (Hung: paragraphs [0037], [0040]-[0041]). Therefore, given the teachings of Hung, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Wu in view of Hung by employing the bottom width of the contact plug being greater than a top width of the contact plug. Allowable Subject Matter Claims 3, 7-9 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner's statement of reasons for allowance: With respect to claim 3, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein no barrier layer is formed on a portion of a side surface of at least one of the 1st contact plug and the 2nd contact plug contacting the 1st isolation structure, and wherein a barrier layer is formed on another portion of the side surface of the at least one of the 1st contact plug and the 2nd contact plug that does not contact the 2nd isolation structure. With respect to claims 7-9, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein a shape of a portion of the 2nd source/drain region contacting the 2nd isolation structure is different from a shape of an opposite portion of the 2nd source/drain region that does not contact the 2nd isolation structure. Claims 8-9 are included likewise as they depend from claim 7. With respect to claim 15, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, a 4th source/drain region, above the 1st source/drain region, and another 2nd isolation structure, between the 3rd contact plug and the 4th contact plug, isolating the 4th contact plug from the 3rd contact plug, wherein the other 2nd isolation structure is different and separate from the 1st isolation structure isolating the 4th source/drain region from the 3rd source/drain region, wherein at least one of the 1st to 4th contact plugs is connected to at least one of the 1st metal lines, and wherein another at least one of the 1st to 4th contact plugs is connected to at least one of the 2nd metal lines. With respect to claim 16, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, a 4th source/drain region, above the 1st source/drain region, and a common contact plug connected to both the 3rd source/drain region and the 4th source/drain region, wherein at least one of the 1st contact plug, the 2nd contact plug and the common contact plug is connected to at least one of the 1st metal lines, and wherein another at least one of the 1st contact plug, the 2nd contact plug and the common contact plug is connected to at least one of the 2nd metal lines. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. December 27, 2025 /MALIHEH MALEK/Primary Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Jul 31, 2023
Application Filed
Dec 27, 2025
Non-Final Rejection — §102, §103
Apr 15, 2026
Interview Requested

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
82%
With Interview (+3.4%)
2y 11m
Median Time to Grant
Low
PTA Risk
Based on 584 resolved cases by this examiner. Grant probability derived from career allow rate.

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