DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, direct to claim(s) 1-20 in the reply filed on 01/05/2026 is acknowledged and is under consideration. The Election was made without traverse in the reply filed on 01/05/2026.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 07/31/2023, 10/28/2024, and 09/02/2025 are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Claim Objections
Claim 10 is objected to because of the following informalities: Claim 10 currently recites, “the first gate electrode of the first gate structure and a second gate electrode of the second gate electrode”. The Examiner interpreted the latter half of the above claim limitation as “a second gate electrode of the second gate structure” similar to the first half of the claim. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 7-13, and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aaron D. Lilak et al, (hereinafter LILAK), US 20200294998 A1.
Regarding Claim 1, LILAK teaches a semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) comprising:
a first field effect transistor (FET) (Fig. 1A, 104, lower device region) having a first gate structure (Fig. 1A, 120A/122A/123A, gate electrodes/gate dielectrics/gate spacers) and a pair of first source/drain regions (Fig. 1A, 124A);
a second FET (Fig. 1A, 108, upper device region) stacked over the first FET (Fig. 1A, 104, lower device region) and having a second gate structure (Fig. 1A, 120B/122B/123B, gate electrodes/gate dielectrics/gate spacers) and a pair of second source/drain regions (Fig. 1A, 124B);
a dielectric pillar (Fig. 1A, 140, etch selective material, can be a dielectric material, [0028]) located beneath the first FET (Fig. 1A, 104, lower device region) and directly contacting one of the first source/drain regions (Fig. 1A, 124A) of the pair of first source/drain regions (Fig. 1A, 124A); and
backside (Fig. 1A, 103, backside contact region) gate dielectric cap (Fig. 1A, 136, etch selective material, are dielectric materials, [0028]) located adjacent to the dielectric pillar (Fig. 1A, 140, etch selective material, can be a dielectric material, [0028]), wherein the backside (Fig. 1A, backside contact region, 103) gate dielectric cap (Fig. 1A, 136, etch selective material, are dielectric materials, [0028]) directly contacts a surface of a first gate electrode (Fig. 1A, 120A, gate electrodes) of the first gate structure (Fig. 1A, 120A/122A/123A, gate electrodes/gate dielectrics/gate spacers).
Regarding Claim 2, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 1, wherein the dielectric pillar (Fig. 1A, 140, etch selective material, can be a dielectric material, [0028]) further comprises a sidewall having a first portion (Fig. 1A, 126, spacer) that directly contacts a sidewall (Fig. 1A, 123A, gate spacer) of the first gate electrode (Fig. 1A, 120A, gate electrodes) and a second portion that directly contacts a sidewall of the backside gate dielectric cap (Fig. 1A, 136, etch selective material, are dielectric materials, [0028]).
Regarding Claim 4, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 1, further comprising a backside source/drain contact structure (Fig. 1A, 138) contacting the other first source/drain region (Fig. 1A, 124A) of the pair of first source/drain regions (Fig. 1A, 124A).
Regarding Claim 7, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 4, further comprising a shared frontside (Fig. 1A, 101) source/drain contact structure (Fig. 1A, 125, [0026]) contacting the first source/drain region (Fig. 1A, 124A) of the pair of first source/drain regions (Fig. 1A, 124A) that is located on the dielectric pillar (Fig. 1A, 140, etch selective material, can be a dielectric material, [0028]) and one of the second source/drain regions (Fig. 1A, 124B) of the pair of second source/drain regions (Fig. 1A, 124B).
Regarding Claim 8, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 7, wherein the shared frontside (Fig. 1A, 101) source/drain contact structure (Fig. 1A, 125, [0026]) is connected to a frontside back-end-of-the-line (BEOL) structure (Fig. 1A, 101/105, frontside contact region, or BEOL, [0029]) by a metal via and a metal line (Fig. 1A, M0…MN, interconnect/metallization layers, [0029]).
Regarding Claim 9, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 8, further comprising a frontside (Fig. 1A, 101) source/drain contact structure (Fig. 1A, 125, [0026]) contacting the other second source/drain region (Fig. 1A, 124B) of the pair of second source/drain regions (Fig. 1A, 124B) and connected to the frontside BEOL structure (Fig. 1A, 101/105, frontside contact region, or BEOL, [0029]) by a metal via and at least one metal line (Fig. 1A, M0…MN, interconnect/metallization layers, [0029]).
Regarding Claim 10, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 8, further comprising a frontside (Fig. 1A, 101) shared first/second gate electrode contact structure (Fig. 1A, 120A/120B/122A/122B/123A/123B, gate electrodes/gate dielectrics/gate spacers) contacting both the first gate electrode (Fig. 1A, 120A) of the first gate structure (Fig. 1A, 120A/122A/123A, gate electrodes/gate dielectrics/gate spacers), and a second gate electrode (Fig. 1A, 120B) of the second gate electrode (Fig. 1A, 120B/122B/123B, gate electrodes/gate dielectrics/gate spacers) and connected to the frontside BEOL structure (Fig. 1A, 101/105, frontside contact region, or BEOL, [0029]) by yet another metal via and a yet another metal line (Fig. 1A, M0…MN, interconnect/metallization layers, [0029]).
Regarding Claim 11, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 1, wherein the second gate structure (Fig. 1A, 120B/122B/123B, gate electrodes/gate dielectrics/gate spacers) comprises a second gate electrode, and wherein the second gate electrode (Fig. 1A, 120B) is composed of a compositionally different work function metal (Fig. 1A, 120B, p-type work function metal, [0021]) than the first gate electrode (Fig. 1A, 120A).
Regarding Claim 12, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 1, wherein the first gate structure (Fig. 1A, 120A/122A/123A, gate electrodes/gate dielectrics/gate spacers) is wrapped around a portion of at least one first semiconductor channel material nanosheet (Fig. 1A, 116A, nanowires, [0013]) of a first nanosheet stack (Fig. 1A, 116A, nanowires, [0013]), and the second gate structure (Fig. 1A, 120B/122B/123B, gate electrodes/gate dielectrics/gate spacers) is wrapped around a portion of at least one second semiconductor channel material nanosheet (Fig. 1A, 116B, nanowires, [0013]) of a second nanosheet stack (Fig. 1A, 116B, nanowires, [0013]).
Regarding Claim 13, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 1, wherein the first FET (Fig. 1A, 104, lower device region) is spaced apart from the second FET (Fig. 1A, 108, upper device region) by a bonding dielectric layer (Fig. 1A, 106, isolation region, for example, with an insulator layer (e.g. oxide or nitride), [0018]; bonding material may further act as an isolation region, 106, [0027]).
Regarding Claim 19, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 1, wherein the first FET (Fig. 1A, 104, lower device region) and the second FET (Fig. 1A, 108, upper device region) are present in a first active area (annotated Figure 1A), and wherein at least one other second FET (Fig. 1A, 108, upper device region) stacked above at least one other first FET (Fig. 1A, 104, lower device region) are located in a second active area (annotated Figure 1A) that is spaced apart from the first active area (annotated Figure 1A), wherein one source/drain region (Fig. 1A, 124A) of the at least one other first FET (Fig. 1A, 104, lower device region) is electrically connected to a frontside BEOL structure (Fig. 1A, 101/105, frontside contact region, or BEOL, [0029]) by a combination of a backside source/drain contact structure (Fig. 1A, 138, [0013]), a backside metal connector (Fig. 1A, 128, backside interconnect), a frontside/backside deep via structure, a metal via and a metal line (Fig. 1A, M0…MN, interconnect/metallization layers, [0029]).
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Regarding Claim 20, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 19, wherein the backside metal connector (Fig. 1A, 128, backside interconnect) directly contacts a sidewall of a lower portion (annotated Figure 1A) of the frontside/backside deep via structure (Fig. 1A, M0…MN, interconnect/metallization layers, [0029]), and a sidewall of the backside source/drain contact structure (Fig. 1A, 138, [0013]).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over LILAK, in view of Li-Zhen Yu et al, (hereinafter YU), US 20230121408 A1.
Regarding Claim 3, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) Claim 1, wherein the dielectric pillar (Figs. 1A/6F, 140/356, etch selective material, can be a dielectric material, [0028], [0049]) has a height that is greater than a height (annotated Figure 6F) of the backside (Fig. 1A, 103, backside contact region) gate dielectric cap (Fig. 1A, 136, etch selective material, are dielectric materials, [0028]).
Though the etch selective dielectric material, 356 (or dielectric pillar) height is greater than the gate dielectric cap, 136, LILAK does not explicitly disclose the semiconductor device, wherein the dielectric pillar has a height that is greater than a height of the backside gate dielectric cap.
YU teaches the semiconductor device (Fig. 32A, integrated circuit structure), wherein the dielectric pillar (Fig. 32A, 270, front side dielectric cap include silicon nitride or other suitable dielectric material, [0048]) has a height that is greater than a height of the backside (Fig. 32A, 103, backside contact region) gate dielectric cap (Fig. 1A, 240, front-side dielectric caps, [0044]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LILAK to incorporate the teachings of YU, such that the semiconductor device, wherein the dielectric pillar has a height that is greater than a height of the backside gate dielectric cap, so that the dielectric materials 240 and 270 having different heights may have different etch selectivity for ease in manufacturing of the stacked integrated circuit (YU, [0044], [0048]).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over LILAK, in view of Alexander Reznicek et al, (hereinafter REZNICEK), US 20220085013 A1.
Regarding Claim 5, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 4, further comprising an inner spacer (annotated Figure 1A) separating the backside source/drain contact structure (Fig. 1A, 138) from the first gate electrode (Fig. 1A, 120A, gate electrodes).
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LILAK does not explicitly disclose the semiconductor device of Claim 4, further comprising an asymmetric inner spacer separating the backside source/drain contact structure from the first gate electrode.
REZNICEK teaches the semiconductor device (Fig. 13, 1300, inverter structure, [0132]), further comprising an asymmetric inner spacer (annotated Figure 13) separating the backside source/drain contact structure (Fig. 13, 850/850C, [0135]) from the first gate electrode (Fig. 13, 1250/1250A, gate metal, [0138]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LILAK to incorporate the teachings of REZNICEK, such that the semiconductor device, further comprising an asymmetric inner spacer separating the backside source/drain contact structure from the first gate electrode, so that the inner spacers provide dielectric isolation between the S/D and the gate structure (REZNICEK, Figure 13, [0047]).
Claim(s) 6, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over LILAK, in view of Guo-Huei Wu et al, (hereinafter WU), US 20200328212 A1.
Regarding Claim 6, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 4, further comprising a backside back-end-of-the-line (BEOL) structure (Figs. 1A, 102) located beneath the first FET (Fig. 1A, 104, lower device region) and connected to the backside source/drain contact structure (Fig. 1A, 138).
LILAK does not explicitly disclose the semiconductor device, further comprising a backside back-end-of-the-line (BEOL) structure located beneath the first FET and connected to the backside source/drain contact structure by a backside VSS power source.
WU teaches the semiconductor device (Fig. 2A, semiconductor devices, a complementary FET or CFET, [0034]), further comprising a backside back-end-of-the-line (BEOL) structure (Fig. 2A, 330, bottom via contact) located beneath the first FET (Fig. 2A, 111, NMOS) and connected to the backside source/drain contact structure (Fig. 2A, 130/135) by a backside VSS power source (Fig. 2A, 320, supply line Vss[0046]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LILAK to incorporate the teachings of WU, such that the semiconductor device, further comprising a backside back-end-of-the-line (BEOL) structure located beneath the first FET and connected to the backside source/drain contact structure by a backside VSS power source, so that one of the power supply lines (power rail) Vss, 320 (e.g. negative or ground potential) for supplying power to the CFET is located below the CFET, (WU, [0039]).
Regarding Claim 17, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 1, further comprising a frontside/backside deep via structure (Fig. 1A, M0…MN, interconnect/metallization layers, [0029]) having a first end electrically connected to one of the second source/drain regions (Fig. 1A, 124B) of the pair of source/drain regions (Fig. 1A, 124B) by a frontside second gate (Fig. 1A, 120B) source/drain contact structure (Fig. 1A, 125).
LILAK does not explicitly disclose the semiconductor device, further comprising a frontside/backside deep via structure having a first end electrically connected to one of the second source/drain regions of the pair of source/drain regions by a frontside second gate source/drain contact structure, and a second end electrically connected to a backside BEOL structure by a VDD power source.
WU teaches the semiconductor device (Fig. 2A, semiconductor devices, a complementary FET or CFET, [0034]) of Claim 1, further comprising a frontside/backside deep via structure (Fig. 2A, 340/342/344, via contact, [0048]) having a first end electrically connected to one of the second source/drain regions (Fig. 2A, 230/235) of the pair of source/drain regions (Fig. 2A, 230/235) by a frontside second gate (Fig. 2A, 120) source/drain contact structure (Fig. 2A, 230/235), and a second end electrically connected to a backside BEOL structure (Fig. 2A, 330, bottom via contact) by a VDD power source (Fig. 2A, 130/135) by a backside VSS power source (Fig. 2A, 310/350/360/370, supply line Vdd/signal lines, [0046]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LILAK to incorporate the teachings of WU, such that the semiconductor device, further comprising a frontside/backside deep via structure having a first end electrically connected to one of the second source/drain regions of the pair of source/drain regions by a frontside second gate source/drain contact structure, and a second end electrically connected to a backside BEOL structure by a VDD power source, so that one of the power supply lines (power rail) Vdd, 310 (e.g. positive potential) for supplying power to the CFET is located below the CFET, (WU, [0039]).
Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over LILAK, in view of Aaron D. Lilak, (hereinafter LILAK2), US 20200006329 A1.
Regarding Claim 14, LILAK teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]) of Claim 1.
LILAK does not explicitly disclose the semiconductor device, further comprising a first gate cut structure located adjacent to the first FET, and a second gate cut structure located adjacent to the second FET.
LILAK2 teaches the semiconductor device (Fig. 2a, integrated circuit, [0002-0003]), further comprising a first gate cut structure (Fig. 2a, 109a/109b/111, iso wall/gate spacers, dielectric/insulator material, [0028-0029]) located adjacent to the first FET (Fig. 2a, lower device region, [0032]) and a second gate cut structure (Fig. 2a/3, 113a/113b/321, iso wall/spacers, dielectric/insulator material, [0035]) located adjacent to the second FET (Fig. 2a, upper device region, [0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LILAK to incorporate the teachings of LILAK2, such that the semiconductor device, further comprising a first gate cut structure located adjacent to the first FET, and a second gate cut structure located adjacent to the second FET, so that the isolation wall with variable etch selectivity and etch rate compared to the STI has been implemented to effectively isolate the fin structures both in the lower and upper device region (LILAK2, [0028], [0034-0035]).
Regarding Claim 15, LILAK as modified by LILAK2 teaches the semiconductor device of Claim 14.
LILAK2 further teaches the semiconductor device (Fig. 2a, integrated circuit, [0002-0003]), wherein the first gate cut structure (Fig. 2a, 109a/109b/111, iso wall/gate spacers, dielectric/insulator material, [0028-0029]) comprises a first outer dielectric material liner (Fig. 2a, 111, gate spacers, may be silicon nitride or silicon dioxide etc., [0030]) encasing a first inner core dielectric material (Fig. 2a, 109a/109b, iso wall, dielectric/insulator material, [0028-0029]), and wherein the second gate cut structure (Fig. 2a/3, 113a/113b/321, iso wall/spacers, dielectric/insulator material, [0035]) comprises a second outer dielectric material liner (Fig. 3, 321, spacers, silicon nitride or silicon oxynitride etc., [0046]) encasing a second inner core dielectric material (Fig. 2a, 113a/113b, iso wall, dielectric/insulator material, [0035]).
Regarding Claim 16, LILAK as modified by LILAK2 teaches the semiconductor device of Claim 14.
LILAK2 further teaches the semiconductor device (Fig. 2a, integrated circuit, [0002-0003]), wherein the first gate structure (Fig. 2a, 109a/109b/111, iso wall/gate spacers, dielectric/insulator material, [0028-0029]) and the second gate structure (Fig. 2a/3, 113a/113b/321, iso wall/spacers, dielectric/insulator material, [0035]) are spaced apart by a bonding dielectric layer (Fig. 3, 101, [0036]).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over LILAK, in view of WU, and further in view of Mark I. Gardner et al, (hereinafter GARDNER), US 20220238520 A1.
Regarding Claim 18, LILAK as modified by WU teaches the semiconductor device of Claim 17.
LILAK further teaches the semiconductor device (Fig. 1A, stacked transistor architecture, [0012]), wherein the frontside/backside deep via structure (Fig. 1A, M0…MN, interconnect/metallization layers, [0029]) has an upper via portion encased in a second outer dielectric material liner (Fig. 1A, the contact structures, 125 include a conductive liner or barrier layer, deposited in a contact trench formed in an insulator layer over the source and drain regions, 124B, [0026]), and a middle portion (Fig. 1A, 106, isolation region) that is encased in a bonding dielectric layer (Fig. 1A, 106, isolation region, bonding material (e.g., silicon nitride, SiOx) may further act as an isolation region, 106, [0027]) that is located between the first FET (Fig. 1A, 103, lower device region) and the second FET (Fig. 1A, 108, upper device region).
LILAK as modified by WU does not explicitly disclose the semiconductor device, wherein the frontside/backside deep via structure has an upper via portion encased in a second outer dielectric material liner, a lower portion that is encased in a first outer dielectric material liner.
GARDNER teaches the semiconductor device (Fig. 24, 1800, fourth semiconductor device), wherein the frontside/backside deep via structure (Figs. 9-15/24, planarized via etching to form dielectric spacers, 910/2310, [0032], [0035]) has an upper via portion (Fig. 24, 2332, PMOS device) encased in a second outer dielectric material liner (Fig. 24, 2440/1880, dielectric material/second dielectric layer), a lower portion (Fig. 24, 2331, NMOS device) that is encased in a first outer dielectric material liner (Fig. 24, 2440/1870, dielectric material/first dielectric layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LILAK as modified by WU to incorporate the teachings of GARDNER, such that the semiconductor device, wherein the frontside/backside deep via structure has an upper via portion encased in a second outer dielectric material liner, a lower portion that is encased in a first outer dielectric material liner, so that a dielectric material 640/2440 can be deposited to encapsulate the PMOS (or NMOS) devices 631/632/2431/2432 and be planarized via, for example, CMP (GARDNER, [0032]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20190157310 A1 – Figure 7J
STATEMENT OF RELEVANCE – Backside deep vias encased within the backside contact insulator, which may include any suitable dielectric material [0052].
US 20220216340 A1 – Figure 17
STATEMENT OF RELEVANCE – The frontside contact, 278 is spaced apart from the stack of second channel members by the top source/drain feature [0042].
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812 /CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812