DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, 7-9, 11, and 15-16, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Duarte-Guevara et al. (Enhanced Biosensing Resolution with Foundry Fabricated Individually Addressable Dual-Gated ISFETs, cited in IDS filed 07/31/2023).
Regarding claim 1, Duarte-Guevara discloses a device (Figure 1), comprising:
a source region and a drain region disposed in a substrate (see: S and D embedded into Active Silicon layer);
a sensing region disposed in the substrate (see: region of the top surface of the Active Silicon layer between the PDMS well sidewalls);
a channel region disposed in the substrate and between the source region and the drain region (see: region of Active Silicon layer which extends between D and S);
a gate dielectric disposed on a first surface of the sensing region and on a first surface of the channel region (see: Gate Dielectric disposed underneath the region of the top surface of the Active Silicon layer between the PDMS well sidewalls and the region of Active Silicon layer which extends between D and S);
a sensing well disposed on a second surface of the sensing region (see: PDMS well disposed above the top surface of the Active Silicon layer); and
a gate electrode disposed on a first surface of the gate dielectric and overlapping the sensing region and the channel region (see: Individual back-gate disposed underneath the Gate Dielectric, the region of the top surface of the Active Silicon layer between the PDMS well sidewalls and the region of Active Silicon layer which extends between D and S).
Regarding claim 2, Duarte-Guevara further discloses an elongated side of the sensing region extends along a first direction (ABSTRACT Figure, see: longitudinal axis of the region of the top surface of the Active Silicon layer between the PDMS well sidewalls) and an elongated side of the channel region extends along a second direction that is perpendicular to the first direction region (ABSTRACT Figure, see: region of Active Silicon layer which extends between D and S, in a direction perpendicular to the longitudinal axis of the region of the top surface of the Active Silicon layer between the PDMS well sidewalls).
Regarding claim 4, Duarte-Guevara further discloses the sensing well is overlapping with the sensing region and the channel region (Figure 1, see: PDMS well is disposed above the region of the top surface of the Active Silicon layer between the PDMS well sidewalls and the region of Active Silicon layer which extends between D and S).
Regarding claim 5, Duarte-Guevara further discloses the sensing well is overlapping with the sensing region, the channel region, the source region, and the drain region (Figure 1, see: PDMS well is disposed above the region of the top surface of the Active Silicon layer between the PDMS well sidewalls, D, S, and the region of Active Silicon layer which extends between D and S).
Regarding claim 7, Duarte-Guevara further discloses the sensing well is configured to hold a liquid analyte (Figure 1, see: fluid contained in PDMS well).
Regarding claim 8, Duarte-Guevara further discloses a buried oxide layer disposed on a second surface of the channel region (Figure 1, see: Silicon Oxide layer above the top surface of the Active Silicon layer containing D and S, and embedded underneath another Active Silicon layer).
Regarding claim 9, Duarte-Guevara further discloses a buried oxide layer disposed on the substrate (Figure 1, see: Silicon Oxide layer embedded underneath another Active Silicon layer), wherein the sensing well is disposed in the buried oxide layer (Figure 1, see: PDMS well extends through the Silicon Oxide layer).
Regarding claim 11, Duarte-Guevara discloses a device (Figure 1), comprising:
a buried oxide layer disposed on a first surface of a substrate (see: Silicon Oxide layer above the top surface of the Active Silicon layer containing D and S, and embedded underneath another Active Silicon layer);
a gate dielectric disposed on a second surface of the substrate (see: Gate Dielectric disposed within the Active Silicon layer);
a gate electrode disposed on a first surface of the gate dielectric (see: Individual back-gate disposed underneath the Gate Dielectric);
a sensing region disposed in the substrate (see: region of the top surface of the Active Silicon layer between the PDMS well sidewalls);
a channel region disposed in the substrate and abutting the sensing region (see: region of Active Silicon layer which extends between D and S, and is disposed underneath the region of the top surface of the Active Silicon layer between the PDMS well sidewalls); and
a source region and a drain region disposed in the substrate and abutting the sensing region substrate (see: S and D embedded into Active Silicon layer and underneath the region of the top surface of the Active Silicon layer between the PDMS well sidewalls).
Regarding claim 15, Duarte-Guevara further discloses a sensing well disposed on the sensing region (Figure 1, see: PDMS well disposed above the top surface of the Active Silicon layer).
Regarding claim 16, Duarte-Guevara further discloses a sensing well disposed on the sensing region and the channel region (Figure 1, see: PDMS well disposed above the top surface of the Active Silicon layer and the region of Active Silicon layer which extends between D and S).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3, 6, 10, 12-14, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duarte-Guevara et al. (Enhanced Biosensing Resolution with Foundry Fabricated Individually Addressable Dual-Gated ISFETs, cited in IDS filed 07/31/2023), in view of Kim et al. (An extended gate FET-based biosensor integrated with a Si microfluidic channel for detection of protein complexes, cited in IDS filed 07/31/2023).
Regarding claim 3, Duarte-Guevara further discloses the sensing well is overlapping with the sensing region (Figure 1, see: PDMS well disposed above the top surface of the Active Silicon layer).
Duarte-Guevara does not explicitly disclose the sensing well is non-overlapping with the channel region.
Kim teaches an analogous FET based biosensor having an extended gate configuration to enable the microfluidic channel to be offset from the source, drain, and channel of the FET (Fig. 1). It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to configure the biosensor disclosed by Duarte-Guevara into an extended gate configuration, as taught by Kim, in order to provide for the advantages of insensitivity to temperature and light, simple method of passivation and packaging, flexibility of shape of the extended gate (Kim: pg. 488/col. 2/para. 2).
Regarding claim 6, Duarte-Guevara further discloses the device is configured to perform electrical label-free detection of DNA replication (pg. 8366/CONCLUSIONS).
Duarte-Guevara does not explicitly disclose the sensing region is configured to bind target molecules.
Kim teaches an analogous FET based biosensor having a gold extended gate metal to form a self-assembled monolayer with thiol for binding streptavidin and biotin (Fig. 3). It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate a functionalization layer in the biosensor disclosed by Duarte-Guevara, as taught by Kim, in order to provide for protein sensing functionality and increased specificity in DNA detection (Kim: pg. 488/col. 2/para. 2).
Regarding claim 10, Duarte-Guevara does not explicitly disclose the gate electrode is H-shaped or T-shaped.
Kim teaches an analogous FET based biosensor having a “T” shaped extended gate configuration to enable the microfluidic channel to be offset from the source, drain, and channel of the FET (Fig. 1). It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to configure the biosensor disclosed by Duarte-Guevara into an extended gate configuration, as taught by Kim, in order to provide for the advantages of insensitivity to temperature and light, simple method of passivation and packaging, flexibility of shape of the extended gate (Kim: pg. 488/col. 2/para. 2).
Regarding claim 12, Duarte-Guevara does not explicitly disclose the sensing region and the channel region are disposed in a T-shaped layout configuration.
Kim teaches an analogous FET based biosensor having a pair of extended gate electrodes and a microchannel arranged in a “T” shaped configuration (Fig. 2). It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to configure the biosensor disclosed by Duarte-Guevara into an extended gate configuration, as taught by Kim, in order to provide for the advantages of insensitivity to temperature and light, simple method of passivation and packaging, flexibility of shape of the extended gate (Kim: pg. 488/col. 2/para. 2).
Regarding claim 13, Duarte-Guevara does not explicitly disclose an other sensing region disposed in the substrate, wherein the source region and the drain region are disposed between the sensing region and the other sensing region.
Kim teaches an analogous FET based biosensor having an extended gate configuration to enable the microfluidic channel to be offset from the source, drain, and channel of the FET (Fig. 1), wherein the source and drain wells (see: p+ regions) are disposed between the gate electrode (see: “T” shaped Cr/Au electrode) and the source and drain contacts (see: “L” shaped Cr/Au electrodes). It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to configure the biosensor disclosed by Duarte-Guevara into an extended gate configuration, as taught by Kim, in order to provide for the advantages of insensitivity to temperature and light, simple method of passivation and packaging, flexibility of shape of the extended gate (Kim: pg. 488/col. 2/para. 2).
Regarding claim 14, modified Duarte-Guevara further discloses the sensing region, the other sensing region, and the channel region are disposed in an H-shaped layout configuration (Kim: Fig. 1, see: “H” shape defined by the source and drain regions “p+” and the “T” shaped gate electrode).
Regarding claim 17, Duarte-Guevara discloses a method (pg. 8360-8361/Device Fabrication), comprising:
depositing a gate dielectric on a first surface of a substrate (Figure 1, see: Gate Dielectric disposed underneath the Active Silicon layer);
depositing a gate electrode on a first surface of the gate dielectric (Figure 1, see: Individual back-gate disposed underneath the Gate Dielectric);
forming a first sensing region in the substrate and abutting a second surface of the gate dielectric (Figure 1, see: region of the top surface of the Active Silicon layer above the Gate Dielectric);
forming a channel region in the substrate and abutting the first sensing region (Figure 1, see: region of Active Silicon layer which extends between D and S, and is disposed underneath the region of the top surface of the Active Silicon layer above the Gate Dielectric); and
forming a source region and a drain region in the substrate and abutting the first sensing region (Figure 1, see: D and S disposed underneath the region of the top surface of the Active Silicon layer above the Gate Dielectric).
Duarte-Guevara does not explicitly disclose forming a second sensing region in the substrate.
Kim teaches an analogous FET based biosensor having a pair of extended gate electrodes forming two sensing regions (Fig. 2). It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to configure the biosensor disclosed by Duarte-Guevara into an extended gate configuration, as taught by Kim, in order to provide for the advantages of insensitivity to temperature and light, simple method of passivation and packaging, flexibility of shape of the extended gate (Kim: pg. 488/col. 2/para. 2).
Regarding claim 18, Duarte-Guevara further discloses the device is configured to perform electrical label-free detection of DNA replication (pg. 8366/CONCLUSIONS).
Modified Duarte-Guevara does not explicitly disclose binding target molecules to the first and second regions.
Kim teaches an analogous FET based biosensor having a gold extended gate metal to form a self-assembled monolayer with thiol for binding streptavidin and biotin (Fig. 3). It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate a functionalization layer in the biosensor disclosed by modified Duarte-Guevara, as taught by Kim, in order to provide for protein sensing functionality and increased specificity in DNA detection (Kim: pg. 488/col. 2/para. 2).
Regarding claim 19, Duarte-Guevara further discloses depositing a buried oxide layer on a second surface of the substrate (Figure 1, see: Silicon Oxide layer embedded underneath another Active Silicon layer).
Regarding claim 20, Duarte-Guevara further discloses forming a sensing well on a second surface of the substrate (Figure 1, see: PDMS well).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT J EOM whose telephone number is (571)270-7075. The examiner can normally be reached Monday-Friday (9:00AM-5:00PM).
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/ROBERT J EOM/ Primary Examiner, Art Unit 1797
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