DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/09/2023, 05/02/2024. The submission is following the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 11 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chung et al., (US 2023/0411431 A1).
Regarding claim 11, Chung et al., disclose (Fig.6) an image sensor, comprising: at least one substrate (104a and 104b); and a set of pixels (106s) on the at least one substrate (104a and 104b, see Fig.6), a pixel (106) in the set of pixels (106s) including, a first substrate portion (104a) of the at least one substrate (104a and 104b); a second substrate portion (104b) of the at least one substrate (104a and 104b) , the second substrate portion (104b) electrically isolated from the first substrate portion (paragraph [0040], the first substrate portion including the terminal Tsub1 and the second substrate portion including terminal Tsub2 are electrically isolated from each other); a photodiode (106); a charge storage node (FD); a charge transfer gate (114) on and biased by the first substrate portion (104a, Fig.6 shows the transfer gate 114 disposed and biased by the Tsub1), the charge transfer gate (114) operable to selectively couple the photodiode (106) to the charge storage node (FD); and at least one transistor (120) on and biased by the second substrate portion (104b, Fig.6, the transfer gate 120 disposed 104b and biased by the Tsub2).
Regarding claim 14, Chung et al., as discussed in claim 11, disclose the at least one substrate (104a and 104b) includes a substrate stack (see Fig.3), the substrate stack including a first substrate (104a) and a second substrate (104b); the first substrate (104a) includes the first substrate portion (104a); and the second substrate (104b) includes the second substrate portion (104b).
5. Claims 11, 12, 15, 18-23, 25, 27, 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mas et al., (US 2022/0272291 A1).
Regarding claim 11, Mas et al., disclose an image sensor, comprising: at least one substrate (302, Fig.3) ; and a set of pixels (10) on the at least one substrate (Fig. 3 and paragraph [0068] “an array 300 of pixels 10. Array 300 is implemented inside and on top of a semiconductor substrate 302”),
a pixel (10) in the set of pixels (see Fig.3) including, a first substrate portion of the at least one substrate; a second substrate portion of the at least one substrate, the second substrate portion electrically isolated from the first substrate portion (Fig.3 and paragraph [0068], the substrate 302 is divided by insulating structures or trenches 304, and each pixel 10 is in a portion of substrate 302; Or the first substrate portion is the area containing the pixel 10 and the second portion of the substrate is the outside of the pixel) ;
a photodiode (“PD”, Fig.3); a charge storage node (107, Fig. 3 shows mem1, mem2 being connected to node 107 as charge storage nodes); a charge transfer gate (TGmem1/Tgmem2, Fig.s 1, 3) on and biased by the first substrate portion (see Fig.1, 3, and paragraph [0071], TGmem1/Tgmem2 is on the isolated substrate portion because “each pixel 10 comprises a photoconversion area PD and at least two assemblies E1, E2, each comprising a memory area mem1, mem2 and a transfer gate TGmem1, TGmem2”, and biased by the Vpixsub as shown in Fig.3), the charge transfer gate (TGmem1/Tgmem2, Fig.1) operable to selectively couple the photodiode (PD) to the charge storage node (107); and at least one transistor on and biased by the second substrate portion (as stated in [0071] above, each pixel 10 comprises… a transfer gate TGmem1, TGmem2 within a portion of a substrate, so the two transistors such as TGmem1, TGmem2 are both within the second pixel’s isolated substrate portion biased by the Vpixsub; OR in case, the second portion is outside of the pixel 10, which contain transistors such as reset transistor 114 or transistor 122 biased differently).
Regarding claim 12, Mas et al., as discussed in claim 11, disclose further comprising a control circuit (“circuit BIAS”, Fig.3, paragraph [0075], “ a circuit BIAS configured to deliver, for each pixel 10 and at least during each integration phase, voltage Vpixsub to the portion of substrate 302 having pixel 10 arranged inside and on top of it”) operable to bias each of the first substrate portion and the second substrate portion independently of other substrate portions of the at least one substrate (paragraph [0070], “pixels 10 are gathered in groups of neighboring pixels, each group of pixels being implemented inside and on top of a portion of substrate 302 electrically insulated, by structures 304, from portions of substrate 302 having other groups of pixels 10 implemented inside and on top thereof”, and paragraph [0079], “where the pixels of array 300 are organized in groups and where each group of pixels 10 is electrically insulated from the other pixel groups by a structure 304, voltage Vpixsub is for example applied to each portion of substrate 302 having a group of pixels 10 implemented inside and on top of it” , indicating each substrate portion for each pixel is electrically isolated from each other’s by structures 304, and applying the Vpixsub to each isolated substrate portion).
Regarding claim 15, Mas et al., as discussed in claim 11, disclose the at least one transistor includes at least one of: a charge storage node reset transistor; a charge storage node readout transistor; or a readout select transistor (Fig.1, readout transistor 112/ reset transistor 114).
Regarding claim 18, Mas et al., disclose (Figs.3) an image sensor, comprising:
a semiconductor substrate (“semiconductor substrate 302”, [0068]);
a pixel (pixel 10, Fig.3) including, a photodiode (“PD”, Fig. 1 and paragraph [0071], “each pixel 10 comprises, similarly to the pixel 1 of FIG. 1, a photoconversion area PD”);
a charge storage node (107); and a charge transfer gate (TGmem1/TGmem2, Fig.1 and paragraph [0071]) disposed on and biased by the semiconductor substrate (302, see Figs. 1-3, and [0072]), “ for each pixel 10, and at least during each integration phase, a bias voltage Vpixsub different from ground GND, that is, non-zero, to a portion of substrate 302 having pixel 10 arranged inside and on top of it”), the charge transfer gate (TGmem1/TGmem2, Fig.1) operable to selectively connect the photodiode (PD) to the charge storage node (107, paragraph [0073] and Fig. 1, for each pixel 10, each transfer gate TGmem1 or TGmem2 coupling area PD of the pixel to charge storage node l07”); and
a control circuit (a circuit BIAS, Fig.3 paragraphs [0063], [0076]) operable to dynamically bias the semiconductor substrate to three or more different potentials (“Vpixsub”, Fig.3 shows three separate Vpixsub potentials), the different potentials applied during different modes of operation of the pixel (paragraph [0075] and Fig.3 show the circuit BIAS configured to deliver Vpixsub to each substrate portion, and paragraph [0072]. “for each pixel 10, and at least during each integration phase, a bias voltage Vpixsub different from ground GND”, and paragraph [0074], “voltage Vpixsub is in the range from and excluding 0 V to 1.5 V; and voltage Vpixsub is in the range from and excluding 0 V to −1.5V, for example, when voltage Vpixsub is applied to the substrate of a transfer gate, which is then blocked when it receives a control potential equal to ground GND and conductive when it receives a potential smaller than a negative threshold value”, indicating that the multiple substrate biases are applied during the different voltage levels and during different modes such as the integration phase, ground GND, and rang from -1.5 to 1.5 voltage ).
Regarding claim 19, Mas et al., as discussed in claim 18, disclose a set of pixel transistors (112, 114, 116, Fig. 1) disposed on and biased by the semiconductor substrate (302, Figs.1-3), the set of pixel transistors operable to reset and read the pixel (paragraph [0047] “the reset transistor 114, and a transistor 116 assembled as a follower source” that are reset and read from the pixel), the set of pixel transistors (112, 114, 116) including, a charge storage node reset transistor (114); a charge storage node readout transistor (116); and a readout select transistor (112).
Regarding claim 20, Mas et al., as discussed in claim 18, disclose the control circuit (the circuit BIAS, Fig.3) being operable to, bias the semiconductor substrate ( paragraph [0075], sensor 3 comprises a circuit BIAS configured to deliver, for each pixel 10 and at least during each integration phase) to a first potential, during a charge transfer mode (during each integration phase, [0073] [0083]) (paragraphs [0072], [0073] and [0083], during each integration phase, each transfer gate coupling area PD of the pixel to a memory area of the pixel is blocked.. so that the control signal delivered to this transfer gate is at ground potential GND) in which charge is transferred from the photodiode (PD) to the charge storage node (107, Fig. 7);
bias the semiconductor substrate to a second potential (during each readout phase, [0084]), different from the first potential (during each integration phase, [0083]), during a readout mode in which charge is read from the charge storage node (117) (Figs. 3, 7 and paragraph [0084], during each readout phase, Vpixsub are maintained at ground GND, whereby the gates are maintained blocked), and bias the semiconductor substrate to a third potential (during standby, paragraphs [0077], [0093]), different from the first potential (during each integration phase ) and the second potential (during each readout phase), during all modes of operation of the pixel other than the charge transfer mode and the readout mode (paragraph [0077[, “circuit BIAS is further configured to draw voltage Vpixsub to ground GND when sensor 3 is at standby or unused, that is, outside of integration phases and readout phases”).
Regarding claim 21, Mas et al., disclose a pixel of an image sensor, comprising:
a set of substrate portions, each substrate portion of the set of substrate portions electrically isolated from other substrate portions of the set of substrate portions (Fig.3 and paragraph [0068], the substrate 302 is divided by insulating structures or trenches 304, and each pixel 10 is in portions of substrate 302);
a photodiode (“PD”, Fig.3) on a first substrate portion of the set of substrate portions (see Fig.3); a charge storage node (107, Fig.1) on the first substrate portion (Fig. 1),
at least one charge transfer gate (TGmem1/ TGmem2, Fig.1) on the first substrate portion (paragraph [0043] and Fig.1, the TGmem1/ TGmem2 is in the same substrate portion as the PD)
, each charge transfer gate (TGmem1/ TGmem2, Fig.1) of the at least one charge transfer gate forming at least part of a charge transfer path between the photodiode (PD) and the charge storage node (107);
a readout circuit (110, Fig.1) coupled to the charge storage node (107) and formed on a second substrate portion of the set of substrate portions (see Fig.1, the readout circuit 110 formed in a separate substrate portion);
and a control circuit (“circuit BIAS”, Fig.3, paragraph [0075])
operable to dynamically bias each substrate portion of the set of substrate portions independently of each other substrate portion of the set of substrate portions (see Fig.3 and paragraphs [0075], [0076], “the circuit BIAS is used to apply Vpixsub individually/separately to each pixel substrate portion).
Regarding claim 22, Mas et al., as discussed in claim 21, disclose a reset transistor (114, Fig.1, and paragraph [0050], “transistor 114 receives a control signal RST”) coupled to the charge storage node (107) and formed on the second substrate portion of the set of substrate portions (see Fig.1, the transistor 114 is formed on a separate substrate portion, which is not the substrate portion holding the PD and charge storage node mem1/mem2 including node 107).
Regarding claim 23, Mas et al., as discussed in claim 21, disclose the at least one charge transfer gate (TGmem1/ TGmem2, Fig.1) consists of one charge transfer gate (TGmem1/TGmem2).
Regarding claim 25, Mas et al., as discussed in claim 21, disclose the first substrate portion (the portion where the PD, mem1/mem2, and the transfer gates, see Fig.1) and the second substrate portion (where the 110 is located) are different portions of a same substrate (see Figs.1and 3, both are portions of the same substrate 302, and electrically isolated by the 304, paragraphs [0068]-[0070]).
Regarding claim 27, Mas et al., as discussed in claim 21, disclose the control circuit (the “circuit BIAS”, Fig.3) being operable to dynamically bias the first substrate portion (paragraph [0075], “the circuit BIAS configured to deliver, for each pixel 10”, indicating the circuit BIAS is used to apply the Vpixsub to the substrate portion under each pixel 10) to different voltages at different times (paragraphs [0075] and [0084], during each readout phase, Vpixsub are maintained at ground GND, whereby the gates are maintained blocked, paragraph [0077[, “circuit BIAS is further configured to draw voltage Vpixsub to ground GND when sensor 3 is at standby or unused, that is, outside of integration phases and readout phases”), all of the different voltages (GND from [0077], 0V-1.5 from [0074]), between a pair of power rail voltages of the image sensor (all the voltage between the power rails from GND (0V) to “power supply potential Vsupply, for example, in the order of 2.8 V”, [0060]).
Regarding claim 28, Mas et al., as discussed in claim 21, disclose the control circuit (the “circuit BIAS”, Fig.3) is operable to dynamically bias the first substrate portion to different voltages at different times (paragraphs [0075] and [0084], during each readout phase, Vpixsub are maintained at ground GND, whereby the gates are maintained blocked, paragraph [0077[, “circuit BIAS is further configured to draw voltage Vpixsub to ground GND when sensor 3 is at standby or unused, that is, outside of integration phases and readout phases”), at least one voltage of the different voltages outside a pair of power rail voltages of the image sensor (paragraph [0074], “According to another example, voltage Vpixsub is in the range from and excluding 0 V to −1.5V, for example, from −0.1V to −1.5 V”, the range -0.1V to -1.5V is outside of the power rails which are 0V to 2.8V, as stated above from [0060]).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Mas et al., in view of Kim et al., (US 2025/0221077 A1).
Regarding claim 13, Mas et al., as discussed in claim 11, disclose the at least one substrate including a substrate that defines both the first substrate portion and the second substrate portion and at least one wall in the substrate electrically isolates the second substrate portion from the first substrate portion (Fig.3 and paragraph [0068], the substrate 302 is divided by insulating structures or trenches 304, and each pixel 10 is in a portion of substrate 302). Mas et al., do no disclose the wall being as oxide as claimed. Kim et al., disclose one oxide wall in the substrate electrically isolates the second substrate portion from the first substrate portion ( the first isolation pattern 151 may include an oxide, [0052] and Fig. 5). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mas et al., by utilizing the teaching of Kim et al, in order to prevent better unwanted electrical flow between the substate portions.
Claims 24, 26 are rejected under 35 U.S.C. 103 as being unpatentable over Mas et al., in view of Fadida (US 2024/0388811 A1).
Regarding claim 24, Mas et al., as discussed in claim 21, do not disclose the global charge transfer gate electrically coupled to the photodiode; and a pixel charge transfer gate electrically coupled between the global charge transfer gate and the charge storage node as claimed. Fadida discloses (Fig.5) a global charge transfer gate (GS) electrically coupled to the photodiode (Pd); and a pixel charge transfer gate (TX) electrically coupled between the global charge transfer gate (GS) and a charge storage node (FD). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mas et al., by utilizing the teaching of Fadida, in order to provide better timing control and reduce noise charge transfer.
Regarding claim and 26, Mas et al., as discussed in claims 11 and 21, do not disclose the first substrate portion being part of a first substrate; and the second substrate portion is part of a second substrate as claimed. Fadida discloses a first substrate portion being part of a first substrate; and a second substrate portion is part of a second substrate (Fig. 1 and paragraph [0027]). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mas et al., by utilizing the teaching of Fadida, in order to lower or reduce noise, improving the image quality.
Allowable Subject Matter
7. Claims 16, 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 16: the prior art fails to disclose the photodiode being a first photodiode; the charge transfer gate is a first charge transfer gate; the pixel further comprises, a third substrate portion of the at least one substrate; a second photodiode; and a second charge transfer gate on and biased by the third substrate portion.
Claim 17 depends on claim 16.
8. Claim 1 is allowable.
Claims 2-10 depend on claim 1.
Regarding claim 1, the prior art fails to disclose an image sensor comprising a set of charge transfer gates, each charge transfer gate of the set of charge transfer gates disposed on and biased by a different substrate portion of the set of substrate portions, and each charge transfer gate of the set of charge transfer gates operable to selectively connect a respective photodiode of the set of photodiodes to the charge storage node.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAI THI NGOC TRAN whose telephone number is (571)-272- 3456. The examiner can normally be reached Monday-Friday: 9:00-5:30pm.
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/M.T.T./Examiner, Art Unit 2878
/GEORGIA Y EPPS/Supervisory Patent Examiner, Art Unit 2878