DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 6/17/26. Claims 1-20 are pending. Claims 13-20 are withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The rejection of claim(s) 1-12 under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al. (US PGPub 2020/0212229, hereinafter referred to as “Hu”).
Hu discloses the semiconductor device as claimed. See figures 1-18 and corresponding text, where Hu teaches, in claim 1, an integrated circuit device, comprising:
a substrate (102) of a first conductivity type (figure 2; [0013]);
a buried layer (104) of a second conductivity type located in the substrate (102) (figure 2; [0013]);
a central isolated region (120) of the second conductivity type located over the buried layer (104); (figure 2; [0014-0015])
a first floating poly isolation structure (126) located in the substrate (102) to surround the central isolated region (120) and to extend down to and surround the buried layer (104);
a second floating poly isolation structure (136) located in the substrate (102) to surround the first floating poly isolation structure (126);
a shallow ring region (122) of the second conductivity type located in the substrate (102) between at least a portion of the first floating poly isolation structure (126) and a portion of the second first floating poly isolation structure (126) (figure 2; [0016-0017]); and
a first conductive interconnect structure (162) for electrically shorting the central isolated region (120) to the shallow ring region (122), wherein the first floating poly isolation structure (126) is shorted to the second floating poly isolation structure (136) (figure 2; [0024-0025], [0050]).
Hu teaches, in claim 2, where the buried layer extends laterally only below the central isolated region and does not extend laterally past the first floating poly isolation structure (figure 2; [0014-0015]).
Hu teaches, in claim 3, where the first and second floating poly isolation structures each comprise a polysilicon structure formed in an insulating liner layer (figure 2; [0014-0015]).
Hu teaches, in claim 4, where the central isolated region is electrically shorted to the shallow ring region by the first conductive interconnect structure formed with a metal interconnect structure formed over the substrate to electrically connect the central isolated region to the shallow ring region (figure 2; [0016-0017]).
Hu teaches, in claim 5, where the first and second floating poly isolation structures are electrically shorted by the second conductive interconnect structure formed with a metal interconnect structure formed over the substrate to electrically connect the first floating poly isolation structure to the second floating poly isolation structure (figure 2; [0016-0017]).
Hu teaches, in claim 6, where the first and second floating poly isolation structures are electrically shorted by the second conductive interconnect structure formed with an insulated polysilicon interconnect structure formed in the substrate to electrically connect the first floating poly isolation structure to the second floating poly isolation structure (figure 2; [0016-0017]).
Hu teaches, in claim 7, where the shallow ring region extends at least partially down to the buried layer, and where the first and second floating poly isolation structures both extend into the substrate past the buried layer (figure 2; [0014-0015]).
Hu teaches, in claim 8, wherein, when the central isolated region is set to a greater than zero potential with respect to the substrate, a voltage across peripheral ends of the buried layer to the substrate is less than a voltage across a central portion of the buried layer to the substrate (figure 2; [0024-0025], [0050]).
Hu teaches, in claim 9, where the shallow ring region of the second conductivity type and underlying portion of the substrate of the first conductivity type form a punch-through structure is configured to pull-up a potential of the first floating poly isolation structure when the central isolated region is set to the greater than zero potential with respect to the substrate (figure 2; [0024-0025], [0050]).
Hu teaches, in claim 10, an integrated circuit device, comprising:
a substrate (102); (figure 2; [0013])
an n-type buried layer (104) located in the substrate (102);
an isolated n-type region (120) located over the n-type buried layer (104), the isolated n-type region (120) and n-type buried layer (104) being vertically aligned;
a first floating poly isolation trench (126) concentrically disposed in the substrate (102) to surround the isolated n-type region (120);
a shallow n-type well region (122) at least partially disposed in the substrate (102) to surround the first floating poly isolation trench (126);
a second floating poly isolation trench (136) concentrically disposed in the substrate (102) to surround the shallow n-type well region (122); and
a first conductive interconnect structure (162) connected to electrically short the isolated n-type region (120) to the shallow n-type well region (122); and
wherein the first floating poly isolation trench (126) is electrically connected to the second floating poly isolation trench (136) (figure 2; [0016-0017]).
Hu teaches, in claim 11, wherein the first floating poly isolation trench is electrically connected to the second floating poly isolation trench by a metal interconnect structure formed over the substrate to electrically connect the first floating poly isolation trench to the second floating poly isolation trench (figure 2; [0016-0017]).
Hu teaches, in claim 12, wherein the first floating poly isolation trench is electrically connected to the second floating poly isolation trench by a polysilicon interconnect structure formed in the substrate to electrically connect the first floating poly isolation trench to the second floating poly isolation trench (figure 2; [0016-0017]).
Response to Arguments
Applicant’s arguments, see Remarks, filed 6/17/26, with respect to the rejection(s) of claim(s) 1-12 under 35 U.S.C. 102(a)(1) Nakamura (US PGPub 2008/0128828, hereinafter referred to as “Nakamura”) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Hu et al. (US PGPub 2020/0212229, hereinafter referred to as “Hu”).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 August 26, 2026
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