DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner proposes: SEMICONDUCTOR MEMORY DEVICE WITH DUMMY VIAS ABOVE THE CELL REGION
Paragraph 2 of the specification is duplicative: “Embodiments relate to a semiconductor memory device and an electronic system including the same and an electronic system including the same.”
Claim Interpretation
The claims recite “dummy vias” and “dummy metal patterns”. The examiner understands the claims to use the adjective “dummy” in the common way in which it is used in semiconductor structures, that is, an element that has the same structure but does not perform the expected function; so in this case, vias and metal patterns that do not pass current.
The examiner understands “landed on” to mean “set in physical connection with”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. All the independent claims, and various other claims, refer to a first or second “blocking layer”. The specification does not explain the blocking layer – what its function is, or properties it must have to serve that function. The existence of the blocking layer is merely alluded to. The term “blocking layer” has a standard meaning in the art of non-volatile memory devices: it is the charge blocking layer, the layer that forms the layer stack in the memory cell (the blocking layer, the storage layer, and the tunneling layer). The application refers to a “blocking insulating layer 132c” ([0064]), and as this has a different name, clearly this is a different kind of layer. A search of the art has not revealed that this has a different art-determined meaning. The applicant has not defined or explained what this layer is. Thus the scope of the claims can not be determined.
The remaining claims are rejected based on their dependencies.
For present purposes the examiner will interpret the blocking layers to be insulating layers.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, US 2017/0117290 A1, in view of Lim, US 2021/0296324 A1.
Claim 1: Lee discloses
a substrate (110) including a cell array region (CR) and an extension region (region with PL1-PL4);
a mold structure including a plurality of gate electrodes (G1 etc.) sequentially stacked on the cell array region and the extension region of the substrate in a stair shape, and a plurality of mold insulating layers (125) stacked alternately with the plurality of gate electrodes;
a plurality of channel structures (PL, [0052]) on the cell array region of the substrate, the plurality of channel structures intersecting the plurality of gate electrodes and passing through the mold structure (FIG. 3B).
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Lee does not disclose the claimed cell contacts, but these were common in the art. See Lim, FIG. 1A, cell contacts 184 connected to the gate electrodes 180. It would have been obvious and common to have such structures to control the gate layers, including in the structure of Lee.
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Lee further discloses a first interlayer insulating layer (on top of G6) on the mold structure and covering the plurality of channel structures and the plurality of cell contacts;
a plurality of first metal patterns (128) respectively connected to the plurality of channel structures, an upper surface of the plurality of first metal patterns being coplanar with an upper surface of the first interlayer insulating layer;
Lim discloses metal patterns 202 and 212 to connect to the cell contacts. These would be at the same level as the contact structures for the channel and other structures. Thus in Lee in view of Lim there would be a plurality of second metal patterns among these layers that respectively connected to the plurality of cell contacts. Because there is a contact in each layer for all the structures, there will be a second metal pattern in a layer of Lee where an upper surface of the plurality of second metal patterns being coplanar with the upper surface of the plurality of first metal patterns;
a first blocking layer (160 containing 152) extending along the upper surface of the first interlayer insulating layer, the upper surface of the plurality of first metal patterns, and the upper surface of the plurality of second metal patterns;
and a plurality of first dummy vias (152Da) passing through the first blocking layer (FIG. 6B).
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Claim 2: at least a portion of the plurality of first dummy vias is in the first interlayer insulating layer (FIG. 6B).
Claim 3: a second interlayer insulating layer (160 above 152) on the first blocking layer, wherein at least a portion of the plurality of first dummy vias is in the second interlayer insulating layer (SBLD).
Claim 5: an upper surface of the plurality of first dummy vias (top of SBLD) is coplanar with an upper surface of the plurality of third metal patterns (top of SBL).
Claim 6: an upper surface of the plurality of first dummy vias (152D) is coplanar with an upper surface of the plurality of vias (152).
Claim 7: Lee discloses a plurality of first dummy metal patterns (SBLD) on the plurality of first dummy vias (152D) and in the second interlayer insulating layer, wherein an upper surface of the plurality of first dummy metal patterns is coplanar with an upper surface of the plurality of third metal patterns.
Claim 9: at least a portion of the plurality of first dummy vias is between the plurality of first metal patterns or between the plurality of second metal patterns. As seen in FIG. 1, the device consists of multiple blocks, and thus the first dummy vias are between metal patterns of two different blocks.
Claim 10: the plurality of first dummy vias are on the extension region of the substrate and not on the cell array region of the substrate. See FIGS. 5B and 6B; the dummy regions with the dummy vias are over the stairstep regions of the extension region.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lim and Youn, US 2008/0277720 A1. Lee does not disclose the overall device. However, the claimed structure was common in the art. See Youn, FIG. 19, which discloses
a main board ([0071]);
a semiconductor memory device (320) on the main board;
and a controller (310) electrically connected to the semiconductor memory device on the main board.
It would have been obvious to use this arrangement as a very common way to mount the semiconductor memory for use.
Lee discloses that the semiconductor memory device includes:
a substrate (110) including a cell array region (CR) and an extension region (region with PL1-PL4);
a mold structure including a plurality of gate electrodes (G1 etc.) sequentially stacked on the cell array region and the extension region of the substrate in a stair shape, and a plurality of mold insulating layers (125) stacked alternately with the plurality of gate electrodes;
a plurality of channel structures (PL, [0052]) on the cell array region of the substrate, and intersecting the plurality of gate electrodes and passing through the mold structure (FIG. 3B);
Lee does not disclose the claimed cell contacts, but these were common in the art. See Lim, FIG. 1A, cell contacts 184 connected to the gate electrodes 180. It would have been obvious and common to have such structures to control the gate layers, including in the structure of Lee.
Lee further discloses a first interlayer insulating layer (on top of G6) on the mold structure and covering the plurality of channel structures and the plurality of cell contacts;
a plurality of first metal patterns (128) respectively connected to the plurality of channel structures, an upper surface of the plurality of first metal patterns being coplanar with an upper surface of the first interlayer insulating layer;
Lim discloses metal patterns 202 and 212 to connect to the cell contacts. These would be at the same level as the contact structures for the channel and other structures. Thus in Lee in view of Lim there would be a plurality of second metal patterns among these layers that respectively connected to the plurality of cell contacts. Because there is a contact in each layer for all the structures, there will be a second metal pattern in a layer of Lee where an upper surface of the plurality of second metal patterns being coplanar with the upper surface of the plurality of first metal patterns;
a first blocking layer (160 containing 152) extending along the upper surface of the first interlayer insulating layer, the upper surface of the plurality of first metal patterns, and the upper surface of the plurality of second metal patterns;
and a plurality of first dummy vias (152D) passing through the first blocking layer (FIG. 5B).
Potentially Allowable Subject Matter
If the 112 rejection is resolved, Claims 4, 8, and 11-19 are potentially allowable, as the examiner did not find this subject matter in the present prior art search as conducted.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is listed in the attached Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897