DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The amendments to the title and the specification overcome the previous objections.
The applicant’s explanation of the meaning of “blocking layer” on the record overcomes the 112 rejection.
The applicant argues on pages 5 and 6 that “with regard to FIG. 6B of Lee, the inter metal dielectric (IMD) 160 cannot simultaneously function as both the claimed ‘first blocking layer’ and ‘second interlayer insulating layer.’ For example, Lee states in Paragraphs [0109] and [0110] that a ‘dummy pattern, referred to hereinafter as a ‘dummy connection line SBLD’ may be provided in the IMD 160’ and that a ‘dummy line pattern LD may be provided under the dummy connection line SBLD in the IMD 160.’ Lee further states that ‘the dummy connection line SBLD and/or the dummy via plug 152Da may constitute metallization embedded in the IMD 160.’ Indeed, Lee teaches that the dummy structure (e.g., SBLD and 152Da) are embedded in IMD 160. Further, Lee does not teach that IMD 160 would be made of different materials (e.g., a first region of IMD 160 being made of a first material while a second region of IMD 160 being made of a second material). Accordingly, the cited art does not teach the above-referenced features of claims 1 and 20, namely, ‘a second interlayer insulating layer on the first blocking layer, the second interlayer insulating layer including a different material than the first blocking layer’ and ‘wherein at least a portion of the plurality of first dummy vias is in the second interlayer insulating layer.’”
Those in the art would recognize that a structure such as 160 would be formed by the application of several different layers, as is very common in formation of such structures. Furthermore, see the new rejections below.
Claim Interpretation
The claims recite “dummy vias” and “dummy metal patterns”. The examiner understands the claims to use the adjective “dummy” in the common way in which it is used in semiconductor structures, that is, an element that has the same structure but does not perform the expected function; in this case, vias and metal patterns that do not pass current.
The examiner understands “landed on” to mean “set in physical connection with”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, US 2017/0117290 A1, in view of Lim, US 2021/0296324 A1, and Wang, US 2022/0366985 A1.
Claim 1: Lee discloses
a substrate (110) including a cell array region (CR) and an extension region (region with PL1-PL4);
a mold structure including a plurality of gate electrodes (G1 etc.) sequentially stacked on the cell array region and the extension region of the substrate in a stair shape, and a plurality of mold insulating layers (125) stacked alternately with the plurality of gate electrodes;
a plurality of channel structures (PL, [0052]) on the cell array region of the substrate, the plurality of channel structures intersecting the plurality of gate electrodes and passing through the mold structure (FIG. 3B).
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Lee does not disclose the claimed cell contacts, but these were common in the art. See Lim, FIG. 1A, cell contacts 184 connected to the gate electrodes 180. It would have been obvious and common to have such structures to control the gate layers, including in the structure of Lee.
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Lee further discloses a first interlayer insulating layer (on top of G6) on the mold structure and covering the plurality of channel structures and the plurality of cell contacts;
a plurality of first metal patterns (128) respectively connected to the plurality of channel structures, an upper surface of the plurality of first metal patterns being coplanar with an upper surface of the first interlayer insulating layer;
Lim discloses metal patterns 202 and 212 to connect to the cell contacts. These would be at the same level as the contact structures for the channel and other structures. Thus in Lee in view of Lim there would be a plurality of second metal patterns among these layers that respectively connected to the plurality of cell contacts. Because there is a contact in each layer for all the structures, there will be a second metal pattern in a layer of Lee where an upper surface of the plurality of second metal patterns being coplanar with the upper surface of the plurality of first metal patterns;
a first blocking layer (160 containing 152) extending along the upper surface of the first interlayer insulating layer, the upper surface of the plurality of first metal patterns, and the upper surface of the plurality of second metal patterns;
and a plurality of first dummy vias (152Da) passing through the first blocking layer (FIG. 6B).
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Claim 1 also recites a second interlayer insulating layer on the first blocking layer, the second interlayer insulating layer including a different material than the first blocking layer; wherein at least a portion of the plurality of first dummy vias is in the second interlayer insulating layer. It was known in the art to have various layers of different materials above the memory stack. For example, see Wang, which discloses layers 764, 766, and 768 above the memory stack; “the fourth dielectric layer 764 includes any suitable material that is different from the third dielectric layer 766 and can be removed selectively with respect to the third dielectric layer 766” [0098]; “the etch-stop layer 768 includes any suitable material that is different from the third dielectric layer 766 such that the etch-stop layer 768 can be removed selectively with respect to the third dielectric layer 766.” [0101]. It would have been obvious to have used such an arrangement in order to have reduced to dimensions of the bit line contacts to reduce potential undesirable contacts ([0004], [0018], [0062]).
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In Lee in view of Wang, the 764/766 dielectric layers can be considered the blocking/interlayer insulating layer pair, or the 766/768 layer pair can be considered the blocking/interlayer insulating layer pair. Comparing FIG. 10B of Lee, which shows that dummy vias penetrate to the level of the channel plugs 128, with FIG. 8 of Wang, which shows the channel plugs 658 below all of the layers 764/766/768, it is clear that the dummy plug will pass through most or all of these layers.
Claim 2: at least a portion of the plurality of first dummy vias is in the first interlayer insulating layer (FIG. 6B).
Claim 3 recites that an upper surface of the plurality of first dummy vias is coplanar with an upper surface of the second interlayer insulating layer. This is disclosed by Wang, FOG/ 8, where 878 can correspond to the dummy via of Lee. Furthermore, in structures such as Lee FIG. 5B, the different metal layers are usually formed each in a dielectric sublayer, and thus there will be interlayer insulating layer that is coplanar with the dummy via. This would not be a source of patentable distinction.
Claim 5: an upper surface of the plurality of first dummy vias (top of SBLD) is coplanar with an upper surface of the plurality of third metal patterns (top of SBL).
Claim 6: an upper surface of the plurality of first dummy vias (152D) is coplanar with an upper surface of the plurality of vias (152).
Claim 7: Lee discloses a plurality of first dummy metal patterns (SBLD) on the plurality of first dummy vias (152D) and in the second interlayer insulating layer, wherein an upper surface of the plurality of first dummy metal patterns is coplanar with an upper surface of the plurality of third metal patterns.
Claim 9: at least a portion of the plurality of first dummy vias is between the plurality of first metal patterns or between the plurality of second metal patterns. As seen in FIG. 1, the device consists of multiple blocks, and thus the first dummy vias are between metal patterns of two different blocks.
Claim 10: the plurality of first dummy vias are on the extension region of the substrate and not on the cell array region of the substrate. See FIGS. 5B and 6B; the dummy regions with the dummy vias are over the stairstep regions of the extension region.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lim, Wang, and Youn, US 2008/0277720 A1. Lee does not disclose the overall device. However, the claimed structure was common in the art. See Youn, FIG. 19, which discloses
a main board ([0071]);
a semiconductor memory device (320) on the main board;
and a controller (310) electrically connected to the semiconductor memory device on the main board.
It would have been obvious to use this arrangement as a very common way to mount the semiconductor memory for use.
Lee discloses that the semiconductor memory device includes:
a substrate (110) including a cell array region (CR) and an extension region (region with PL1-PL4);
a mold structure including a plurality of gate electrodes (G1 etc.) sequentially stacked on the cell array region and the extension region of the substrate in a stair shape, and a plurality of mold insulating layers (125) stacked alternately with the plurality of gate electrodes;
a plurality of channel structures (PL, [0052]) on the cell array region of the substrate, and intersecting the plurality of gate electrodes and passing through the mold structure (FIG. 3B);
Lee does not disclose the claimed cell contacts, but these were common in the art. See Lim, FIG. 1A, cell contacts 184 connected to the gate electrodes 180. It would have been obvious and common to have such structures to control the gate layers, including in the structure of Lee.
Lee further discloses a first interlayer insulating layer (on top of G6) on the mold structure and covering the plurality of channel structures and the plurality of cell contacts;
a plurality of first metal patterns (128) respectively connected to the plurality of channel structures, an upper surface of the plurality of first metal patterns being coplanar with an upper surface of the first interlayer insulating layer;
Lim discloses metal patterns 202 and 212 to connect to the cell contacts. These would be at the same level as the contact structures for the channel and other structures. Thus in Lee in view of Lim there would be a plurality of second metal patterns among these layers that respectively connected to the plurality of cell contacts. Because there is a contact in each layer for all the structures, there will be a second metal pattern in a layer of Lee where an upper surface of the plurality of second metal patterns being coplanar with the upper surface of the plurality of first metal patterns;
a first blocking layer (160 containing 152) extending along the upper surface of the first interlayer insulating layer, the upper surface of the plurality of first metal patterns, and the upper surface of the plurality of second metal patterns;
and a plurality of first dummy vias (152D) passing through the first blocking layer (FIG. 5B).
Claim 20 also recites that second interlayer insulating layer on the first blocking layer, the second interlayer insulating layer including a different material than the first blocking layer; wherein at least a portion of the plurality of first dummy vias is in the second interlayer insulating layer. It was known in the art to have various layers of different materials above the memory stack. For example, see Wang, which discloses layers 764, 766, and 768 above the memory stack; “the fourth dielectric layer 764 includes any suitable material that is different from the third dielectric layer 766 and can be removed selectively with respect to the third dielectric layer 766” [0098]; “the etch-stop layer 768 includes any suitable material that is different from the third dielectric layer 766 such that the etch-stop layer 768 can be removed selectively with respect to the third dielectric layer 766.” [0101]. It would have been obvious to have used such an arrangement in order to have reduced to dimensions of the bit line contacts to reduce potential undesirable contacts ([0004], [0018], [0062]).
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In Lee in view of Wang, the 764/766 dielectric layers can be considered the blocking/interlayer insulating layer pair, or the 766/768 layer pair can be considered the blocking/interlayer insulating layer pair. Comparing FIG. 10B of Lee, which shows that dummy vias penetrate to the level of the channel plugs 128, with FIG. 8 of Wang, which shows the channel plugs 658 below all of the layers 764/766/768, it is clear that the dummy plug will pass through most or all of these layers.
Allowable Subject Matter
Claims 4, 8, and 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 14-19 are allowed. The examiner did not find the claimed metal patterns and second dummy vias in the arrangement claimed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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