DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant’s arguments, see Claim Rejections – 35 USC § 103, filed 4/02/2026, with respect to the rejection(s) of claim(s) 1 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung) in view of Jang Sung Uk et al. (Pub No. KR 20200086606 A) (hereinafter, Jang) in view of Kim, Dongwoo et al. (Pub No. US 20220069134 A1) (hereinafter, Kim).
6. Applicant’s arguments, see Claim Rejections – 35 USC § 103, filed 4/02/2026, with respect to the rejection(s) of claim(s) 15 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung) in view of Kim, Dongwoo et al. (Pub No. US 20220069134 A1) (hereinafter, Kim).
7. Applicant’s arguments, see Claim Rejections – 35 USC § 103, filed 4/02/2026, with respect to the rejection(s) of claim(s) 19 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung) in view of More, Shahaji B. et al. (Pub No. US 20220037520 A1) (hereinafter, More 2) in view of Chu, Feng-Ching et al. (Pub No. US 20220069135 A1) (hereinafter, Chu).
Re claims 1 and 19, Jung teaches the second semiconductor layer (234) which comprises the third germanium concentration which is less than the second germanium concentration (Ge concentration of 234 is less than 244 per ¶[0135]) of the third semiconductor layer (244). Therefore, the features disclosed in ¶[0135] of Jung anticipate the amended limitations.
Further, re claims 1, 15 and 19, the arguments made by the applicant regarding criticality are valid, however, the prior art render obvious the limitations, “wherein the third semiconductor layer comprises a second concentration of germanium (Ge) that is smaller than the first concentration of germanium (Ge).”
8. Regarding claim 8, applicant's arguments filed 4/02/2026 have been fully considered but they are not persuasive. Applicant argues the element 820 of Fig. 34 of Jung does not anticipate a second semiconductor layer because there is no first semiconductor layer which contacts the gate structures, however, according to the embodiments of the instant application, the first semiconductor layers do not contact gate structures, therefore element 820 may be considered a second semiconductor layer according to the embodiment of Jung.
9. Regarding claim 17, the “second semiconductor layer” has been changed to the “first semiconductor layer” to accurately reflect the claim language.
10. Applicant’s arguments, see Specification Objection, filed 4/02/2026, with respect to the objection of the Specification have been fully considered and are persuasive. The objection of the Specification has been withdrawn.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 103
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. Claims 1, 3-5, 7-8 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung) in view of Jang Sung Uk et al. (Pub No. KR 20200086606 A) (hereinafter, Jang), and further in view of Kim, Dongwoo et al. (Pub No. US 20220069134 A1) (hereinafter, Kim).
Re Claim 1, (Currently Amended) Jung teaches a semiconductor device, comprising:
a substrate (Substrate/Active Pattern; 100/105; Fig 29; ¶[0025]) comprising an active region (Active Pattern; 105; Fig 29; ¶[0025]) extending in a first direction (1st Direction; Fig 31);
a gate structure (Gate structure; 330; Fig 29; ¶[0025]) intersecting the active region on the substrate and extending in a second direction (2nd Direction; Fig 29), wherein the active region comprises a recessed region (Recess between gate structures 330; Fig 29) at at least one side of the gate structure;
a plurality of channel layers (Semiconductor pattern; 124; Fig 29; ¶[0025]) on the active region, spaced apart from each other in a third direction (3rd Direction; Fig 29) that is substantially perpendicular to an upper surface (Upper surface of 100; Fig 29) of the substrate, and at least partially surrounded by the gate structure; and
a source/drain region (Source/Drain layer; 250; Fig 29; ¶[0025]) in the recessed region of the active region and connected to the plurality of channel layers,
wherein the source/drain region comprises:
a plurality of first semiconductor layers (Sixth epitaxial layers; 228; Fig 29; ¶[0133]) on the active region and on side surfaces (Side surfaces of 124; Fig 29) of the plurality of channel layers that are exposed through the recessed region,
the plurality of first semiconductor layers being spaced apart from each other;
a second semiconductor layer (Seventh epitaxial layer; 234; Fig 29; ¶[0133]) being provided on at least one of the plurality of first semiconductor layers
a third semiconductor layer (Eighth epitaxial layer; 244; Fig 29; ¶[0133]) on the second semiconductor layer,
wherein the plurality of first semiconductor layers comprise a first concentration of germanium (Ge) (Comprises a concentration of germanium of sixth epitaxial layer 228; ¶[0135]).
wherein the third semiconductor layer comprises a second concentration of germanium (Concentration of germanium of eight epitaxial layer 244; ¶[0135]).
wherein the second semiconductor layer (Seventh epitaxial layer; 234; Fig 29; ¶[0133]) comprises a third concentration of germanium (Ge) (Concentration of germanium of seventh epitaxial layer 234; ¶[0135]) that is smaller than the second concentration of germanium (Ge).
Jung, Fig 29: FinFET cross-section of source/drain epitaxial layers
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However, Jung does not teach a second semiconductor layer extending continuously while being provided on at least one of the plurality of first semiconductor layers and side surfaces of the gate structure; and
wherein the third semiconductor layer comprises a second concentration of germanium (Ge) that is smaller than the first concentration of germanium (Ge).
In the same field of endeavor, Jang teaches a second semiconductor layer (First epitaxial layer; 152c; Fig 9; ¶[0082]) extending continuously while being provided on at least one of the plurality of first semiconductor layers (Third epitaxial layers; 151; Fig 9; ¶[0083]) and side surfaces of the gate structure (Gate structure (includes gate dielectric/gate electrode/spacer layers); 162/165/164; Fig 9; ¶[0019]).
Jang, Fig 9: FinFET cross-section of source/drain epitaxial layers
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a second semiconductor layer extending continuously while being provided on at least one of the plurality of first semiconductor layers and side surfaces of the gate structure, as taught by Jang, with the semiconductor device as taught by Jung. One would have been motivated to do this with a reasonable expectation of success because by surrounding the channel and gate electrodes with an epitaxial layer, the device geometry allows for superior electrostatic control of the channel by the gate voltage. Further, a continuous epitaxial layer provides a uniform contact area for charge carriers flowing through the channel.
However, Jung in view of Jang does not teach wherein the third semiconductor layer comprises a second concentration of germanium (Ge) that is smaller than the first concentration of germanium (Ge).
In the same field of endeavor, Kim teaches wherein the third semiconductor layer (Third epitaxial layer; 153; Fig 2B; ¶[0096]) comprises a second concentration of germanium (Ge) (May be pure Silicon, i.e. no Ge content; ¶[0096]) that is smaller than the first concentration of germanium (Ge) (Germanium concentration of first epitaxial layer 151; ¶[0096]; Note: The germanium concentration of first epitaxial layer151 is not disclosed, however it is an SiGe layer, which contains germanium, which may be higher than the third epitaxial layer 153 which may contain zero Ge content).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the third semiconductor layer comprises a second concentration of germanium (Ge) that is smaller than the first concentration of germanium (Ge), as taught by Kim, with the semiconductor device as taught by Jung in view of Jang. One would have been motivated to do this with a reasonable expectation of success because a third epitaxial layer with lower Ge content than the first epitaxial layer would be more cost effective and allows for better thermal conductivity within the central portions of the source/drain regions, whereas the first and second epitaxial layers closer to the channels require more compressive strain, i.e. higher Ge content, for better carrier mobility proximate to the channels.
Re Claim 3, (Original) Jung in view of Jang does not teach a semiconductor device of claim 1, wherein the first concentration of germanium (Ge) is in a range of about 1% to about 15%.
Jung fails to disclose the exact first concentration of germanium as claimed.
Nevertheless, as depicted in ¶[0135] such features (concentration of germanium of sixth epitaxial layer 228) must possess particular dimension. The choice of the first concentration of germanium, respectively, is matter of engineering design choice; therefore, obvious expedient.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Jung's first concentration of germanium because this would be the best engineering design choice.
In addition, the selection of the particular ranges as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04
Re Claim 4, (Currently Amended) Jung teaches the semiconductor device of claim 1, wherein the plurality of first semiconductor layers (Sixth epitaxial layers; 228; Fig 29; ¶[0133]) have a substantially conformal uniform thickness (Equal thicknesses on each channel layer; ¶[0134]).
Re Claim 5, (Original) Jung teaches the semiconductor device of claim 1, wherein the plurality of first semiconductor layers (First and fifth epitaxial layers (second embodiment); 230/237; Fig 26; ¶[0123]) have a first thickness (Thickness of 230 ends of channels 124; Fig 26) on the side surfaces of the plurality of channel layers (Semiconductor patterns; 124; Fig 26; ¶[0123]) and a second thickness (Thickness of 237 on active pattern 105; Fig 26) larger than the first thickness on the active region.
Jung, Fig 26: Second embodiment of FinFET device with first semiconductor layers of varying thicknesses
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Re Claim 7, (Original) Jung teaches the semiconductor device of claim 1, wherein, in a cross section (Fig 26) along the first direction (1st Direction; Fig 26), at least some ends of the plurality of first semiconductor layers (First and fifth epitaxial layers; 230/237; Fig 26; ¶[0123]) are shifted from each other such that, in the third direction (3rd Direction; Fig 26), the at least some ends (Inner ends of 230/237 are not linear; Fig 26) are disposed in a non- straight line.
Re Claim 8, (Original) Jung teaches the semiconductor device of claim 1, wherein the second semiconductor layer (Tenth epitaxial layer (third embodiment); 820; Fig 34; ¶[0163]) contacts the gate structure (First gate structure; 632; Fig 34; ¶[0163]) between the plurality of channel layers (First semiconductor patterns; 426; Fig 34; ¶[0163]).
Jung, Fig 34: Third embodiment illustrating a semiconductor layer contacting a gate structure
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Re Claim 11, (Original) Jung teaches the semiconductor device of claim 1, wherein the plurality of first semiconductor layers (Sixth epitaxial layers; 228; Fig 29; ¶[0133]), the second semiconductor layer (Seventh epitaxial layer; 234; Fig 29; ¶[0133]), and the third semiconductor layer (Eighth epitaxial layer; 244; Fig 29; ¶[0133]) further comprise impurities comprising at least one of boron (B), gallium (Ga), and indium (In) (Comprises p-type impurity dopants, which boron, gallium and indium are commonly used as p-type impurities; ¶[0135]).
Re Claim 12, (Original) Jung teaches the semiconductor device of claim 1,
wherein the source/drain region (Source/Drain layer; 250; Fig 29; ¶[0025]) further comprises a fourth semiconductor layer (Ninth epitaxial layer; 248; Fig 29; ¶[0133]) filling the recessed region (Recess between gate structures 330; Fig 29) on the third semiconductor layer (Eighth epitaxial layer; 244; Fig 29; ¶[0133]).
13. Claims 6, 10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung) in view of Jang Sung Uk et al. (Pub No. KR 20200086606 A) (hereinafter, Jang) in view of Kim, Dongwoo et al. (Pub No. US 20220069134 A1) (hereinafter, Kim) as applied to claim 1, and further in view of More, Shahaji B. (Pub No. US 20230411456 A1) (hereinafter, More).
Re Claim 6, (Original) Jung in view of Jang and Kim does not teach the semiconductor device of claim 1, wherein the plurality of first semiconductor layers have a thickness of about 0.1 nm to about 3 nm.
In the same field of endeavor, More teaches the semiconductor device of claim 1, wherein the plurality of first semiconductor layers (Seed layer convex protrusions; 910; Fig 9B; ¶¶[0127-0128]) have a thickness of about 0.1 nm to about 3 nm (Per ¶[0128] convex protrusions of seed layer 905 may be 1 nm to 5 nm thick).
More, Fig 9B: FinFET with epitaxial layers of 1 nm to 5 nm thick
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the plurality of first semiconductor layers having a thickness of about 0.1 nm to about 3 nm, as taught by More, with the semiconductor device as taught by Jung in view of Jang and Kim. One would have been motivated to do this with a reasonable expectation of success because if the semiconductor layers (seed layer) is too thin, the seed layer may provide insufficient coverage as a capping layer for the channels. Further, if the width of the seed layer is too thick, the seed layer merging issue may occur, wherein unintended merging of the epitaxial material may grow on adjacent fins. Finally, if the seed layer is too thick an available volume for additional epitaxial layers within the source/drain recess may be reduced (More, ¶[0128]).
Re Claim 10, (Original) Jung in view of Jang and Kim does not teach the semiconductor device of claim 1, wherein the second semiconductor layer comprises a plurality of regions protruding convexly toward the side surfaces of the gate structure.
In the same field of endeavor, More teaches the semiconductor device of claim 1, wherein the second semiconductor layer (Epitaxial layer; 915; Fig 11; ¶[0131]) comprises a plurality of regions (Regions protruding convexly towards gate structures 240; ¶[0046]) protruding convexly toward the side surfaces of the gate structure (Gate structures; 240; Fig 11; ¶[0046]).
More, Fig 11: GAA Device with epitaxial layers protruding convexly towards gate structures
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the second semiconductor layer comprising a plurality of regions protruding convexly toward the side surfaces of the gate structure, as taught by More, with the semiconductor device as taught by Jung in view of Jang and Kim. One would have been motivated to do this with a reasonable expectation of success because the electric field is strongest in the region near the gate and by positioning the source and drain close to the gate, the gate voltage can efficiently and quickly control the resistance of the channel, allowing the device to act as an effective switch or amplifier.
Re Claim 14, (Original) Jung in view of Jang and Kim does not teach the semiconductor device of claim 12, wherein the source/drain region further comprises a fifth semiconductor layer on an upper surface of the fourth semiconductor layer and comprising a fifth concentration of germanium (Ge) that is smaller than the second concentration of germanium (Ge).
In the same field of endeavor, More teaches the semiconductor device of claim 12, wherein the source/drain region (Source/drain regions; 225; Fig 11; ¶[0043]) further comprises a fifth semiconductor layer (Capping layer; 235; Fig 11; ¶[0142]) on an upper surface of the fourth semiconductor layer (Epitaxial layer; 920; Fig 11; ¶[0142]) and comprising a fifth concentration of germanium (Ge) (Ge content of 15% to 25%; ¶[0142]) that is smaller than the second concentration of germanium (Ge) (Ge content of 35% to 55%; ¶[0136]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the source/drain region further comprising a fifth semiconductor layer on an upper surface of the fourth semiconductor layer and comprising a fifth concentration of germanium (Ge) that is smaller than the second concentration of germanium (Ge), as taught by More, with the semiconductor device as taught by Jung in view of Jang and Kim. One would have been motivated to do this with a reasonable expectation of success to reduce dopant diffusion and to protect the source/drain regions in semiconductor processing operations (More, ¶[0045]).
14. Claims 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung) in view of Jang Sung Uk et al. (Pub No. KR 20200086606 A) (hereinafter, Jang) in view of Kim, Dongwoo et al. (Pub No. US 20220069134 A1) (hereinafter, Kim) as applied to claim 1, and further in view of More, Shahaji B. et al. (Pub No. US 20220037520 A1) (hereinafter, More 2).
Re Claim 9, (Original) Jung in view of Jang and Kim does not teach the semiconductor device of claim 1, wherein the second semiconductor layer comprises a silicon (Si) layer.
In the same field of endeavor, More 2 teaches the semiconductor device of claim 1, wherein the second semiconductor layer (Second epitaxial layer; 50-2; Fig 17; ¶[0069]) comprises a silicon (Si) layer (Epitaxial layer 50-2 may comprise of a Si layer or SiGe with Ge at 0 atomic %; ¶[0069]).
More 2, Fig 17: FinFET device with first to fifth epitaxial layers in source/drain region
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the second semiconductor layer comprising a silicon layer, as taught by More 2, with the semiconductor device as taught by Jung in view of Jang and Kim. One would have been motivated to do this with a reasonable expectation of success because a pure Si source/drain region provides better thermal stability during subsequent high-temperature annealing steps in the manufacturing process compared to layers with higher Ge concentrations, which might relax or intermix.
Re Claim 13, (Original) Jung in view of Jang and Kim does not teach the semiconductor device of claim 12, wherein a fourth concentration of germanium (Ge) of the fourth semiconductor layer is greater than the second concentration of germanium (Ge).
In the same field of endeavor, More 2 teaches the semiconductor device of claim 12, wherein a fourth concentration of germanium (Ge) (Concentration of Ge of 50-4, i.e. 30-60 atomic %; Fig 17; ¶[0074]) of the fourth semiconductor layer (Fourth epitaxial layer; 50-4; Fig 17; ¶[0074]) is greater than the second concentration of germanium (Ge) (Concentration of Ge of 50-3, i.e. 20-30 atomic %; Fig 17; ¶[0072]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a fourth concentration of germanium (Ge) of the fourth semiconductor layer is greater than the second concentration of germanium (Ge), as taught by More 2, with the semiconductor device as taught by Jung in view of Jang. One would have been motivated to do this with a reasonable expectation of success because higher Ge content creates beneficial tensile strain on the surrounding epitaxial layers, such as the third epitaxial layer with the second concentration, significantly boosting hole mobility and drive current.
15. Claims 15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung), and further in view of Kim, Dongwoo et al. (Pub No. US 20220069134 A1) (hereinafter, Kim).
Re Claim 15, (Original) Jung teaches a semiconductor device, comprising:
a substrate (Substrate/Active Pattern; 100/105; Fig 29; ¶[0025]) comprising an active region (Active Pattern; 105; Fig 29; ¶[0025]) extending in a first direction (1st Direction; Fig 31);
a gate structure (Gate structure; 330; Fig 29; ¶[0025]) intersecting the active region on the substrate and extending in a second direction (2nd Direction; Fig 29), wherein the active region comprises a recessed region (Recess between gate structures 330; Fig 29) at at least one side of the gate structure;
a plurality of channel layers (Semiconductor pattern; 124; Fig 29; ¶[0025]) on the active region, spaced apart from each other in a third direction (3rd Direction; Fig 29) that is substantially perpendicular to an upper surface (Upper surface of 100; Fig 29) of the substrate, and at least partially surrounded by the gate structure; and
a source/drain region (Source/Drain layer; 250; Fig 29; ¶[0025]) in the recessed region of the active region and connected to the plurality of channel layers,
wherein the source/drain region comprises:a plurality of first semiconductor layers (Sixth epitaxial layers; 228; Fig 29; ¶[0133]) on the active region and on side surfaces (Side surfaces of 124; Fig 29) of the plurality of channel layers that are exposed through the recessed region;
a second semiconductor layer (Seventh epitaxial layer; 234; Fig 29; ¶[0133]) on the first semiconductor layer; and
a third semiconductor layer (Eighth epitaxial layer; 244; Fig 29; ¶[0133]) on the second semiconductor layer,
wherein the first semiconductor layer comprises a first concentration of germanium (Ge) (Comprises a concentration of germanium of sixth epitaxial layer 228; ¶[0135]),
wherein the third semiconductor layer comprises a second concentration of germanium (Ge) (Eighth epitaxial layer 244 comprises a concentration of germanium greater than the sixth and seventh epitaxial layers 228/234; ¶[0135]), and
wherein the second semiconductor layer comprises a third concentration of germanium (Ge) (Concentration of Ge of seventh epitaxial layer 234 is smaller than concentration of Ge of eighth epitaxial layer 244; ¶[0135]) that is smaller than the second concentration of germanium (Ge).
However, Jung does not teach wherein the third semiconductor layer comprises a second concentration of germanium (Ge) that is smaller than the first concentration of germanium (Ge).
In the same field of endeavor, Kim teaches wherein the third semiconductor layer (Third epitaxial layer; 153; Fig 2B; ¶[0096]) comprises a second concentration of germanium (Ge) (May be pure Silicon, i.e. no Ge content; ¶[0096]) that is smaller than the first concentration of germanium (Ge) (Germanium concentration of first epitaxial layer 151; ¶[0096]; Note: The germanium concentration of first epitaxial layer151 is not disclosed, however it is an SiGe layer, which contains germanium, which may be higher than the third epitaxial layer 153 which may contain zero Ge content).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the third semiconductor layer comprises a second concentration of germanium (Ge) that is smaller than the first concentration of germanium (Ge), as taught by Kim, with the semiconductor device as taught by Jung. One would have been motivated to do this with a reasonable expectation of success because a third epitaxial layer with lower Ge content than the first epitaxial layer would be more cost effective and allows for better thermal conductivity within the central portions of the source/drain regions, whereas the first and second epitaxial layers closer to the channels require more compressive strain, i.e. higher Ge content, for better carrier mobility proximate to the channels.
Re Claim 18, (Original) Jung teaches the semiconductor device of claim 15, wherein the source/drain region (Source/Drain layer; 250; Fig 29; ¶[0025]) comprises a plurality of first semiconductor layers (Sixth epitaxial layers; 228; Fig 29; ¶[0133]), and
wherein the plurality of first semiconductor layers are spaced apart from each other on the active region (Active Pattern; 105; Fig 29; ¶[0025]) and the side surfaces (Side surfaces of 124; Fig 29) of the plurality of channel layers (Semiconductor pattern; 124; Fig 29; ¶[0025]).
16. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung) in view of Kim, Dongwoo et al. (Pub No. US 20220069134 A1) (hereinafter, Kim) as applied to claim 15, and further in view of More, Shahaji B. et al. (Pub No. US 20220037520 A1) (hereinafter, More 2).
Re Claim 16, (Original) Jung teaches the semiconductor device of claim 15, wherein the first semiconductor layer (Sixth epitaxial layers; 228; Fig 29; ¶[0133]) and the third semiconductor layer (Eighth epitaxial layer; 244; Fig 29; ¶[0133]) comprise silicon germanium (SiGe) layers (Epitaxial layers 228/244 comprise SiGe; ¶[0135]).
However, Jung in view of Kim does not teach wherein the second semiconductor layer comprises a silicon (Si) layer.
In the same field of endeavor, More 2 teaches wherein the second semiconductor layer (Second epitaxial layer; 50-2; Fig 17; ¶[0069]) comprises a silicon (Si) layer (Epitaxial layer 50-2 may comprise of a Si layer or SiGe with Ge at 0 atomic %; ¶[0069]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the second semiconductor layer comprising a silicon layer, as taught by More 2, with the semiconductor device as taught by Jung in view of Kim. One would have been motivated to do this with a reasonable expectation of success because a pure Si source/drain region provides better thermal stability during subsequent high-temperature annealing steps in the manufacturing process compared to layers with higher Ge concentrations, which might relax or intermix.
17. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung) in view of Kim, Dongwoo et al. (Pub No. US 20220069134 A1) (hereinafter, Kim) as applied to claim 15, and further in view of More, Shahaji B. (Pub No. US 20230411456 A1) (hereinafter, More).
Re Claim 17, (Original) Jung in view of Kim does not teach the semiconductor device of claim 15, wherein the first semiconductor layer comprises a plurality of regions protruding convexly toward the gate structure.
In the same field of endeavor, More teaches the semiconductor device of claim 15, wherein the first semiconductor layer (Epitaxial layer; 915; Fig 11; ¶[0131]) comprises a plurality of regions (Regions protruding convexly towards gate structures 240; ¶[0046]) protruding convexly toward the side surfaces of the gate structure (Gate structures; 240; Fig 11; ¶[0046]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the second semiconductor layer comprising a plurality of regions protruding convexly toward the side surfaces of the gate structure, as taught by More, with the semiconductor device as taught by Jung in view of Kim. One would have been motivated to do this with a reasonable expectation of success because the electric field is strongest in the region near the gate and by positioning the source and drain close to the gate, the gate voltage can efficiently and quickly control the resistance of the channel, allowing the device to act as an effective switch or amplifier.
18. Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung) in view of More, Shahaji B. et al. (Pub No. US 20220037520 A1) (hereinafter, More 2), and further in view of Chu, Feng-Ching et al. (Pub No. US 20220069135 A1) (hereinafter, Chu).
Re Claim 19, (Currently Amended) Jung teaches a semiconductor device, comprising:
a substrate (Substrate/Active Pattern; 100/105; Fig 29; ¶[0025]) comprising an active region (Active Pattern; 105; Fig 29; ¶[0025]) extending in a first direction (1st Direction; Fig 31);
a gate structure (Gate structure; 330; Fig 29; ¶[0025]) intersecting the active region on the substrate and extending in a second direction (2nd Direction; Fig 29), wherein the active region comprises a recessed region (Recess between gate structures 330; Fig 29) at at least one side of the gate structure;
a plurality of channel layers (Semiconductor pattern; 124; Fig 29; ¶[0025]) on the active region, spaced apart from each other in a third direction (3rd Direction; Fig 29) that is substantially perpendicular to an upper surface (Upper surface of 100; Fig 29) of the substrate, and at least partially surrounded by the gate structure; and
a source/drain region (Source/Drain layer; 250; Fig 29; ¶[0025]) in the recessed region of the active region and connected to the plurality of channel layers,
wherein the source/drain region comprises:a plurality of first semiconductor layers (Sixth epitaxial layers; 228; Fig 29; ¶[0133]) on the active region and on side surfaces (Side surfaces of 124; Fig 29) of the plurality of channel layers that are exposed through the recessed region, the plurality of first semiconductor layers being spaced apart from each other and comprising silicon germanium (SiGe) layers (Sixth epitaxial layers 228 comprise SiGe; ¶[0135]);
a second semiconductor layer (Seventh epitaxial layer; 234; Fig 29; ¶[0133]) on at least one of the plurality of first semiconductor layers; and
a third semiconductor layer (Eighth epitaxial layer; 244; Fig 29; ¶[0133]) on the second semiconductor layer, the third semiconductor layer comprising a silicon germanium (SiGe) layer (Eighth epitaxial layer 244 comprises SiGe; ¶[0135]).
wherein a germanium concentration of the second semiconductor layer is less than the germanium concentration of the third semiconductor layer.
However, Jung does not teach the second semiconductor layer comprising a silicon (Si) layer.
wherein a germanium concentration of the third semiconductor layer is less than a germanium concentration of at least one first semiconductor layer of the plurality of first semiconductor layers, and
In the same field of endeavor, More 2 teaches a second semiconductor layer (Second epitaxial layer; 50-2; Fig 17; ¶[0069]) comprising a silicon (Si) layer (Epitaxial layer 50-2 may comprise of a Si layer or SiGe with Ge at 0 atomic %; ¶[0069]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the second semiconductor layer comprising a silicon layer, as taught by More 2, with the semiconductor device as taught by Jung in view of Jang. One would have been motivated to do this with a reasonable expectation of success because a pure Si source/drain region provides better thermal stability during subsequent high-temperature annealing steps in the manufacturing process compared to layers with higher Ge concentrations, which might relax or intermix.
However, Jung in view of More 2 does not teach wherein a germanium concentration of the third semiconductor layer is less than a germanium concentration of at least one first semiconductor layer of the plurality of first semiconductor layers.
In the same field of endeavor, Chu teaches wherein a germanium concentration (Ge content of 240; Fig 16A) of the third semiconductor layer (Third epitaxial layer; 240; Fig 16A; ¶[0031]) is less than a germanium concentration (Ge content of 236; Fig 16A) of at least one first semiconductor layer (First epitaxial layers; 236; Fig 16A; ¶[0031]) of the plurality of first semiconductor layers (The plurality of first epitaxial layers along each channel structure 208; 236; Fig 16A; ¶[0031]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a germanium concentration of the third semiconductor layer is less than a germanium concentration of at least one first semiconductor layer of the plurality of first semiconductor layers, as taught by Chu, with the semiconductor device as taught by Jung in view of More 2. One would have been motivated to do this with a reasonable expectation of success because a third epitaxial layer with lower Ge content than the first epitaxial layer would be more cost effective and allows for better thermal conductivity within the central portions of the source/drain regions, whereas the first and second epitaxial layers closer to the channels require more compressive strain, i.e. higher Ge content, for better carrier mobility proximate to the channels.
Re Claim 20, (Original) Jung teaches the semiconductor device of claim 19, wherein the plurality of first semiconductor layers (First and fifth epitaxial layers (second embodiment); 230/237; Fig 26; ¶[0123]) have a first thickness (Thickness of 230 ends of channels 124; Fig 26) on the side surfaces of the plurality of channel layers (Semiconductor patterns; 124; Fig 26; ¶[0123]) and a second thickness (Thickness of 237 on active pattern 105; Fig 26) larger than the first thickness on the active region.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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