DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Domestic Benefit
No claim to an application for domestic benefit.
Foreign Priority
Receipt is acknowledged of certified copies of papers (i.e., application number 10-2022-0099975 filed in Korea on 08/10/2022) required by 37 CFR 1.55, electronically retrieved 09/10/2023.
Information Disclosure Statement
No information disclosure statement filed.
Claim Objections
Claim 20 objected to because of the following informalities: Independent Claim 20 starts with “The” instead of “A” -- Appropriate correction is required.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title or similar is suggested:
-- DISPLAY APPARATUS WITH CONNECTION ELECTRODE IN NON-LIGHT EMISSION AREA --.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7,10-11, 13-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0012031 A1 to Kim et al. (“Kim”).
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Regarding independent claim 1, Kim teaches in Figure 4 of a display apparatus (see title), comprising:
a substrate 110 (“substrate”; paragraph 027) having a light emission area 30 (“pixel region”; paragraph 0022), including a pixel 400 (“pixel structure”; paragraph 0027), and a non-light emission area 40/50/60 (“first peripheral region”/”bending region”/”second periphery region”; paragraph 0022) in a periphery of the light emission area 30;
a plurality of split lines 300/301/302 (“fan-out wiring”/“first fan-out wiring”/”second fan-out wiring”; paragraph 0027) spaced apart (see Figure 4) from each other in the non-light emission area 40/50/60, the split lines being configured to provide a signal for driving (see paragraph 0037: “The first fan-out wiring 301 may extend substantially along the first direction D1 in the first peripheral region 40 on the first gate insulation layer 150, and may electrically connected to the pixel structure 400 that is disposed in the pixel region 30”) the pixel 400;
a planarization layer 270 (“first planarization layer”) in the non-light emission area 40/50/60 and overlapping with a portion of each of the split lines 300/301/302; and
a connection electrode 330 (“connection electrode”; paragraph 0048) covering the planarization layer 270 in the non-light emission area 40/50/60 and connecting the split lines 300/301/302 to each other,
wherein the planarization layer 270 includes a central area (middle part of the line 300 of Figure 4; around 50) and an edge area (i.e., start of 40 and 60) in a periphery 40/60 of the central area 50, the central area having a different thickness from the edge area (see Examiner’s Annotated Figure 4 of Kim: there is a height difference between the middle longer black line and the shorter edge lines of 270).
Regarding claim 2, Kim teaches wherein a thickness of the central area of the planarization layer 270 is greater than a thickness of the edge area of the planarization layer (see Examiner’s Annotated Figure 4 of Kim: there is a height difference between the middle longer black line and the shorter edge lines of 270).
Regarding claim 3, Kim teaches wherein a width 50 of the central area of the planarization layer 270 is equal to or smaller (see Figure 4: 50 has a width that is smaller than the distance between 301 and 302) than a width of a space between the split lines 301 and 302.
Regarding claim 4, Kim teaches in Figure 4 wherein the connection electrode 330 extends upward from the edge area 40/60 to the central area (i.e., the connection portion of 330) of the planarization layer 270.
Regarding claim 5, Kim teaches in Figure 4 of a passivation layer 200/195 (“insulation layer structure”/“insulating interlayer”; paragraph 0042) covering a portion of each of the split lines 301/302 and disposed between the planarization layer 270 and the split lines 301/302,
wherein a width of the planarization layer 270 is equal to or smaller (i.e., 270 in 40/50/60 ends in the width/horizontal direction) than a width of the passivation layer 195 (whereas in paragraph 0042, 195 is in 40/50/60 AND in pixel region 30).
Regarding claim 7, Kim teaches wherein an upper surface of the planarization layer 270 meets a side surface of the planarization layer 270 at an obtuse angle (see Examiner’s Annotated Figure 4, directly below. Labeled in dark black is an obtuse angle).
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Regarding claim 10, Kim teaches in Figure 4 of a coating layer 275 (“second planarization layer”; paragraph 0027; 275 coats 270) covering the planarization layer 270 in the non-light emission area 40/50/60; and
an encapsulation layer 310 (“pixel defining layer”; paragraph 0027; 310 encapsulates the top surface of 275) in contact with an upper surface of the coating layer 275,
wherein the coating layer 275 has a flat upper surface overlapping each of the central area 50 and the edge area 40/60 of the planarization layer 270 in the non-light emission area 40/50/60, and
wherein a lower surface of the encapsulation layer 310 is in contact with the flat upper surface of the coating layer 275.
Regarding claim 11, Kim teaches in Figure 4 of a planarization layer (i.e., the same dotted layer in area 30) in the light emission area 30 on a same layer as the planarization layer 270 in the non-light emission area 40/50/60;
an anode electrode 290 (“lower electrode”; paragraph 0027) on the planarization layer (i.e., dotted layer) in the light emission area 30; and
an organic light emitting layer 335 (“light emitting layer”; paragraph 0027; abstract states this is an OLED) on the anode electrode 290,
wherein the coating layer 275 extends to the light emission area 30 and covers an edge (see Figure 4) of the anode electrode 290.
Regarding claim 13, Kim teaches in Figure 4 of a cathode electrode 340 (“upper electrode”; paragraph 0027) on the organic light emitting layer 335 in the light emission area 30,
wherein the encapsulation layer 310 extends to the light emission area 30 and is disposed on the cathode electrode (see area 30).
Regarding independent claim 14, Kim teaches in Figure 4 of a display apparatus (see title), comprising:
a substrate 110 having a light emission area 30, including a pixel 400, and a non-light emission area 40/50/60 in a periphery (i.e., hence periphery) of the light emission area 30;
a plurality of split lines 300/301/302 spaced apart from each other in the non-light emission area 40/50/60, the split lines 300/301/302 being configured to provide a signal for driving the pixel (i.e., expressly at least 301 and indirectly all of the lines);
a passivation layer 200/195 covering a portion of each of the split lines 300/301/302;
a planarization layer 270 on the passivation layer 200/195; and
a connection electrode 330 covering the planarization layer 370 and the passivation layer 200/195 and connecting the split lines 301/302 to each other,
wherein the connection electrode 330 has a stair shape (see Examiner’s Annotated Figure 4 below) extending upward from a portion in contact with one of the split lines 301/302 toward a central area 50 of the planarization layer 270.
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Regarding claim 15, Kim teaches wherein a thickness of the central area 50 of the planarization layer 270 is greater (see Examiner’s Annotated Figure 4 below) than a thickness of an edge area of the planarization layer in a periphery of the central area.
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Regarding claim 16, Kim teaches wherein the central area 50 of the planarization layer 270 overlaps the passivation layer 200/195 without overlapping (i.e., the central portion of 270 in Figure 4 reaches 200 before reaching the split lines 301/302) the split lines 301/302, and
the edge area (i.e., 270 reaching 200) of the planarization layer 270 partially overlaps with both the passivation layer 270 and at least one of the split lines 301/302.
Regarding claim 17, Kim teaches in Figure 4 of the planarization layer 270 includes a side surface (i.e., edge of 40/60) extending to the passivation layer 195, and
the side surface of the planarization layer i.e., edge of 40/60) forms an acute angle (see Examiner’s Annotated Figure 4 below) with an upper surface of the passivation layer 200 overlapping with the planarization layer 270.
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Regarding claim 18, Kim teaches in Figure 4 wherein an upper surface of the planarization layer meets a side surface of the planarization layer 270 at an obtuse angle (see Examiner’s Annotated Figure 4 below).
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Regarding independent claim 20, Kim teaches in Figure 4 and Figure 1 of a display apparatus (see title), comprising:
a substrate 110 having a light emission area 30, including a pixel 400, and a non-light emission area 40/50/60 in a periphery (i.e., hence periphery) of the light emission area 30, the non-light emission area 40/50/60 including a pad area 470 (“pad electrodes”; Figure 1; paragraph 0022) having a plurality of pads 470 (see Figure 1);
a first split line 302 in the non-light emission area 40/50/60 and connected (see paragraph 0037: “In addition, the second fan-out wiring 302 may extend substantially along the first direction D1 in the second peripheral region 60 on the first gate insulation layer 150, and may be electrically connected to an external device 101 through pad electrodes 470 that are disposed in the second peripheral region 60 (refer to FIG. 1)” (bolded for emphasis)) to one of the pads 470 in the pad area 470;
a second split line 301 spaced apart from the first split line 302 in the non-light emission area 40/50/60 and connected to a line (see paragraph 0037: “The first fan-out wiring 301 may extend substantially along the first direction D1 in the first peripheral region 40 on the first gate insulation layer 150, and may electrically connected to the pixel structure 400 that is disposed in the pixel region 30” (bolded for emphasis)) in the light emission area 30 connected to the pixel 400;
a planarization layer 270 overlapping with a portion of each of the first 302 and second 301 split lines in the non-light emission area 40/50/60; and
a connection electrode 330 covering the planarization layer 270 and electrically connecting the first split line 302 with the second split line 301,
wherein the planarization layer 270 includes a central area 50 and an edge area 40/60 in a periphery of the central area 50, the central area 50 having a different thickness from the edge area (see Examiner’s Annotated Figure 4 with respect to claim 1 rejection supra).
Allowable Subject Matter
Claims 6, 8, 9, 12, 19 and 21-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 6, further comprising a passivation layer between the planarization layer and the split lines, wherein the planarization layer includes an upper surface and a side surface extending from the upper surface of the planarization layer to the passivation layer, and wherein the side surface of the planarization layer forms an obtuse angle with an upper surface of the passivation layer that is in contact with the connection electrode.
Claim 8 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 8, wherein a width of a space between the split lines is equal to or smaller than a width of the planarization layer.
Claim 9 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 9, further comprising a planarization layer in the light emission area, the planarization in the light emission area including an upper surface with a plurality of concave grooves, wherein the planarization layer in the non-light emission area includes an upper surface with a concave pattern in the edge area, and wherein the planarization layer in the light emission area and the planarization in the non-light emission area are formed from a same layer.
Claim 12 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 12, wherein the anode electrode is on a same layer as the connection electrode.
Claim 19 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 19, a width of the planarization layer is smaller than a width of the passivation layer, and the connection electrode contacts an upper surface of each of the split lines, an upper surface and a side surface of the passivation layer, and a side surface and an upper surface of the planarization layer.
Claim 21 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 21, further comprising a gate driver in the non-light emission area and spaced apart from the pad area, wherein the gate driver includes a plurality of gate-in-panel (GIP) circuits and a plurality of GIP lines respectively connected to the GIP circuits, the GIP lines including the first and second split lines, and wherein the second split line is disposed in the gate driver and does not extend to the pad area.
Dependent claims 22-25 contain allowable subject matter, because they depend on the allowable subject matter of claim 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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02 January 2026
/John P. Dulka/Primary Examiner, Art Unit 2817