DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-11 in the reply filed on 10/9/25 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shimada (US 2022/0013440).
1. A semiconductor package, comprising:
a substrate (Fig.4A-4B (1/100) and [0021]) extending in first direction and a second direction intersecting the first direction (x/y/z direction- see Fig.4A-4B the substrate is a 3D structure) and comprising a solder resist layer (Fig.2B (300) and [0021]) having an open area thereon (Fig.2B/4B (303) and [0024]);
a semiconductor chip (Fig.4A-4B (500) and [0032]) on the substrate (Fig.4A-4B (1/100) and [0021]) in a third direction (Fig.4A-4B (500) and [0032]), the third direction intersecting the first direction and the second direction (x/y/z direction- see Fig.4A-4B the substrate is a 3D structure),
a first surface of the semiconductor chip (Fig.4A-4B (500-bottom surface) and [0032]) facing the substrate (Fig.4A-4B (1/100) and [0021]); and
a bump structure (Fig.4B (400) and [0032]) in contact with a first connection pad (Fig.4B (200) and [0032]) on the open area (Fig.2B/4B (303) and [0024]) and a second connection pad (Fig.4B (510) and [0032]) on the first surface of the semiconductor chip (Fig.4A-4B (500-bottom surface) and [0032]), and configured to connect the substrate (Fig.4A-4B (1/100) and [0021]) to the semiconductor chip (Fig.4A-4B (500) and [0032]), wherein the open area (Fig.2B/4B (303) and [0024]) comprises a first area (Fig.2B (303- portion 301) and [0024]) and a second area (Fig.2B (303- portion 302) and [0024]) disposed in a peripheral part of the first area (Fig.2B (303- portion 301) and [0024]), and wherein a length of the first area (Fig.2B (303- portion 301) and [0024]) in the first direction (x-direction) is greater than a length of the second area (Fig.2B (303- portion 302) and [0024]) in the first direction (x-direction).
2. The semiconductor package of claim 1, wherein a ratio of the length of the first area (Fig.2B (303- portion 301) and [0024]) in the first direction (x-direction) to a length of the first area (Fig.2B (303- portion 301) and [0024]) in the second direction (z-direction) is larger than a ratio of the length of the second area (Fig.2B (303- portion 302) and [0024]) in the first direction (x-direction) to a length of the second area (Fig.2B (303- portion 302) and [0024]) in the second direction (z-direction) See Fig.2B).
3. The semiconductor package of claim 1, wherein a width of the bump structure (Fig.4B/5A-5B (400/410) and [0032]) in the first area (Fig.2B (303- portion 301) and [0024]) in the second direction (z-direction) is smaller than a width of the bump structure (Fig.4B/5A-5B (400/410) and [0032]) in the second area (Fig.2B (303- portion 302) and [0024]) in the second direction (z-direction).
4. The semiconductor package of claim 1, wherein a length of the first area (Fig.2B (303- portion 301) and [0024]) in the second direction (z-direction) is substantially the same as a length of the second area (Fig.2B (303- portion 302) and [0024]) in the second direction (z-direction).
5. The semiconductor package of claim 1, wherein a length of the bump structure (Fig.4B/5A-5B (400/410) and [0032]) in the first area (Fig.2B (303- portion 301) and [0024]) in the first direction (x-direction) is greater than a length of the bump structure (Fig.4B/5A-5B (400/410) and [0032]) in the first area (Fig.2B (303- portion 302) and [0024]) in the second direction (z-direction).
6. The semiconductor package of claim 1, wherein the open area (Fig.2B/4B (303) and [0024]) comprises a plurality of spaced portions (Fig.2A-2B (303- portions 301 and 302) and [0024]) spaced apart from each other in the second direction (y/z direction- See Fig.s 2A-2B).
7. The semiconductor package of claim 6, wherein each of the plurality of spaced portions comprises curved parts (Fig.6A/6B (301/302/303) and [0041]).
8. The semiconductor package of claim 1, further comprising a plurality of alignment patterns disposed adjacent to edge areas of the semiconductor chip, when viewed in a plan view (Fig.1A- electrodes 200/ solder resists openings 303 are aligned and are interpreted as alignment marks for the mounting board and chip- [0021]).
9. The semiconductor package of claim 8, wherein the plurality of alignment patterns have different shapes (Fig.1A/6A/6B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shimada (US 2022/0013440) in further view of Lee et al (US 20070096336).
In reference to claim 10, Shimada teaches the limitations of claim 1 as cited above; however fails to explicitly teach the limitation of claim 10 as recited below:
10. The semiconductor package of claim 1, further comprising a non-conductive material layer between the substrate and the semiconductor chip.
However Lee et al teaches: further comprising a non-conductive material layer (Fig.1A (12) and [0003]) between the substrate (Fig.1A (11) and [0003])and the semiconductor chip (Fig.1A (10) and [0003]).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Shimada’s teachings to further include an underfill material (Fig.1A (12) and [0003]) as taught by Lee – because doing so provides additional strength to secure the chip and prevent deformation [Lee- [0003]). Moreover, such underfill materials are well-known and commonplace in the art for such purposes.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shimada (US 2022/0013440) in further view of Motoyoshi (WO 2014/136241)
Shimada teaches the limitations of claim 1 as cited above, however fails to teach the limitations of claim 11 as recited below:
11. The semiconductor package of claim 1, further comprising a plurality of semiconductor chips electrically connected via a through via and a connection structure on the semiconductor chip.
However, Motoyoshi teaches a plurality of semiconductor chips electrically connected via a through via and a connection structure on the semiconductor chip (Fig.2A (TSV chips 21) and [0010]).
It would have been obvious to one of ordinary skill in the art to modify Shimada’s teachings to include a chip stack connected via through vias as taught by Motoyoshi because such a configuration is well known in the art of semiconductors and allows for more chip functionality with limited surface space.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park et al (US 20230223327); Igarshi et al (WO 2011102561); and Lee (US 20250336857) teach similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
1/2/26