DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention of Group I, Claims 1-15, in the reply filed on 01/12/2026 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/12/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al. (US 2018/0033646) in view of Gandhi (US 2021/0217863).
Sharangpani et al. discloses, as shown in Figures, a three-dimensional memory device comprising:
an alternating stack of insulating layers (32) and electrically conductive layers (46);
memory openings (49) vertically extending through the alternating stack;
memory opening fill structures (55) located in the memory openings; and
a backside blocking dielectric layer (66); wherein:
each of the memory opening fill structures comprises a respective vertical stack of memory elements (50) and a vertical semiconductor channel (60);
each of the electrically conductive layers comprises a metal layer and a tungsten nitride containing diffusion barrier layer (46A); and
the backside blocking dielectric layer is located between the tungsten nitride containing diffusion barrier layer (46A) and the memory opening fill structures (55).
Sharangpani et al. discloses the backside blocking dielectric layer comprising aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one Lanthanide element, etc. [0102]. Sharangpani et al. does not disclose the backside blocking dielectric layer comprising hafnium or zirconium oxide containing. However, Grandhi discloses a dielectric barrier material (44) formed within voids (42), and the dielectric barrier material (44) is hafnium oxide, zirconium oxide, aluminum oxide, hafnium silicate, or zirconium silicate ([0042]-[0043] and Figure 7 of Grandhi. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the backside blocking dielectric layer of Sharangpani et al. comprising hafnium or zirconium oxide, such as taught by Grandhi since aluminum oxide, and hafnium oxide, etc. are commonly used as the barrier dielectric layer and they are interchangeable.
Regarding claim 2, Sharangpani et al. and Grandhi disclose each of the electrically conductive layers (46) is laterally spaced from the memory opening fill structures (55), an overlying one of the insulating layers, and an underlying one of the insulating layers (32) by the hafnium or zirconium oxide containing blocking dielectric layer (66).
Regarding claim 3, Sharangpani et al. and Grandhi disclose the tungsten nitride containing diffusion barrier layer comprises tungsten nitride [0106].
Regarding claim 4, Sharangpani et al. and Grandhi disclose the tungsten nitride containing diffusion barrier layer comprises tungsten boronitride [0106].
Regarding claim 5, Sharangpani et al. and Grandhi disclose the metal layer comprises tungsten, molybdenum, ruthenium or cobalt [0119].
Regarding claim 6, Sharangpani et al. and Grandhi disclose the metal layer consists essentially of tungsten.
Regarding claim 7, Sharangpani et al. and Grandhi disclose the hafnium or zirconium oxide containing backside blocking dielectric layer comprises hafnium oxide [0043].
Regarding claim 8, Sharangpani et al. and Grandhi disclose the hafnium or zirconium oxide containing backside blocking dielectric layer comprises zirconium oxide [0043].
Regarding claim 9, Sharangpani et al. and Grandhi disclose the hafnium or zirconium oxide containing backside blocking dielectric layer comprises hafnium zirconium oxide [0043].
Regarding claim 10, Sharangpani et al. and Grandhi disclose the hafnium or zirconium oxide containing backside blocking dielectric layer comprises hafnium silicate [0043].
Regarding claim 11, Sharangpani et al. and Grandhi disclose the hafnium or zirconium oxide containing backside blocking dielectric layer comprises zirconium silicate [0043].
Regarding claim 12, Sharangpani et al. and Grandhi disclose the hafnium or zirconium oxide containing backside blocking dielectric layer comprises hafnium zirconium silicate [0043].
Regarding claim 13, Sharangpani et al. and Grandhi disclose the device further comprising an aluminum oxide backside blocking dielectric, wherein the hafnium or zirconium oxide containing backside blocking dielectric layer (66) is spaced from the memory opening fill structures (46), the overlying one of the insulating layers, and the underlying one of the insulating layers (32) by the aluminum oxide backside blocking dielectric layer.
Regarding claim 14, Sharangpani et al. and Grandhi disclose the hafnium or zirconium oxide containing backside blocking dielectric layer (66) is in direct contact with the memory opening fill structures (55), the overlying one of the insulating layers (32), and the underlying one of the insulating layers (Figure 10F).
Regarding claim 15, Sharangpani et al. and Grandhi disclose the vertical stack of memory elements comprises portions of a memory film comprising a charge storage layer (504) located between a tunneling dielectric layer (506) and a front side blocking dielectric layer; and the memory elements are configured to store data by electron storage in the charge storage layer and the three-dimensional memory device does not store data by changing a ferroelectric polarization direction of the memory film (Figs. 2H-3).
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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