DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Response to Arguments
Applicant's arguments filed on 12/18/2025 have been fully considered but they are not persuasive. Applicant’s arguments on page 9, applicants argue “Shi does not disclose combining different error types, such as frequency error with real power error, or voltage error with reactive power error, into a single error value as claimed”. Examiner respectfully disagree because FIG. 4 “delta w” is the combine error of BUS B and Bus A (see further 0026 “Phase angles from buses A and B are subtracted, and passed through a PI controller to determine K.sub.Pφ+K.sub.Iφ/s, where K.sub.Pφ is the proportional gain of the PI controller, and K.sub.Iφ is the integral gain of the PI controller. The output is passed through a mode selection switch, and if the mode for 1 is selected, the change in w is added to the reference frequency w.sub.ref to generate w*.sub.ref”).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8,10-18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shi et al. USPGPUB 20150295581 A1(hereinafter “Shi”).
As to claim 1, Shi teaches a control system to monitor and control a first electric power source coupled in parallel with a second electric power source, wherein the first electric power source and the second electric power source are configured to share a load (FIG. 2 paragraph 0021), the control system comprising: a processor configured to: receive a representation of a first measurement and a representation of a second measurement (paragraph 0029-0034 and FIG. 7-8), wherein the first measurement and the second measurement are measurements of different characteristics of the first electric power source (FIG. 8 and to the “speed” of the power source, which correspond to the frequency); generate corresponding error values for the first measurement and the second measurement and combine the corresponding error values as a single first error value (FIG. 4 and paragraph 0026-0028); compare the single first error value to a first window (FIG. 5 and paragraph 0027), wherein the first window defines upper and lower limits about a first characteristic of the first electric power source around a set point, and wherein the first window is configured to generate a first output signal representing an adjustment to a time- independent component of a closed-loop controller (paragraph 0026-007 and FIG. 5-6); and generate, using the first output signal and the closed-loop controller having a time-dependent component and the time-independent component, a first control signal (FIG. 4 and paragraph 0026); and a controller coupled to the first electric power source and configured to receive the first control signal and, in response, adjust the first characteristic of the first electric power source (paragraph 0021-0022 and FIG. 2).
As to claim 2, Shi teaches wherein the first measurement includes a frequency measurement, the second measurement includes a real power measurement, and the first characteristic is a speed of the first electric power source (FIG. 8 and paragraph 0038-0042).
As to claim 3, Shi teaches wherein the first measurement includes a voltage measurement, the second measurement includes a reactive power measurement, and the first characteristic is a voltage of the first electric power source (FIG. 7 and paragraph 0034-0036).
As to claim 4, Shi teaches wherein the processor is further configured to: receive a representation of a third measurement and a representation of a fourth measurement; generate corresponding error values for the third measurement and the fourth measurement and combine the corresponding error values as a single second error value; and generate, using the single second error value and the closed-loop controller, a second control signal, wherein the controller is further configured to receive the second control signal and, in response, adjust a second characteristic of the first electric power source (paragraph 0035-005 and FIG. 2-8).
As to claim 5, Shi teaches wherein the first measurement includes a frequency measurement, the second measurement includes a real power measurement, the third measurement includes a voltage measurement, and the fourth measurement includes at least one of a reactive power measurement or a power factor measurement (paragraph 0035-0044 and FIG. 7-8).
As to claim 7, Shi teaches wherein the processor is further configured to: compare the single first error value to a second window, wherein the second window defines upper and lower limits about a second characteristic of the first electric power source, wherein the second window is configured to generate a second output signal representing an adjustment to the time-dependent component of the closed-loop controller (paragraph 0035-005 and FIG. 2-8).
As to claim 8, Shi teaches wherein the time-independent component is a proportional component, wherein the time-dependent component is an integral component (paragraph 0026-0028).
As to claim 10, is related to claim 1 with similar limitations also rejected by same rational.
As to claim 11, is related to claim 2 with similar limitations also rejected by same rational.
As to claim 12, is related to claim 3 with similar limitations also rejected by same rational.
As to claim 13, is related to claim 4 with similar limitations also rejected by same rational.
As to claim 14, is related to claim 5 with similar limitations also rejected by same rational.
As to claim 16, is related to claim 7, with similar limitations also rejected by same rational.
As to claim 17, is related to claim 8 with similar limitations also rejected by same rational.
As to claim 19, is related to claim 1 with similar limitations also rejected by same rational.
As to claim 20, is related to claim 2 with similar limitations also rejected by same rational.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi et al. USPGPUB 20150295581 A1(hereinafter “Shi”) in view of Deboy et al. USPGPUB 2013/0181530 (hereinafter “Deboy”).
As to claims 9 and 19, Shi teaches all the limitations of base claims as outlined above.
Shi does not explicitly wherein the closed-loop controller includes a proportional-integral-derivative (PID) controller.
However, Deboy teaches wherein the closed-loop controller includes a proportional-integral-derivative (PID) controller (paragraph 0106-0117).
Shi and Deboy are analogous art because they are from the same field of endeavor and contain overlapping structural and functional similarities. They both relate to power generation system.
Therefore at the time of effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the above power generation system, as taught by Shi, and incorporating closed-loop controller includes a proportional-integral-derivative (PID) controller, as taught by Deboy.
One of ordinary skill in the art would have been motivated to increasing interest in sustainable energy production there is a focus on using photovoltaic modules for producing electric power. Photovoltaic (PV) modules include a plurality of photovoltaic (PV) cells, that are also known as solar cells, as suggested by Deboy (paragraph 0003).
Allowable Subject Matter
Claims 6 and 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and listed on the attached PTO Form 892 but not relied upon is considered pertinent to applicant's disclosure.
Deboy et al USPGPUB 2014/0191582 teaches a power converter circuit includes a synchronization circuit that is configured to generate at least one synchronization signal. A series circuit includes a number of converter units configured to output an output current. At least one of the converter units includes a transformer and is configured to generate an output current such that a frequency or a phase of the generated output current is dependent on the synchronization signal.
ROSCOE USPGPUB 2013/0051103 teaches a method of controlling an inverter for converting a DC input to an AC output, the method including measuring a voltage of an AC output produced by the inverter; determining a drive voltage for controlling the inverter; and if a difference in amplitude and/or phase between the drive voltage and the measured voltage exceeds a predetermined threshold, modifying the drive voltage to reduce the difference in amplitude and/or phase between the drive voltage and the measured voltage. The method may be particularly useful for controlling an inverter during "islanded" operation with a variable load, and may therefore be useful e.g. in marine, battlefield, disaster relief and/or aviation electrical power systems.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZIAUL KARIM whose telephone number is (571)270-3279. The examiner can normally be reached on Monday-Thursday 8:00-4:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mohammad Ali can be reached on 571 272 4105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZIAUL KARIM/Primary Examiner, Art Unit 2119