Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, and 10 are rejected under 35 U.S.C. 102a1 as being anticipated by US20200006166A1 (Raorane).
Regarding Claim 1, Raorane discloses a microelectronic element package assembly (Fig. 1, el. 100, Para. [0024]), comprising: a package substrate (Fig. 1, el. 102, Para. [0024]), having a substrate body (Fig. 1, el. 102), substrate contacts (Fig. 1, el. 122, Para. [0024]) disposed at a top surface of the substrate body (Fig. 1, Para. [0024]), package terminals (Fig. 1, el. 134, Para. [0024]) disposed at a bottom surface of the substrate body (Fig. 1, Para. [0024]), and routing lines disposed between the top and bottom surfaces (Para. [0030]); at least two microelectronic elements (Fig. 1, el. 114, Para. [0031]) electrically connected to the substrate contacts (Para. [0024]); a microelectronic element capacitor carrier (Fig. 1 and 3A, el. 380, Para. [0035]) overlying and bonded to the package substrate (Para. [0024]); the capacitor carrier including: a plurality of ground contacts electrically connected to a ground source (Para. [0027] – “The conductive pathways 186 may allow power, ground, and other electrical signals to move between the component 184 and the package substrate 102”); a plurality of power contacts electrically connected to a power source (Para. [0027] – see above); and capacitor routing lines (Fig. 1, el. 186, Para. [0024]), wherein at least some of the capacitor routing lines are connected to the plurality of ground contacts (Para. [0027]) and other capacitor routing lines are electrically connected to the plurality of power contacts (Para. [0027]), wherein the capacitor carrier is positioned laterally adjacent the at least two microelectronic elements (Fig. 1) and extends at least partially around the at least two microelectronic elements (Para. [0025]) so that an inner edge of the capacitor carrier is adjacent outer edges of the last two microelectronic elements (Fig. 1); and a plurality of capacitors (Fig. 1, el. 184, Para. [0028] and [0030]) joined to the capacitor carrier (Fig. 1, Para. [0024]), each of the plurality of capacitors having a first end joined to one of the plurality of ground contacts (Fig. 1, Para. [0027]) and a second end joined to one of the plurality of power contacts (Fig. 1, Para. [0027]), at least some of the plurality of capacitors providing power to at least one of the at least two microelectronic elements (Para. [0027]).
Regarding Claim 6, Raorane discloses the assembly of claim 1, wherein the plurality of capacitors are bonded to a top surface of the capacitor carrier (Fig. 5A, Para. [0037]) and arranged in arrays across the top surface of the capacitor carrier (Fig. 5A, els. 184, Para. [0037]).
Regarding Claim 10, Raorane discloses the assembly of claim 1, wherein the at least two microelectronic elements comprise at least three microelectronic elements (Para. [0031] which describes an assembly with a CPU, PCH, DRAM, etc.), wherein at least one of the at least three microelectronic elements is an integrated circuit chip (Para. [0031]) and two of the least three microelectronic elements are high-performance computing chips (Para. [0031]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Raorane.
Regarding Claim 2, Raorane discloses the assembly of claim 1, wherein the capacitor carrier is comprised of ceramic (Para. [0025]).
Raorane does not disclose that that the ceramic is low temperature co-fired.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to use low temperature co-fired ceramic to make the capacitor carrier. As is well-known in the art, using low-temperature co-fired ceramic is beneficial for embedding passive components and reducing size.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Raorane.
Regarding Claim 3, Raorane discloses the assembly of claim 2, wherein the capacitor carrier further includes a main body (Fig. 3, els. 380-1 and 380-2, Para. [0035]), wherein the capacitor routing lines further comprise dedicated power lines and dedicated ground lines (Fig. 3, els. 386-1, Para. [0035]) extending in the main body of the capacitor carrier, and the routing lines of the package substrate further comprises capacitor power lines and capacitor ground lines extending in the substrate body (Para. [0030]). Raorane further discloses that a carrier can have multiple capacitors (Para. [0030]).
Raorane does not disclose that the power and ground lines extend throughout the main body of the capacitor carrier, and does not disclose that the power and ground lines extend throughout the substrate body.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to extend both sets of power and ground lines throughout their respective bodies. In the case of the of the capacitor carrier, if there are multiple capacitors side by side, it would be beneficial to have power and ground lines extending through the body. In the case of the substrate body, having power and ground lines extending throughout the body allows for the capacitors to be distributed around the chips and allows for efficient routing to other chips.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Raorane.
Regarding Claim 4, Raorane discloses the assembly of claim 1, where the capacitor carrier extends contiguously around the at least two microelectronic elements (Para. [0025] – “In some embodiments, the stiffener 180 may take the shape of a frame or outer ring along the perimeter of the package substrate 102 on the outside of the die 114”), the capacitor carrier being disposed between the peripheral edge of the package substrate and the outer edges of the at least two microelectronic elements (Fig. 1).
Raorane does not disclose that the capacitor carrier has a peripheral edge spaced away from a peripheral edge of the package substrate.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to move the capacitor carrier of Raorane inwards so that it has a peripheral edge spaced away from the peripheral edge of the package substrate. This would be a simple rearrangement of parts (MPEP 2144.04(VI)(C)).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Raorane.
Regarding Claim 5, Raorane discloses the assembly of claim 1, wherein the capacitor carrier comprises a plurality of capacitor carrier components that are positioned around the package substrate to collectively from the shape of a ring (Para. [0025] – “For example, a package substrate may include two L-shaped stiffeners arranged to form a non-continuous frame around the perimeter of the package substrate”).
Raorane does not disclose that the capacitor carrier has a peripheral edge spaced away from a peripheral edge of the package substrate.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to move the capacitor carrier of Raorane inwards so that it has a peripheral edge spaced away from the peripheral edge of the package substrate. This would be a simple rearrangement of parts (MPEP 2144.04(VI)(C)).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Raorane.
Regarding Claim 9, Raorane discloses the assembly of claim 1.
Raorane does not disclose that the others of the plurality of capacitors are electrically interconnected a second of the least two microelectronic elements.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to electrically interconnect the some of the capacitors to a second of the least two microelectronic elements. This has the benefit of providing, for example, a bypass capacitor for the second microelectronic element.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Raorane in view of US20190109122A1 (Ong).
Regarding Claims 7 and 8, Raorane discloses the assembly of claim 1.
Raorane does not disclose that the assembly further comprises a heat spreader overlying the plurality of capacitors and the at least two microelectronic elements.
Ong discloses an assembly (Fig. 1M, el. 109, Para. 0047]) with a capacitor carrier (Fig. 1M, el. 112a, Para. [0047]), a microelectronic element (Para. [0026]), a plurality of capacitors (Fig. 1M, el. 117, Para. [0030]), and a heat spreader overlying the plurality of capacitors and the microelectronic element (Fig. 1M, el. 156, Para. [0057]).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add a heat spreader over the capacitors and microelectronic components, as in Ong. As disclosed by Ong, doing so has the benefit of improving heat dissipation (Para. [0022]), while improving stiffness (the heat spreader can also be a stiffener, as in Ong).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Raorane in view of US20100084175A1 (Suzuki).
Regarding Claims 11-12, Raorane discloses the assembly of claim 1.
Raorane does not disclose that the capacitor carrier is comprised of a material having a coefficient of thermal expansion ranging from 5 ppm/C to 10 ppm/C or from 10 ppm/C to 15 ppm/C, and does not disclose that the Young’s modulus ranges from 150 GPa to 350 GPa or a range from 50 GPa to 150 GPa.
Suzuki discloses a ceramic capacitor (Fig. 1, el. 101, Para. [0046]) with a CTE of 4.6 ppm/C and 11.7 ppm/C and a Young modulus of 120 GPa.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to use materials with a CTE and Youngs modulus close to the numbers disclosed by Suzuki. It is well-known that it is important to match the characteristics of a capacitor carrier with the capacitor. Further, changing the ranges would be achieved through routine optimization (2144.05 II).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Raorane in view of US10764996B1 (Boja).
Raorane discloses the assembly of claim 1.
Raorane does not disclose that the package assembly further comprises an interposer that provides an electrical interconnection between the at least two microelectronic elements and the package substrate.
Boja discloses a package assembly (Fig. 1, el. 110, Col. 3, ll. 36-38), with a plurality of microelectronic elements (Fig. 1, els. 114, Col. 3, ll. 48-49), a package substrate (Fig.1 , el. 122, Col. 3, ll. 48-50), and an interposer (Fig. 1, el. 112, ll. 48-51) that provides an electrical interconnection between the at least two microelectronic elements and the package substrate (Col. 3, ll. 65-67).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add an interposer between the microelectronic elements and package substrate, as in Boja. As disclosed by Boja, this has the advantage of allowing more circuity, including transistors, to be added to the assembly (Cols. 3-4, ll. 66-2).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Raorane in view of Boja and Suzuki.
Regarding Claim 14, Raorane discloses a microelectronic element package assembly (Fig. 1, el. 100, Para. [0024]), comprising: a package substrate (Fig. 1, el. 102, Para. [0024]), at least two microelectronic elements (Fig. 1, el. 114, Para. [0031]) electrically connected to the substrate (Para. [0024]); a capacitor carrier ring (Fig. 1 and 3A, el. 380, Para. [0035]) overlying the package substrate (Para. [0024]) and extending circumferentially around the at least two microelectronic elements (Para. [0025]), the CCR further comprising a plurality of ground contacts electrically connected to a ground source (Para. [0027]) and a plurality of power contacts electrically connected to a power source (Para. [0027]); a plurality of arrays of capacitors (Fig. 1, el. 184, Para. [0028] and [0030]), each of the capacitors in the plurality of arrays of capacitors having a first end joined to one of the plurality of ground contacts (Fig. 1, Para. [0027]) and a second end joined to one of the plurality of power contacts (Fig. 1, Para. [0027]), wherein at least some of the plurality of capacitors in the one ore more of the plurality of arrays of capacitors are electrically connected with one of the at least two microelectronic elements (Para. [0027]).
Raorane does not disclose an interposer overlying and bonded to the package substrate and that the at least two microelectronic elements are connected to the package substrate through the interposer; does not disclose that the CCR is comprised of a material having a CTE ranging from 5-15 ppm/C and a Young’s modulus ranging from 25-350 GPa.
Boja discloses a package assembly (Fig. 1, el. 110, Col. 3, ll. 36-38), with a plurality of microelectronic elements (Fig. 1, els. 114, Col. 3, ll. 48-49), a package substrate (Fig.1 , el. 122, Col. 3, ll. 48-50), and an interposer (Fig. 1, el. 112, ll. 48-51) that provides an electrical interconnection between the at least two microelectronic elements and the package substrate (Col. 3, ll. 65-67). Suzuki discloses a ceramic capacitor (Fig. 1, el. 101, Para. [0046]) with a CTE of 4.6 ppm/C and 11.7 ppm/C and a Young modulus of 120 GPa.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add an interposer between the microelectronic elements and package substrate, as in Boja. As disclosed by Boja, this has the advantage of allowing more circuity, including transistors, to be added to the assembly (Cols. 3-4, ll. 66-2). Further, It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to use use materials with a CTE and Youngs modulus close to the numbers disclosed by Suzuki. It is well-known that it is important to match the characteristics of a capacitor carrier with the capacitor. Further, changing the ranges would be achieved through routine optimization (2144.05 II).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Raorane in view of Boja and Suzuki.
Regarding Claim 15, Raorane in view of Boja and Suzuki discloses the assembly of claim 14, wherein the CCR comprises a ceramic material (Para. [0025]).
Raorane does not disclose that that the ceramic is laminated.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to use laminated ceramic to make the CCR. As is well-known in the art, using laminated ceramic is beneficial for improving the strength of the CCR.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Raorane in view of Suzuki.
Regarding Claim 17, Raorane in view of Boja and Suzuki discloses the assembly of Claim 14, wherein the capacitors are at least partially embedded within the CCR (Raorane, Fig. 3A, Para. [0035]).
Regarding Claim 18, Raorane discloses the assembly of claim 1.
Raorane does not disclose that the assembly further comprises a heat spreader overlying the plurality of capacitors.
Ong discloses an assembly (Fig. 1M, el. 109, Para. 0047]) with a capacitor carrier (Fig. 1M, el. 112a, Para. [0047]), a microelectronic element (Para. [0026]), a plurality of capacitors (Fig. 1M, el. 117, Para. [0030]), and a heat spreader overlying the plurality of capacitors and the microelectronic element (Fig. 1M, el. 156, Para. [0057]).
it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add a heat spreader over the capacitors, as in Ong. As disclosed by Ong, doing so has the benefit of improving heat dissipation (Para. [0022]), while improving stiffness (the heat spreader can also be a stiffener, as in Ong).
Claims 19 and 20 are rejected under 35 U.S.C. 102a1 as being anticipated by Raorane in view of Ong.
Regarding Claim 19, Raorane discloses a chip package assembly (Fig. 1, el. 100, Para. [0024]) comprising: a package substrate (Fig. 1, el. 102, Para. [0024]) having at least one power contact electrically connected to a power source (Para. [0029]); at least two chips electrically connected to the package substrate (Para. [0031]); a stiffening element (Fig. 3A, el. 380, Para. [0035]) jointed to the package substrate (Fig. 1, Para. [0035]) and extending at least partially around the at least two chips (Para. [0025]), the stiffening element positioned directly adjacent the at least two chips (Fig. 1), and the stiffening element further including at least one pocket (Fig. 3A, el. 382, Para. [0035]), wherein the pocket includes an interior contact surface (see annotated Fig. 3A below) and interior walls extending around and away from the interior contact surface and terminating in an opening (see annotated Fig. 3A below); and a plurality of chip capacitors disposed within the at least one pocket (Para. [0030]), one end of each of the plurality of chip capacitors being joined to the interior contact surface (Fig. 3A, Para. [0035]) and another end of each of the plurality of chip capacitors being joined to the power contact (Para. [0035]).
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Raorane does not disclose that the stiffening element is electrically connected to a ground source so that the stiffening element is a ground.
Ong disclose an assembly (Fig. 1, el. 100, Para. [0014]) comprising a package substrate (Fig. 1, el. 102, Para. [0015]), an electrically conductive stiffener with a pocket (Fig. 1, el. 116, Para. [0016]), where the stiffener is electrically connected to a ground source so that the stiffening element is ground (Para. [0021]), and a plurality of capacitors disposed within the pocket (Fig. 1, Para. [0015]), where one end of each of the plurality of capacitors is joined to an interior contact surface (Fig. 1, Para. [0021]) and the other end is joined to a power contact (Fig. 1, Para. [0021]).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to have the stiffener of Raorane connected directly to ground, with one end of the capacitors connected directly to the interior contact surface, and the other connected to a power source, as disclosed by Ong. As disclosed by Ong, this has the benefit of providing additional electrical shielding in a multi-device package (Para. [0021]).
Regarding Claim 20, Raorane in view of Ong discloses the assembly of claim 19, wherein the stiffening element is a monolithic structure (Raorane, Para. [0025] – “In some embodiments, for example, the stiffener 180 may take the shape of a frame or outer ring along the permiter of the package substrate 102 and …..may be….rectangular”).
Allowable Subject Matter
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 16, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination that the CCR comprises a PCB and another PCB joined to the CCR and overlying the plurality of arrays of capacitors.
Conclusion
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899