Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed February 3, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 8, 14
b. Pending: 1, 3-8, 10-14, 16-20
Claims 1, 3, 4, 8, 10, 11, 14, 16, 17 have been amended, and claims 2, 9, and 15 have been canceled.
Response to Arguments
Applicant's arguments filed February 3, 2026 have been fully considered but they are not persuasive. The Attorney argues on page 13 that Mui et al. (US Pub. 20140211568 A1; “Mui-2”) does not teach the limitations of claim 2. The subject matter of claim 2 has been incorporated into claim 1 and claim 2 has been canceled. Claims 9 and 15, which contain mostly the same subject matter as claim 2, have been incorporated into claims 8 and 14, respectively, and are also canceled.
On page 13, line 17 through page 14, line 5, Attorney argues that Mui-2 does not teach sensing a current between the first and second periods of time. Specifically, Attorney states, “amended claim 1 now requires the sensing to occur between the first and second periods of time, not during one or the other”. This argument is not persuasive because it does not make sense to argue that the current measurement must be “between” the two time periods but that the current measurement may not occur during either or both time periods. Examiner’s reasoning is as follows:
Per Figs. 15 and 16 of the original disclosure, time periods R1 and R2 are adjacent, with no gaps in between (see annotated screenshot below).
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Also, Figs. 19 and 20 show that compared to closed blocks, open blocks have an increased current in between two peaks of cell current. The R1 and R2 labels on Fig. 19 indicate that there is a peak in cell current during time period R1 and there is a peak in cell current during time R2. The labels do not indicate the bounds of time periods R1 and R2, much less a gap between the two time periods that coincides with the valley in the cell current level.
A reasonable person would assume that if there are two time periods R1 and R2, they would immediately follow each other, or that if there was a gap in time—an intermediate time period—between R1 and R2, it too would have a label, such as Rgap.
Please also refer to the 112(b) rejection below.
Specification
The disclosure is objected to because of the following informalities:
While the title of the invention is descriptive, it is unclear and does not have proper grammar. The following title is suggested: Open block detection method and cell current control for non-volatile memory apparatus.
In paras. [0110], [0112], [0116], and [0121], the word “between” is used (“between R1-R2 valley” in [0110] and [0116] and “between the first period of time R1 and the second period of time R2” in [0112] and [0121]). The Examiner recommends revising these phrases to “during the current ‘valley’ which occurs between the R1 current peak and the R2 current peak”. The following portion of para. [0110] is clear and could be useful for amendments:
“During the first and second periods of time (i.e., R1-R2 period), which corresponds to word line pre-charging and word line ramping, there is a valley that appears to show block openness-dependent ICC current. The first peak (R1) corresponds to read pump preparation. The R1-R2 valley correlates with block openness”
Appropriate correction is required.
Claim Objections
Claims 1, 8, 9, and 14 are objected to because of the following informalities:
Regarding claims 1, 8, and 14, make the following change:
“selected ones of the plurality of word lines ramp to at least one read pass voltage”
Regarding claim 9, on page 6 of the Claims filed February 3, 2026, make the following change:
9. (Canceled).
Appropriate correction is required.
Double Patenting
Double patenting rejections have been withdrawn pursuant to claim amendments.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-8, and 10-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claims 1 and 8 recite “sense electric current consumed by the memory apparatus between the first period of time (R1) and the second period of time (R2) of the at least one read operation”. This phrase is indefinite because it is unclear from the claim how the two periods of time relate to each other (although the use of ‘R1’ and ‘R2’ suggests that R2 should immediately follow R1), and it is unclear whether the claim is teaching that the sensing of current occurs in a separate time period between two time periods, or if the sensing occurs sometime within the R1-to-R2 time range. Independent claims 1 and 8, and claims 3-7 and 10-13, which depend on those independent claims, are thus rejected under 35 U.S.C. 112(b).
Examiner suggests amending claims 1 and 8 using language from para. [0110] of the Specification. Refer to Specification objection 2 for recommended changes to the Specification, which could also inform claim amendments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Mui (US Pub. 20150003162 A1) in view of Park (US Pub. 20170235633 A1).
Regarding independent claim 1, Mui discloses a memory apparatus (Fig. 5: memory device 596; [0064]), comprising:
a memory block (Fig. 4: block BLK0; [0059]) including a plurality of memory cells that are arranged in a plurality of word lines ([0060]: The array of memory cells is divided into a large number of blocks (e.g., BLK0-BLK2) of memory cells, where each block includes a set of one or more NAND strings in communication with a common set of word lines), the memory cells being configured to retain a threshold voltage corresponding to one of a plurality of data states ([0067]: FIG. 6B depicts a Vth distribution which follows FIG. 6A after a programming operation. This example includes the erased state (E) and three programmed states (A, B and C) for a total of four data states) and being disposed in memory holes ([0042]: Each NAND string may include a channel region which extends horizontally in a substrate in the case of 2D NAND, or in a vertically in a channel layer of a memory hole, in the case of 3D NAND); and
a control means (Fig. 5: control circuitry 510; [0064]) coupled to the word lines and the memory holes and configured to:
during at least one read operation to read data ([0067] references a read operation) contained in the memory cells of a selected word line of the plurality of word lines, the memory cells of the selected word line being already programmed to contain readable data ([0069]: Vdem is a read voltage which can be applied to a selected word line in a current sensing operation so that the programmed memory cells will be in a non-conductive state and the erased state memory cells will be in a conductive state), determine an amount of the memory cells within the memory block that are programmed by measuring current in the memory block ([0117]: The control circuit: measures a combined current through the plurality of NAND strings as a reference combined current while applying a read pass voltage to the plurality of word lines, and to identify one or more selected word lines of the plurality of word lines which are programmed word lines, for each of the one or more selected word lines: measures an additional combined current through the plurality of NAND strings while applying a demarcation voltage to the selected word line and applying the read pass voltage to remaining word lines of the plurality of word lines; [0047]: A number (Nwl) of programmed word lines in a block can also be counted. Examiner asserts that counting programmed word lines is analogous to counting programmed memory cells),
Mui teaches adjustable parameters but does not disclose:
adjust at least one read parameter based on the amount of the memory cells within the memory block that are programmed,
and utilize the adjusted at least one read parameter while reading the memory cells of the selected word line.
However, Park teaches:
adjust at least one read parameter based on the amount of the memory cells within the memory block that are programmed ([0099]: In a program operation, the data storage device 1000 according to example embodiments of inventive concepts stores the number of cells of each state (E0, P1, P2, and P3). The data storage device 1000 may predict a moving direction and a moving level of the read voltage using the number of cells and ECC information. Examiner asserts that the read voltage may be a read parameter),
and utilize the adjusted at least one read parameter while reading the memory cells of the selected word line ([0049]: The address decoder 1120 selects a word line in a program or read operation. A select read voltage or a read voltage is provided to the selected word line; also see claim 9: a memory controller configured to search a read voltage of the nonvolatile memory based on fail bit information calculated using a number of original memory cells stored in a specific state in a program operation, a number of memory cells of a specific state calculated by a read operation).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Park to Mui wherein a control means is configured to adjust at least one read parameter based on the amount of the memory cells within the memory block that are programmed, and utilize the adjusted at least one read parameter while reading the memory cells within the memory block that are programmed in order to reduce the time needed to determine an optimal read voltage, and thereby improve read performance (Park, [0042]).
Regarding independent claim 8, all but its last limitation are nearly identical in claimed subject matter as claim 1 except for their focus on the controller as being configured to perform all of the limitations. Thus, all but the last limitation of independent claim 8 are rejected for the same reasons as independent claim 1.
Mui teaches adjustable parameters but does not disclose:
instruct the memory apparatus to utilize the adjusted at least one read parameter while reading the memory cells of the selected word line to determine if the memory cells have the threshold voltage above one or more of a plurality of read levels associated with each of the plurality of data states in the at least one read operation.
However, Park teaches:
instruct the memory apparatus to utilize the adjusted at least one read parameter while reading the memory cells of the selected word line ([0049]) to determine if the memory cells have the threshold voltage above one or more of a plurality of read levels associated with each of the plurality of data states in the at least one read operation ([0070]: FIG. 6 (a) illustrates an example where a progressive defect occurs in a direction in which threshold voltages of memory cells increase…Such progressive defect may occur when data is repeatedly written and erased, when data is repeatedly read, or when a large amount of time passes after data is written; [0071]: The data storage device 1000 according to example embodiments of inventive concepts, in a case where a distribution of memory cells is changed, provides a method of searching an optimum read voltage level; [0097]: Assume that read voltages being provided to a select word line in an initial state are Vrd1, Vrd2 and Vrd3. Here, the Vrd1 is a read voltage level to distinguish between the E0 and the P1. Although not illustrated, the Vrd2 is a read voltage level to distinguish between the P1 and the P2; also see claim 9: a memory controller configured to search a read voltage of the nonvolatile memory based on fail bit information calculated using a number of original memory cells stored in a specific state in a program operation, a number of memory cells of a specific state calculated by a read operation).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Park to modified Mui wherein the controller is configured to instruct the memory apparatus to utilize the adjusted at least one read parameter while reading the memory cells of the selected word line to determine if the memory cells have the threshold voltage above one or more of a plurality of read levels associated with each of the plurality of data states in the at least one read operation in order to reduce the time needed to determine an optimal read voltage, and thereby improve read performance (Park, [0042]).
Independent claim 14 is nearly identical in claimed subject matter as claim 1 except for being drafted in method format instead of device format and is rejected for the same reasons as independent claim 1.
Claims 2, 5, 9, 12, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Mui (US Pub. 20150003162 A1) in view of Park (US Pub. 20170235633 A1), and further in view of Mui-2 (US Pub. 20140211568 A1).
Regarding claim 2, Mui and Park together disclose the limitations of claim 1,
and further through Mui:
further including a power circuit (Fig. 5: power control module 516) configured to measure an electrical current consumed by the memory apparatus ([0065]: The power control module 516 controls the power and voltages supplied to the word lines and bit lines during memory operations; [0117]), wherein the at least one read operation ([0067])
determine the amount of the memory cells of the memory block that are programmed based on the electrical current consumed by the memory apparatus ([0117]) between the first period of time and the second period of time of the at least one read operation (Examiner asserts that the determination of the amount of memory cells may occur between a first and second period of time).
Neither Mui nor Park disclose:
further including a power circuit configured to measure an electrical current consumed by the memory apparatus, wherein the at least one read operation includes a first period of time in which the plurality of word lines ramp up to a power supply voltage and a second period of time in which selected ones of the plurality of word lines ramp to at least one read pass voltage and unselected ones of the plurality of word lines ramp to the at least one read pass voltage, the read pass voltage selected to allow the memory cells connected to the plurality of word lines to conduct, and the control means is further configured to:
using the power circuit, sense the electrical current consumed by the memory apparatus between the first period of time and the second period of time of the at least one read operation; and
However, Mui-2 teaches:
further including a power circuit (Fig. 3: power control module 226; [0046]: The power control module 226 controls the power and voltages supplied to the word lines and bit lines during memory operations) configured to measure an electrical current consumed by the memory apparatus ([0071]: After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turned on in response to the voltage applied to the word line), wherein the memory cells are each connected to one of a plurality of word lines, the at least one read operation includes a first period of time in which the plurality of word lines ramp up to a power supply voltage ([0046]: The power control module 226 controls the power and voltages supplied to the word lines and bit lines during memory operations. In one embodiment, power control module 226 includes one or more charge pumps that can create voltages larger than the supply voltage; [0050]: During read or sensing, the operation of the system is under the control of state machine 222 that controls the supply of different control gate voltages to the addressed cell. As it steps through the various predefined control gate voltages (the read reference voltages or the verify reference voltages) corresponding to the various memory states supported by the memory; the first period of time may be Fig. 30, step 3002; [0159]: In step 3002, the selected word line (common to the selected memory cells connected to the top and bottom) is pre-charged to the demarcation Vth) and a second period of time in which selected ones of the plurality of word lines ramp to at least one read pass voltage ([0071]: In general, during verify operations and read operations, the selected word line is connected to a voltage (one example of a reference signal), a level of which is specified for each read operation; the second period of time may be Fig. 30, step 3004; [0159]: In step 3004, the selected memory cells connected to the selected word line will be sensed (first pass) during the same time period to see if their respective threshold voltage is less than the demarcation Vth) and unselected ones of the plurality of word lines ramp to the at least one read pass voltage, the read pass voltage selected to allow the memory cells connected to the plurality of word lines to conduct ([0071]: During a read or verify process, the unselected memory cells are provided with one or more read pass voltages at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased)), and the control means is further configured to:
using the power circuit, sense the electrical current consumed by the memory apparatus ([0071]) between the first period of time and the second period of time of the at least one read operation ([0162]: based on the determined sensing parameter sense whether current conducted by the non-volatile element exceeds a pre-determined value; also see [0160]-[0161] and [0163]-[0164]. Examiner concludes that the sensing of the current occurs during the sensing step, 3004, which is encompassed in the duration of time that includes the first and second periods of time); and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Mui-2 to modified Mui wherein the memory apparatus further includes a power circuit configured to measure an electrical current consumed by the memory apparatus, wherein the at least one read operation includes a first period of time in which the plurality of word lines ramp up to a power supply voltage and a second period of time in which selected ones of the plurality of word lines ramp to at least one read pass voltage and unselected ones of the plurality of word lines ramp to the at least one read pass voltage, the read pass voltage selected to allow the memory cells connected to the plurality of word lines to conduct, and the control means is further configured to, using the power circuit, sense the electrical current consumed by the memory apparatus between the first period of time and the second period of time of the at least one read operation in order to account for variances in bit line resistance by adjusting current testing based on the position of the memory cell from the sensing circuitry (Mui-2, [0038]).
Regarding claim 5, Mui and Park together disclose the limitations of claim 1,
and further through Mui:
wherein the memory holes ([0042]) are each connected to one of a plurality of bit lines ([0004]: A straight NAND string extends in one memory hole; [0049]: The NAND string depicted in FIGS. 1A and 1B includes four transistors, 100, 102, 104 and 106, in series and sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 connects the NAND string to bit line 126), the at least one read operation ([0067])
Neither Mui nor Park disclose:
the at least one read operation includes a fourth period of time in which one or more of the plurality of bit lines are ramped up to a bit line voltage and the control means is further configured to utilize the adjusted at least one read parameter beginning at the fourth period of time.
However, Mui-2 teaches:
wherein the memory holes are each connected to one of a plurality of bit lines, the at least one read operation ([0050]) includes a fourth period of time ([0148]: FIG. 27 is a timing diagram describing the behavior of various signals from FIG. 25. The signal BLS is at Vdd the entire time depicted and the signal BLC is at Vbl+Vsrc+Vth, where Vbl is the voltage of the Bit Line, Vsrc is the voltage of the source line and Vth is the threshold voltage of transistor 902. Examiner concludes that the fourth period of time may be a time before the time shown in Fig. 27) in which one or more of the plurality of bit lines are ramped up to a bit line voltage ([0138]: Transistor 2502 receives the signal BLC at its gate, and is used as a voltage clamp. The gate voltage BLC is biased at a constant voltage equal to the desired Bit Line voltage plus the threshold voltage of transistor 2502. The function of transistor 2502, therefore, is to maintain a constant Bit Line voltage during a sensing operation (during read or verify)) and the control means is further configured to utilize the adjusted at least one read parameter ([0046]) beginning at the fourth period of time ([0148]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Mui-2 to modified Mui wherein the memory holes are each connected to one of a plurality of bit lines, the at least one read operation includes a fourth period of time in which one or more of the plurality of bit lines are ramped up to a bit line voltage and the control means is further configured to utilize the adjusted at least one read parameter beginning at the fourth period of time in order to account for variances in bit line resistance by adjusting current testing based on the position of the memory cell from the sensing circuitry (Mui-2, [0038]).
Regarding claim 9, Mui and Park together disclose the limitations of claim 8. Claim 9 recites substantially the same limitations as claim 2, and henceforth is rejected for the same reasons.
Regarding claim 12, Mui and Park together disclose the limitations of claim 8. Claim 12 recites substantially the same limitations as claim 5, and henceforth is rejected for the same reasons.
Regarding claim 15, Mui and Park together disclose the limitations of claim 14. Claim 15 recites substantially the same limitations as claims 2 and 9, and henceforth is rejected for the same reasons.
Regarding claim 18, Mui and Park together disclose the limitations of claim 14. Claim 18 recites substantially the same limitations as claims 5 and 12, and henceforth is rejected for the same reasons.
Claims 3, 10, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Mui (US Pub. 20150003162 A1), Park (US Pub. 20170235633 A1), and Mui-2 (US Pub. 20140211568 A1), and further in view of Lei et al. (US Pub. 20130242661 A1; “Lei”).
Regarding claim 3, Mui, Park, and Mui-2 together disclose the limitations of claim 2, and further through Mui:
wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack ([0004]: a 3D NAND stacked memory device can be formed from an array of alternating conductive and dielectric layers), the memory holes extend vertically through the stack ([0042]: Each NAND string may include a channel region which extends horizontally in a substrate in the case of 2D NAND, or in a vertically in a channel layer of a memory hole, in the case of 3D NAND), the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes ([0049]: One example of a memory system suitable for implementing the present technology uses the NAND flash memory structure, which arranges multiple transistors in series between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1A is a top view showing one NAND string. FIG. 1B is an equivalent circuit thereof. The NAND string depicted in FIGS. 1A and 1B includes four transistors, 100, 102, 104 and 106, in series and sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 connects the NAND string to bit line 126. Select gate 122 connects the NAND string to source line 128), the drain-side select gate transistor of each of the memory holes is connected to one of a plurality of bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line ([0049]), the plurality of word lines includes a first neighboring word line is immediately adjacent to and disposed vertically above each of the selected ones of the plurality of word lines in the stack and a second neighboring word line is immediately adjacent to and disposed vertically below each of the selected ones of the plurality of word lines in the stack ([0057]: A number of word lines WL0-WL63 extend between the SGS and SGD transistors. WL0 is an edge word line which is adjacent to the source side (SS) of the block and WL63 is an edge word line which is adjacent to the drain side (DS) of the block), the plurality of word lines includes a top word line (Fig. 1B: word line WL3; [0049]) adjacent the drain-side select gate transistor (select gate, drain (SGD) transistor; [0057]) and a bottom word line (WL0) adjacent the source-side select gate transistor (select gate, source (SGS) transistor; [0057]),
Neither Mui, Park, nor Mui-2 explicitly disclose:
the at least one read pass voltage including a standard read pass voltage applied to unselected ones of the plurality of word lines other than the first neighboring word line, the second neighboring word line, the top word line and the bottom word line during the at least one read operation and a lower read pass voltage lower in magnitude than the standard read pass voltage and applied to the top word line and the bottom word line during the at least one read operation and a higher read pass voltage higher in magnitude than the lower read pass voltage and the standard read pass voltage and applied to the first neighboring word line and the second neighboring word line during the at least one read operation,
the at least one read parameter is at least one of a bit line voltage applied to the plurality of bit lines during the at least one read operation, the standard read pass voltage, a cell source voltage level applied to a source line during the at least one read operation, the lower read pass voltage, and the higher read pass voltage.
However, Lei teaches:
the at least one read pass voltage including a standard read pass voltage applied to unselected ones of the plurality of word lines other than the first neighboring word line, the second neighboring word line, the top word line and the bottom word line (referring to Fig. 12, per [0083]: In step 604, the standard read pass voltage, Vread, is applied to the middle memory cells, which are those memory cells between the ends of the NAND string that are not selected for reading) during the at least one read operation ([0023]: FIG. 12 is a flow chart describing one embodiment of a process for reading from non-volatile storage) and a lower read pass voltage lower in magnitude than the standard read pass voltage and applied to the top word line and the bottom word line during the at least one read operation ([0083]: the process of FIG. 12 proposes to use a lower pass voltage at the end of the NAND strings as compared to the middle of the NAND strings … In step 602, a lower read pass voltage, VreadL, is applied to memory cells at the ends of the NAND string) and a higher read pass voltage higher in magnitude than the lower read pass voltage and the standard read pass voltage and applied to the first neighboring word line and the second neighboring word line during the at least one read operation ([0083]: In step 606, a higher read pass voltage, VreadK, is applied to those memory cells of the NAND string that are neighbors to the selected memory cell),
the at least one read parameter is at least one of a bit line voltage applied to the plurality of bit lines during the at least one read operation, the standard read pass voltage (Vread), a cell source voltage level applied to a source line during the at least one read operation, the lower read pass voltage (VreadL), and the higher read pass voltage (VreadK).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lei to modified Mui wherein the at least one read pass voltage including a standard read pass voltage applied to unselected ones of the plurality of word lines other than the first neighboring word line, the second neighboring word line, the top word line and the bottom word line during the at least one read operation and a lower read pass voltage lower in magnitude than the standard read pass voltage and applied to the top word line and the bottom word line during the at least one read operation and a higher read pass voltage higher in magnitude than the lower read pass voltage and the standard read pass voltage and applied to the first neighboring word line and the second neighboring word line during the at least one read operation, the at least one read parameter is at least one of a bit line voltage applied to the plurality of bit lines during the at least one read operation, the standard read pass voltage, a cell source voltage level applied to a source line during the at least one read operation, the lower read pass voltage, and the higher read pass voltage in order to gain more margin to combat Read Disturb for memory cells connected to the end word lines by using a voltage on the dummy word line even higher than the higher read pass voltage (Lei, [0099]).
Regarding claim 10, Mui, Park, and Mui-2 together disclose the limitations of claim 9. Claim 10 recites substantially the same limitations as claim 3, and henceforth is rejected for the same reasons.
Regarding claim 16, Mui, Park, and Mui-2 together disclose the limitations of claim 15. Claim 16 recites substantially the same limitations as claims 3 and 10, and henceforth is rejected for the same reasons.
Claims 4, 11, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Mui (US Pub. 20150003162 A1), Park (US Pub. 20170235633 A1), and Mui-2 (US Pub. 20140211568 A1) as applied to claims 2, 9, and 15 above, and further in view of Hsu et al. (US Pat. 9484098 B1; “Hsu”).
Regarding claim 4, Mui, Park, and Mui-2 together disclose the limitations of claim 2. Neither Mui, Park, nor Mui-2 disclose:
further including predetermined values for the at least one read parameter at each of a plurality of predetermined ranges of the amount of the memory cells of the block that are programmed, and the control means is further configured to select and use the predetermined values for the at least one read parameter based on a comparison of the amount of the memory cells of the block that are programmed to the plurality of predetermined ranges.
However, Hsu teaches:
further including predetermined values for the at least one read parameter (col. 2, line 67 through col. 3, line 2: modified set of read parameters chosen from a number of predefined sets of read parameters) at each of a plurality of predetermined ranges of the amount of the memory cells of the block that are programmed (col. 2, lines 44-46: Indicators of numbers of memory cells programmed to each of the plurality of states may be maintained; col. 2, lines 57-59: identifying a first number of memory cells of the plurality of memory cells that were read as being in a first state using the default set of read parameters. Examiner concludes that there are defined sets of read parameters associated with the amounts of memory cells programmed), and the control means is further configured to select and use the predetermined values for the at least one read parameter based on a comparison of the amount of the memory cells of the memory block that are programmed to the plurality of predetermined ranges (col. 2, lines 63-67 through col. 3, lines 1-2: sending data read using the default set of read parameters to a memory controller; and if the difference between the first number and the expected number is greater than the limit, then rereading the plurality of memory cells using a modified set of read parameters, the modified set of read parameters chosen from a number of predefined sets of read parameters).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Hsu to modified Mui wherein the memory apparatus further includes predetermined values for the at least one read parameter at each of a plurality of predetermined ranges of the amount of the memory cells of the block that are programmed, and the control means is further configured to select and use the predetermined values for the at least one read parameter based on a comparison of the amount of the memory cells of the block that are programmed to the plurality of predetermined ranges in order to use information about changes to the number of memory cells in a memory state to more efficiently adjust read parameters, including the direction and magnitude of the adjustment (Hsu, col. 2, lines 1-11).
Regarding claim 11, Mui, Park, and Mui-2 together disclose the limitations of claim 9. Claim 11 recites substantially the same limitations as claim 4, and henceforth is rejected for the same reasons.
Regarding claim 17, Mui, Park, and Mui-2 together disclose the limitations of claim 15. Claim 17 recites substantially the same limitations as claims 4 and 11, and henceforth is rejected for the same reasons.
Claims 6, 13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Mui (US Pub. 20150003162 A1), Park (US Pub. 20170235633 A1), and further in view of Yang et al. (US Pub. 20200201546 A1; “Yang”).
Regarding claim 6, Mui and Park together disclose the limitations of claim 1.
Mui discloses a read operation, a control means, and a plurality of blocks.
Neither Mui nor Park discloses:
wherein the at least one read operation includes a plurality of read operations and the control means is further configured to adjust and utilize the at least one read parameter based on the amount of the memory cells of the memory block that are programmed for each of the plurality of read operations.
However, Yang teaches:
wherein the at least one read operation ([0090]) includes a plurality of read operations (per [0060], the read operation includes applying various voltages for each memory cell; further per [0060]: all of the bit lines of the memory block 302-1 can be simultaneously programmed or read) and the control means is further configured to adjust and utilize the at least one read parameter based on the amount of the memory cells of the memory block that are programmed for each of the plurality of read operations ([0081]; [0090]; also see [0008]: The controller is configured to read the first data from the first memory block … and perform a read improvement process … The controller is further configured to … perform cleanup operations; and per [0007], cleanup operations include adjusting a set of read parameters).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Yang to modified Mui wherein the at least one read operation includes a plurality of read operations and the control means is further configured to adjust and utilize the at least one read parameter based on the amount of the memory cells of the memory block that are programmed for each of the plurality of read operations in order to implement a read improvement program that takes the throughput time of the error correction engine into account by setting a throughput time threshold (Yang, [0022]-[0023]).
Regarding claim 13, Mui and Park together disclose the limitations of claim 8. Claim 13 recites substantially the same limitations as claim 6, and henceforth is rejected for the same reasons.
Regarding claim 19, Mui and Park together disclose the limitations of claim 14. Claim 19 recites substantially the same limitations as claims 6 and 13, and henceforth is rejected for the same reasons.
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mui (US Pub. 20150003162 A1) in view of Park (US Pub. 20170235633 A1), and further in view of K et al. (US Pub. 20180350446 A1; “K”).
Regarding claim 7, Mui and Park together disclose the limitations of claim 1. Neither Mui nor Park disclose:
further including a temperature detection circuit configured to measure a temperature of the memory apparatus, wherein the memory holes are each connected to one of a plurality of bit lines, the at least one read parameter includes a bit line voltage temperature compensation coefficient for modifying a bit line voltage applied to the plurality of bit lines during the at least one read operation, and the control means is further configured to:
determine the temperature of the memory apparatus; and
adjust and utilize the bit line voltage temperature compensation coefficient based on the temperature of the memory apparatus.
However, K teaches:
further including a temperature detection circuit configured to measure a temperature of the memory apparatus ([0174]: In one embodiment, the system includes a temperature sensor. The temperature sensor detects a temperature when programming), wherein the memory holes ([0065]: in a three dimensional NAND memory array, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels; also see [0082] and Fig. 4B) are each connected to one of a plurality of bit lines ([0083]: Each of the circles representing vertical columns has an “x” to indicate its connection to one bit line), the at least one read parameter includes a bit line voltage temperature compensation coefficient for modifying a bit line voltage applied to the plurality of bit lines during the at least one read operation ([0174]: The temperature sensor … stores an indication of the programmed temperature. The indication can be stored as one or more bits within the memory it describes, or can be stored in another location (e.g., in a table). When reading, the temperature sensor detects the current temperature. The test circuit can then access the current temperature and the programmed temperature to use in the test process), and the control means is further configured to:
determine the temperature of the memory apparatus ([0174]; per [0134]-[0135] and [0141], the temperature refers to the temperature of the memory cells); and
adjust and utilize the bit line voltage temperature compensation coefficient based on the temperature of the memory apparatus ([0165]: The table can be used at step 712 of process 700 to read a selected page with temperature compensated read levels. The table can be accessed to determine the temperature compensated read levels by providing the indicated adjustment to the default read level for each state; [0166]: the adjustments in FIG. 15 can be used to provide adjusted read voltages for sensing at the various states. A similar table may be used to provide adjustments to other sense parameters. For example, a table may include adjustments to sense times, bit line voltages, etc. for the different states. The adjustments to the sense parameters result in sensing at an adjusted reference level. Examiner concludes that the adjustments to bit line voltages based on temperature compensated read levels are analogous to adjustments to the bit line temperature compensation coefficient).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of K to modified Mui wherein the memory apparatus further includes a temperature detection circuit configured to measure a temperature of the memory apparatus, wherein the memory holes are each connected to one of a plurality of bit lines, the at least one read parameter includes a bit line voltage temperature compensation coefficient for modifying a bit line voltage applied to the plurality of bit lines during the at least one read operation, and the control means is further configured to: determine the temperature of the memory apparatus; and adjust and utilize the bit line voltage temperature compensation coefficient based on the temperature of the memory apparatus in order to implement a test process to determine whether the memory has experienced read disturb, and therefore requires maintenance, or whether the memory is experiencing cross-temperature effects (K, [0044]).
Regarding claim 20, Mui and Park together disclose the limitations of claim 14. Claim 20 recites substantially the same limitations as claim 7, and henceforth is rejected for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lien et al. (US Pub. 20210375349 A1) and Lien et al. (US Pub. 20210375371 A1): para. [0051] and Fig. 6 are relevant to claims 1, 8, and 14.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.A./Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824
4/16/2026
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