DETAILED ACTION
This action is responsive to communication filed 01/09/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 11-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 01/09/2026.
Applicant’s election of Species 1 in the reply filed on 01/09/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/04/2023 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sugiyama (US 20020149120 A1).
Regarding claim 1, Sugiyama (see, e.g., FIG. 1) discloses a semiconductor device comprising:
a substrate (13)
including an element region (10)
and a scribe lane region defining and surrounding the element region; (14)
and one or more test circuits arranged on the substrate (12 and 15) and including one or more test elements for characteristic evaluation (12) and one or more test pads for applying a test signal for testing the one or more test elements, (15)
wherein all of the one or more test pads are spaced apart from the element region in a horizontal direction.
Regarding claim 2, Sugiyama (see, e.g., FIG. 1) discloses the semiconductor device of claim 1,
wherein the one or more test elements are arranged in the element region.
Regarding claim 3, Sugiyama (see, e.g., FIG. 1) discloses the semiconductor device of claim 1,
wherein at least a first test pad (15) of the one or more test pads is electrically connected to a first test element (12) of the one or more test elements,
the first test element formed in the element region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s)
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama (US 20020149120 A1) as applied to claim 3 above, and further in view of Maruyama (US 20080251788 A1).
Regarding claim 4, Sugiyama (see, e.g., FIG. 1) discloses the semiconductor device of claim 3,
wherein the first test pad (15) is electrically connected to the first test element (12)
and to a second test element formed in the scribe lane region.
Maruyama (see, e.g., FIG. 6) discloses:
wherein the first test pad (16) is electrically connected to the first test element (13A)
and to a second test element (24) formed in the scribe lane region (18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sugiyama with Maruyama in order to prevent one bad chip from damaging another during a burn-in test while not changing the operating condition of the device (paragraphs [0111]-[0114]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama (US 20020149120 A1) as applied to claim 1 above, and further in view of Tsai et al. (US 20080246031).
Regarding claim 5, Sugiyama (see, e.g., annotated FIG. 1 below) discloses the semiconductor device of claim 1,
wherein each of the one or more test pads is arranged to have a first horizontal direction width in a first horizontal direction (see annotated Fig. 1 below: “first width in first horizontal direction”)
that differs from a second horizontal direction width in a second horizontal direction (see annotated Fig. 1 below: “second width in second horizontal direction”)
Sugiyama fails to disclose that the first horizontal direction width and the second horizontal direction width differ.
Tsai et al. (see, e.g., FIG. 4) discloses:
wherein each of the one or more test pads (32) is arranged to have a first horizontal direction width in a first horizontal direction (D)
that differs (paragraph [0023]: “about 70 μm” and “about 50 μm”) from a second horizontal direction width in a second horizontal direction (W).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sugiyama with Tsai et al. in order to optimize the available area of the probing process and sawing process (paragraph [0024]).
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Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama (US 20020149120 A1) in view of Tsai et al. (US 20080246031) as applied to claim 5 above, and further in view of Kaltalioglu et al. (US 8748295 B2).
Regarding claim 6 Sugiyama in view of Tsai et al. fails to disclose the semiconductor device of claim 5,
wherein a relatively longer horizontal width between the first horizontal direction width and the second horizontal direction width of at least one test pad of the one or more test pads ranges from about 20 micrometers to about 60 micrometers.
Kaltalioglu et al. (see, e.g., FIG. 5) discloses:
wherein a relatively longer horizontal width (d-3) between the first horizontal direction width and the second horizontal direction width of at least one test pad (242e) of the one or more test pads ranges from about 20 micrometers to about 60 micrometers (column 8, lines 1-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sugiyama in view of Tsai et al. with Kaltalioglu et al. for the purpose of optimizing the reduction of the width of the scribe lane region as stated by Tsai et al. (paragraph [0024]) while still allowing the pad to be probed, which is shown to be at 40 micrometers in Kaltalioglu et al. (column 8, lines 18-22).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama (US 20020149120 A1) as applied to claim 1 above, and further in view of Kato (US 20120313094 A1).
Regarding claim 7, Sugiyama fails to disclose the semiconductor device of claim 1, further comprising:
a guard ring arranged along an edge of the element region inside the element region.
Kato (see, e.g., FIG. 2A) discloses:
a guard ring (5a) arranged along an edge of the element region (2a) inside the element region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sugiyama with Kato for the purpose grounding the Test elements so as to not harm an element of the semiconductor chip during a testing process (paragraph [0049]).
Claims 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. (US 20210217735 A1) in view of Sugiyama (US 20020149120 A1).
Regarding claim 22, Seo et al. (see, e.g., FIG. 10 and Annotated FIG. 20 below) discloses A semiconductor package (Fig. 10: 2b) comprising:
an interposer (Fig. 10: 610);
a first semiconductor chip (Fig. 10: C1) arranged on the interposer
and including an element region (see annotated Fig. 20 below: “element region”) and a scribe lane region (see annotated Fig. 20 below: “scribe lane region”) defining and surrounding the element region;
a plurality of second semiconductor chips (Fig. 10: C2, C3, and C4) sequentially stacked on the first semiconductor chip,
a molding layer (Fig. 10: 162) surrounding the plurality of second semiconductor chips on the first semiconductor chip;
and one or more test element groups arranged on the first semiconductor chip
and including one or more test elements for characteristic evaluation
and one or more test pads for applying a test signal for testing the one or more test elements,
wherein the one or more test pads are spaced apart from the element region in a horizontal direction,
and wherein at least a first test pad of the one or more test pads is electrically connected to a first test element of the one or more test elements,
the first test element formed in the element region.
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Sugiyama (see, e.g., FIG. 1) discloses:
one or more test element groups (12 and 15) arranged on the first semiconductor chip
and including one or more test elements for characteristic evaluation (12)
and one or more test pads for applying a test signal for testing the one or more test elements (15),
wherein the one or more test pads are spaced apart from the element region (10) in a horizontal direction (test pads 15 are located in scribe lane region 14),
and wherein at least a first test pad of the one or more test pads is electrically connected to a first test element of the one or more test elements,
the first test element formed in the element region (first test elements 12 formed in element region 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Seo et al. with Sugiyama for providing a method of analyzing the for defects in the first semiconductor chip without substantially increasing the dimensions of the chip (paragraph [0008]).
Regarding claim 23 Seo et al. (see, e.g., Annotated FIG. 20 above) discloses the semiconductor package of claim 22, wherein, from a plan perspective,
the one or more test element groups do not overlap the plurality of second semiconductor chips in a vertical direction (as the test element group added by Sugiyama in the modification made in the rejection of claim 22 above specifies that the test pads are placed in the scribe lane region (see, e.g., Sugiyama FIG. 1) then the equivalent location in Seo et al. would be “scribe lane region” in the annotated Fig. 20 above, in which case the only overlap in the vertical direction would be molding layer 162).
Regarding claim 24, Seo et al. discloses the semiconductor package of claim 22, wherein
the one or more test elements are arranged in the element region of the first semiconductor chip and are not electrically connected to the plurality of second semiconductor chips or the interposer (the modification made by Sugiyama in the rejection of claim 22 above already specified that the one or more test elements 12 are arranged in the element region 10, and that the test elements are specifically for monitoring for defects in the chip which requires the elements to only be electrically connected to the test pads).
Claims 25 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. (US 20210217735 A1) in view of Sugiyama (US 20020149120 A1) as applied to claim 22 above, and further in view of Nyhus et al. (US 11545449 B2).
Regarding claim 25 Seo et al. in view of Sugiyama fails to disclose the semiconductor package of claim 22, further comprising:
a guard ring arranged along an edge of the first semiconductor chip, wherein:
the one or more test elements and the guard ring are spaced apart from each other in a horizontal direction.
Nyhus et al. (see, e.g., FIG. 1) discloses:
a guard ring (122) arranged along an edge of the first semiconductor chip (100), wherein:
the one or more test elements and the guard ring are spaced apart from each other in a horizontal direction (the guard rings 122 are spaced apart from the active region 110 which is the equivalent to the element region in which the one or more test elements are placed in Seo et al. in view of Sugiyama).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Seo et al. in view of Sugiyama with Nyhus et al. for reducing mechanical stress and electrically isolating the first semiconductor chip (column 4, lines 4-8).
Regarding claim 26 Seo et al. in view of Sugiyama fails to disclose the semiconductor package of claim 25, wherein
the guard ring is arranged to have a constant vertical height.
Nyhus et al. (see, e.g., FIG. 1) discloses wherein:
the guard ring is arranged to have a constant vertical height (the guard rings 122 of the sound groups 130 are described as being a closed loop without breaks having a rectangular shape free of defects (column 7 lines 31-52) where free from defects includes disclinations in the structure (column 3 lines 1-2)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Seo et al. in view of Sugiyama with Nyhus et al. for improving the effectiveness of the guard rings (column 4 lines 54-57).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AIDAN D BANKLER whose telephone number is (571)272-0883. The examiner can normally be reached Monday through Thursday 7:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AIDAN D BANKLER/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 21, 2026
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