DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 10 is objected to because of the following informalities: “A gate line” in line 2 should be corrected to “a gate line” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 6-7, 11-13 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (U.S. Publication No. 2022/0093448 A1; hereinafter Yu).
With respect to claim 1, Yu discloses an integrated circuit device comprising: a substrate [330] having a backside surface; a pair of fin-type active regions [230] protruding from the substrate and defining a trench region in the substrate on an opposite side of the backside surface (See Figure 10A), wherein the pair of fin-type active regions extend in a first lateral direction; a pair of source/drain regions [210] disposed, one-by-one, on the pair of fin-type active regions, respectively; a device isolation film [140/225] covering a sidewall of each of the pair of fin-type active regions and disposed in the trench region; a via power rail [325] disposed between the pair of fin-type active regions and between the pair of source/drain regions (see Figure 112; four sets of source/drain regions, the via power rail in the middle of outer [210] regions are between the pair of source/drain regions), wherein the via power rail passes through the device isolation film in a vertical direction (See Figure 16B); a backside power rail [375] passing through the substrate in the vertical direction and disposed at a position overlapping the via power rail in the vertical direction (See Figure 20B; ¶[0073]), wherein the backside power rail is connected to the via power rail; and an air spacer [385,340,360,357] disposed between the substrate and the backside power rail (see ¶[0073]; “the seal cap 385, the first spacer layer 340, and the second spacer layer 360 together define the air gap 357”).
With respect to claim 2, Yu discloses wherein the substrate and the device isolation film are exposed by the air spacer (See Figure 23B).
With respect to claim 4, Yu discloses an insulating liner [305] disposed between the backside power rail and the air spacer, wherein the insulating liner is in contact with the backside power rail (see Figure 23B).
With respect to claim 6, Yu discloses wherein the backside power rail is spaced apart from the pair of source/drain regions with the device isolation film disposed therebetween (See Figure 23B).
With respect to claim 7, Yu discloses wherein the air spacer covers both sidewalls of the backside power rail in a second lateral direction, wherein the second lateral direction intersects with the first lateral direction, the backside power rail is spaced apart from the pair of fin-type active regions with the air spacer and the substrate disposed therebetween (See Figure 23B).
With respect to claim 11, Yu discloses an integrated circuit device comprising: a substrate [330] having a backside surface; a plurality of fin-type active regions [230] protruding from the substrate and defining a plurality of trench regions in the substrate on an opposite side of the backside surface, wherein the plurality of fin-type active regions extend in a first lateral direction (see Figure 10A and 23A); a plurality of source/drain regions [210] disposed on the plurality of fin-type active regions, respectively; a device isolation film [140/225] disposed on a sidewall of each of the plurality of fin-type active regions in the plurality of trench regions; a via power rail [325] spaced apart from the plurality of fin-type active regions and the plurality of source/drain regions (see Figure 112; four sets of source/drain regions, the via power rail in the middle of outer [210] regions are between the pair of source/drain regions), wherein the via power rail passes through the device isolation film in a vertical direction; and a backside power structure passing the substrate in the vertical direction and disposed at a position overlapping the via power rail in the vertical direction (See Figure 20B; ¶[0073]), wherein the backside power structure comprises: a backside power rail [375] passing through the substrate in the vertical direction and disposed at a position overlapping the via power rail in the vertical direction, wherein the backside power rail is connected to the via power rail; and an air spacer [357] disposed between the substrate and the backside power rail (see ¶[0073]).
With respect to claim 12, Yu discloses wherein the backside power structure further comprises an insulating liner [305] disposed between the backside power rail and the air spacer, and a width of the air spacer in a second lateral direction is defined by the substrate and the insulating liner, wherein the second lateral direction intersects with the first lateral direction (See Figure 23B).
With respect to claim 13, Yu discloses wherein a width of the air spacer in a second lateral direction is defined by the substrate and the backside power rail, wherein the second lateral direction intersects with the first lateral direction (See Figures 23A-B).
With respect to claim 16, Yu discloses wherein the backside power structure is apart from the plurality of source/drain regions with the device isolation film disposed therebetween and is spaced apart from the plurality of fin-type active regions with the substrate disposed therebetween (See Figure 23A-B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5, 8-10, 15, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Xie et al. (U.S. Publication No. 2024/0204067 A1; hereinafter Xie)
With respect to claim 5, Yu discloses wherein the substrate has a through region that accommodates the air spacer and the backside power rail, the through region has a pair of inner sidewalls that are exposed by the air spacer in a second lateral direction, wherein the second lateral direction intersects with the first lateral direction (see Figure 23A-B), but fails to disclose a distance between the pair of inner sidewalls in the second lateral direction gradually reduces toward the backside surface of the substrate.
In the same field of endeavor, Xie teaches a backside power rail [2010] wherein a distance between the pair of inner sidewalls in the second lateral direction gradually reduces toward the backside surface of the substrate (See Figure 21B). Implementation of a tapered angle of the backside power rails as taught by Xie allows for simplification of the manufacturing process and increases a contact area between the via and the backside power rails for improved device performance and reliability (See Xie ¶[0069]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 8, Yu discloses wherein the backside power rail has a width that gradually reduces toward the backside surface of the substrate in a second lateral direction, wherein the second lateral direction intersects with the first lateral direction.
In the same field of endeavor, Xie teaches wherein a backside power rail [2010] has a width that gradually reduces toward the backside surface of the substrate in a second lateral direction, wherein the second lateral direction intersects with the first lateral direction (See Figure 21B). Implementation of a tapered angle of the backside power rails as taught by Xie allows for simplification of the manufacturing process and increases a contact area between the via and the backside power rails for improved device performance and reliability (See Xie ¶[0069]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 9, Yu discloses a gate line [230] extending in a second lateral direction and disposed on the pair of fin-type active regions, wherein the second lateral direction intersects with the first lateral direction; but fails to disclose a pair of nanosheet stacks disposed between the pair of fin-type active regions and the gate line, wherein each nanosheet stack comprises at least one nanosheet that is at least partially surrounded by the gate line, wherein the via power rail passes through the gate line in the vertical direction and between the pair of nanosheet stacks, however does disclose channel layers in sheet orientations [124] wherein the via power rail passes through the gate line in the vertical direction and between the pair of channel layers (see Figure 23A). In the same field of endeavor, Xie teaches a pair of nanosheet stacks [10] disposed between the pair of fin-type active regions and the gate line, wherein each nanosheet stack comprises at least one nanosheet [112] that is at least partially surrounded by the gate line [1310] (see Figure 13C and ¶[0080]).
Both Yu and Xie produce semiconductor channel structures in thin layers (i.e., nanosheets). Implementation of nanosheet structures as taught by Xie produces channel layers within a gate all around FET orientation, thereby improving device capability within a smaller footprint (See ¶[0087]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 10, Yu discloses A gate line [230] extending in a second lateral direction and disposed on the pair of fin-type active regions, wherein the second lateral direction intersects with the first lateral direction; and a pair of semiconductor channel layers [124] disposed between the pair of fin-type active regions and the gate line, wherein each semiconductor channel layer comprises at least channel layer that is at least partially surrounded by the gate line, wherein the air spacer overlaps the gate line in the vertical direction (see Figure 23A).
Yu fails to disclose wherein the semiconductor channel layers are nanosheet stacks wherein each nano sheet stack comprises at least one nanosheet. In the same field of endeavor, Xie teaches wherein the semiconductor channel layers are nanosheet stacks [10] wherein each nano sheet stack comprises at least one nanosheet [112] (see Figure 13C and ¶[0080]).
Both Yu and Xie produce semiconductor channel structures in thin layers (i.e., nanosheets). Implementation of nanosheet structures as taught by Xie produces channel layers within a gate all around FET orientation, thereby improving device capability within a smaller footprint (See ¶[0087]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 15, Yu fails to disclose wherein the substrate has a through region that accommodates the backside power structure, and the through region has a tapered shape.
In the same field of endeavor, Xie teaches wherein the substrate has a through region that accommodates the backside power structure [2010], and the through region has a tapered shape (See Figure 21B). Implementation of a tapered angle of the backside power rails as taught by Xie allows for simplification of the manufacturing process and increases a contact area between the via and the backside power rails for improved device performance and reliability (See Xie ¶[0069]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 17, Yu discloses a gate line [230] extending in a second lateral direction and disposed on the plurality of fin-type active regions, wherein the second lateral direction intersects with the first lateral direction; and a plurality of semiconductor channel stacks disposed between the plurality of fin-type active regions and the gate line (See Figure 23A), wherein each stack comprises at least semiconductor channel [124] at least partially surrounded by the gate line, wherein the via power rail passes through the gate line in the vertical direction and between a pair of adjacent semiconductor channel stacks, from among the plurality of semiconductor channel stacks, and the backside power structure is spaced apart from the plurality of semiconductor channel stacks with the device isolation film disposed therebetween (See Figure 23A-23B). Yu fails to disclose the plurality of semiconductor channel stacks are a plurality of nanosheet stacks,
In the same field of endeavor, Xie teaches wherein the plurality of semiconductor channel stacks are a plurality of nanosheet stacks, wherein each nanosheet stack comprises at least a nanosheet [112] at least partially surrounded by a gate line [1310] (see Figure 13C and ¶[0080]).
Both Yu and Xie produce semiconductor channel structures in thin layers (i.e., nanosheets). Implementation of nanosheet structures as taught by Xie produces channel layers within a gate all around FET orientation, thereby improving device capability within a smaller footprint (See ¶[0087]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 18, Yu discloses an integrated circuit device comprising: a substrate [330] having a backside surface; a fin-type active region [230] protruding from the substrate to and defining a trench region in the substrate on an opposite side of the backside surface (See Figure 10A and 23A); at least one semiconductor layer [124] disposed on the fin-type active region, wherein the at least one semiconductor layer is spaced apart from a fin top surface of the fin-type active region; a gate line [230] at least partially surrounding the at least one semiconductor layer and disposed on the fin-type active region; a source/drain region [210] adjacent to the gate line and disposed on the fin-type active region, wherein the source/drain region is in contact with the at least one nanosheet; a device isolation film [140/225] covering a sidewall of the fin-type active region and disposed in the trench region; a via power rail [325] spaced apart from each of the fin-type active region, the source/drain region, and the gate line, wherein the via power rail passes through the gate line in a vertical direction; and a backside power structure [375] passing through the substrate in the vertical direction and disposed at a position overlapping the via power rail in the vertical direction (See Figure 20B; ¶[0073]), wherein the backside power structure comprises: a backside power rail [375] passing through the substrate in the vertical direction and disposed at a position overlapping the via power rail in the vertical direction, wherein the backside power rail is connected to the via power rail; and an air spacer [357] disposed between the substrate and the backside power rail (see ¶[0073]).
Yu fails to explicitly disclose wherein the at least one semiconductor layer is at least one nanosheet disposed on the fin-type active region, wherein the at least one nanosheet is spaced apart from a fin top surface of the fin-type active region; the gate line at least partially surrounding the at least one nanosheet and disposed on the fin-type active region. In the same field of endeavor, Xie teaches wherein the at least one semiconductor layer is at least one nanosheet [112] disposed on the fin-type active region, wherein the at least one nanosheet is spaced apart from a fin top surface of the fin-type active region; the gate line [1310] at least partially surrounding the at least one nanosheet and disposed on the fin-type active region (see Figure 13C and ¶[0080]). Both Yu and Xie produce semiconductor channel structures in thin layers (i.e., nanosheets). Implementation of nanosheet structures as taught by Xie produces channel layers within a gate all around FET orientation, thereby improving device capability within a smaller footprint (See ¶[0087]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 19, the combination of Yu and Xie discloses wherein the backside power structure further comprises an insulating liner [305] disposed between the backside power rail and the air spacer, and the insulating liner comprises a silicon oxide film, a silicon nitride film, or a combination thereof (See Yu ¶[0070]).
Allowable Subject Matter
Claims 3, 14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claims 3, 14 and 20, none of the prior art teaches or suggests, alone or in combination, one char particle dispersed in the air spacer, wherein the at least one char particle comprises about 70% to about 90% by weight of carbon (C) and about 10% to about 30% by weight of hydrogen (H), based on a total weight of the at least one char particle.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818