Prosecution Insights
Last updated: May 29, 2026
Application No. 18/230,756

SEMICONDUCTOR DEVICE AND METHOD OF MAKING

Final Rejection §102§103
Filed
Aug 07, 2023
Priority
Apr 13, 2023 — provisional 63/459,098
Examiner
BOATMAN, CASEY PAUL
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Limited
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
8m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
56 granted / 68 resolved
+14.4% vs TC avg
Moderate +14% lift
Without
With
+13.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
14 currently pending
Career history
92
Total Applications
across all art units

Statute-Specific Performance

§103
81.9%
+41.9% vs TC avg
§102
10.9%
-29.1% vs TC avg
§112
6.8%
-33.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 68 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Amendment to claims 1, 8, 9, 10, 11 and 13 submitted on March 6, 2026 are acknowledged and have since been entered. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-4, 6-16 and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shimizu (US 20240072191 A1) Regarding Claim 1, Shimizu teaches a semiconductor device (104, shown Fig. 7) comprising: a substrate (21) comprising first dopants (p-type dopants) having a first conductivity type (p-type); a first epitaxial layer (14) over the substrate and comprising second dopants (p-type dopants) having the first conductivity type; a second epitaxial layer (15) over the first epitaxial layer and comprising third dopants (p-type dopants) having the first conductivity type; and a photodiode (10, see [0035]) in at least one of the first epitaxial layer or the second epitaxial layer (shown Fig. 7), wherein the photodiode comprises: a first doped region (13) having a second conductivity type (n-type) different than the first conductivity type; and a second doped region (12), over the first doped region, having the first conductivity type (shown Fig. 7), wherein a dopant concentration of dopants within the second doped region changes from a top surface of the second doped region to a bottom surface of the second doped region (see Fig. 8 which shows a concentration between top surface 12u and bottom surface 12d changing). Regarding Claim 2, Shimizu teaches the semiconductor device of claim 1, wherein: a first thickness of the first epitaxial layer is less than a second thickness of the second epitaxial layer (shown Fig. 7). Regarding Claim 3, Shimizu teaches the semiconductor device of claim 1, wherein: a first concentration (see [0059], see also Fig. 7 showing a p+ region) of the first dopants is greater than a second concentration (shown as a p-region) of the second dopants. Regarding Claim 4, Shimizu teaches the semiconductor device of claim 1, wherein the photodiode comprises: a p-n junction between the first doped region and the second doped region (shown Fig. 7). Regarding Claim 6, Shimizu teaches the semiconductor device of claim 1, comprising: a p-n junction between the first doped region and a portion (15e) of the second epitaxial layer underlying the first doped region (shown Fig. 7, see also [0115]). Regarding Claim 7, Shimizu teaches the semiconductor device of claim 1 (see also embodiment 103 of Fig. 5), comprising: a p-n junction between the first doped region and a portion of the first epitaxial layer (see embodiment 103 of Fig. 5 further teaching all limitations of claim 1) underlying the first doped region (shown Fig. 5). Regarding Claim 8, Shimizu teaches a method of forming a semiconductor device (104, shown Fig. 7), comprising: forming a first epitaxial layer (14) over a substrate (21); forming a second epitaxial layer (15) over the first epitaxial layer; and forming a photodiode (10) in at least one of the first epitaxial layer or the second epitaxial layer (shown Fig. 7) wherein: the photodiode comprises a first doped region (13) having a first conductivity type (n-type); and the first doped region comprises a first sub-region (interpreted as a region between a lower surface 13d and the middle of region 13) having a first concentration of dopants (shown Fig. 8) and a second sub-region (interpreted as a region between the middle of region 13 and upper surface 13u) having a second concentration of dopants different than the first concentration of dopants (shown Fig. 8) interfacing with the first sub-region (see also [0105] which describes region 13 being formed by doping during epitaxial growth, wherein an interface may be defined between any two epitaxial layers). Regarding Claim 9, Shimizu teaches the method of claim 8, wherein: the substrate comprises first dopants (see [0059]) having a second conductivity type (p-type) different than the first conductivity type; forming the first epitaxial layer comprises forming the first epitaxial layer to comprise second dopants having the second conductivity type (shown Fig. 7); forming the second epitaxial layer comprises forming the second epitaxial layer to comprise third dopants having the first conductivity type (shown Fig. 7); and forming the photodiode comprises: forming the first doped region (13) in the second epitaxial layer; and forming a second doped region (12) having the second conductivity type in the second epitaxial layer, wherein: the second doped region overlies the first doped region (shown Fig. 7); and forming the first doped region forms a p-n junction between the first sub-region of the first doped region and a portion, of at least one of the first epitaxial layer or the second epitaxial layer (shown Fig. 7), underlying the first doped region. Regarding Claim 10, Shimizu teaches the method of claim 8, wherein: the substrate comprises first dopants (see [0059]) having a second conductivity type (p-type) different than the first conductivity type; forming the first epitaxial layer comprises forming the first epitaxial layer to comprise second dopants having the second conductivity type (shown Fig. 7); forming the second epitaxial layer comprises forming the second epitaxial layer to comprise third dopants having the second conductivity type (shown Fig. 7); and forming the photodiode comprises: forming the first doped region (13) in the first epitaxial layer; and forming a second doped region (12) having the second conductivity type in the second epitaxial layer, wherein: the second doped region overlies the first doped region (shown Fig. 7); and forming the first doped region forms a p-n junction between the first sub-region of the first doped region and a portion of the second epitaxial layer underlying the first doped region (shown Fig. 7). Regarding Claim 11, Shimizu teaches the method of claim 8, wherein: the substrate comprises a third concentration (p+, see also [0059]) of first dopants having a second conductivity type different than the first conductivity type; forming the first epitaxial layer comprises forming the first epitaxial layer to comprise a fourth concentration (p, shown Fig. 7) of second dopants having the second conductivity type; and forming the second epitaxial layer comprises forming the second epitaxial layer to comprise a fifth concentration (p-, shown Fig. 7) of third dopants having the second conductivity type, wherein the fourth concentration is greater than the fifth concentration (see also Fig. 8). Regarding Claim 12, Shimizu teaches the method of claim 8, wherein forming the first epitaxial layer comprises: forming the first epitaxial layer to have a first thickness that is less than a second thickness of the second epitaxial layer (shown Fig. 7). Regarding Claim 13, Shimizu teaches a semiconductor device (104, shown Fig. 7), comprising: a substrate (21); a first epitaxial layer (14) over the substrate; a second epitaxial layer (15) over the first epitaxial layer; and a photodiode (10) in at least one of the first epitaxial layer or the second epitaxial layer (shown Fig. 7), wherein the photodiode comprises: a first doped region (13) wherein a dopant concentration of dopants within the first doped region changes from a top surface (13u) of the first doped region to a bottom surface (13d) of the first doped region (shown Fig. 8); and a second doped region (12) over the first doped region (shown Fig. 7). Regarding Claim 14, Shimizu teaches the semiconductor device of claim 13, wherein: a first thickness of the first epitaxial layer is less than a second thickness of the second epitaxial layer (shown Fig. 7). Regarding Claim 15, Shimizu teaches the semiconductor device of claim 13, wherein: a first concentration (p) of first dopants in the first epitaxial layer is greater than a second concentration (p-) of second dopants in the second epitaxial layer (shown Fig. 7). Regarding Claim 16, Shimizu teaches the semiconductor device of claim 13, wherein the photodiode comprises: a p-n junction between the first doped region and the second doped region (shown Fig. 7). Regarding Claim 18, Shimizu teaches the semiconductor device of claim 13, comprising: a p-n junction between the first doped region and a portion, of at least one of the first epitaxial layer or the second epitaxial layer (shown Fig. 7), underlying the first doped region. Regarding Claim 19, Shimizu teaches the semiconductor device of claim 13, wherein: the substrate comprises p-type dopants (see [0059] and Fig. 7); the first epitaxial layer comprises p-type dopants (shown Fig. 7); the second epitaxial layer comprises p-type dopants (shown Fig. 7); the dopants of the first doped region are n-type dopants (shown Fig. 7); and the second doped region comprises p-type dopants (shown Fig. 7). Regarding Claim 20, Shimizu teaches the semiconductor device of claim 19, wherein: a first concentration (p) of the p-type dopants in the first epitaxial layer is greater than a second concentration (p-) of the p-type dopants in the second epitaxial layer. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 20240072191 A1) in further view of Tkachuk (US 20130037854 A1). Regarding Claim 5, Shimizu teaches the semiconductor device of claim 1, wherein the photodiode comprises a p-n junction formed between the first doped region and the second doped region. Shimizu does not explicitly teach an intrinsic region between the first doped region and the second doped region. However, implementing an intrinsic region between the first doped region (n-type) and second doped region (p-type) resulting in a p-i-n structure in photodetection devices is known in the art to reduce dark current and improve signal-to-noise ratio compared to p-n structures (see also Tkachuk: [0053]). Thus, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the p-n heterostructures of the photodiode of Shimizu to further comprise an intrinsic region between the first doped region and the second doped region as suggested by Tkachuk as this would reduce dark current and improve signal-to-noise ratio (see Tkachuk: [0053]). Regarding Claim 17, Shimizu teaches the semiconductor device of claim 13, wherein the photodiode comprises a p-n junction formed between the first doped region and the second doped region. Shimizu does not explicitly teach an intrinsic region between the first doped region and the second doped region. However, implementing an intrinsic region between the first doped region (n-type) and second doped region (p-type) resulting in a p-i-n structure in photodetection devices is known in the art to reduce dark current and improve signal-to-noise ratio compared to p-n structures (see also Tkachuk: [0053]). Thus, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the p-n heterostructures of the photodiode of Shimizu to further comprise an intrinsic region between the first doped region and the second doped region as suggested by Tkachuk as this would reduce dark current and improve signal-to-noise ratio (see Tkachuk: [0053]). Response to Arguments Applicant's arguments filed March 6, 2026 have been fully considered but they are not persuasive. Applicant argues on page 1 that Shimizu is silent with respect to a dopant concentration of dopants within the second semiconductor region 12 changing from a top surface of the second semiconductor region to a bottom surface of the second semiconductor region as cited in the amendment of claim 1 and similar arguments regarding the concentration profile of the first doped region 13 regarding claims 8 and 13 on pages 2 and 3 respectively. Examiner respectfully disagrees, and notes that Fig. 8 of Shimizu clearly shows impurity concentrations having varying profiles in both the first doped region and second doped region (see also paragraphs [0116-0119] of Shimizu). As such, the claims stand rejected as detailed above. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY PAUL BOATMAN whose telephone number is (703)756-4778. The examiner can normally be reached M-F 7:30 AM - 5:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.P.B./Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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Prosecution Timeline

Aug 07, 2023
Application Filed
Nov 13, 2023
Response after Non-Final Action
Dec 04, 2025
Non-Final Rejection mailed — §102, §103
Mar 06, 2026
Response Filed
May 07, 2026
Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
96%
With Interview (+13.7%)
3y 6m (~8m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 68 resolved cases by this examiner. Grant probability derived from career allowance rate.

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