DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 08/07/2023 has been considered and
placed in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-7 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (U.S. 10,263,759).
Regarding claims 1 and 12, Wang et al. (hereinafter, Ref~759) discloses (please see Figs. 2-7 and related text for details) a method, comprising:
determining (during a calibration phase as described e.g., in the abstract) a first offset calibration of a first differential pair (770e/770f of Fig. 7 can be read as the claimed pair OR at least it is functionally equivalent to it) of a circuit (e.g., see circuit from Fig. 4), the first differential pair comprises a first transistor (e.g., 770e of Fig. 7) and a second transistor (770f of Fig. 7);
determining (during said calibration phase as described, for instance, in paragraph [0003]) a second offset calibration of a second differential pair (770c/770d of Fig. 7 can be read as the claimed pair OR at least it is functionally equivalent to it) of the circuit, the second differential pair comprises a third transistor (770c of Fig. 7) and a fourth transistor (770d of Fig. 7); and
based on the first offset calibration and the second offset calibration, determining a third offset calibration of a common mode, wherein the common mode comprises a combination of the first differential pair and the second differential pair (Ref~759 teaches that the peak detector may provide a common mode voltage associated with the first and second differential outputs as broadly described in paragraph [0012]. In addition, Ref~759 further teaches that the offset of the peak detector output voltage and the offset of the comparator input voltage offset are reduced as described in paragraph [0034], thus obviating the claimed feature. In other words, each pair may obviously need to be calibrated depending on custom specifications), meeting claims 1 and 12.
Regarding claim 5, Ref~759 discloses the method of claim 1, wherein a bias current (706b of Fig. 7 can be read as the claimed bias current) is shared by the first differential pair and the second differential pair, meeting claim 5.
Regarding claim 6, Ref~759 discloses the method of claim 1, wherein the first differential pair is configured to receive a reference level voltage (disposed at gate of 770e/7470f), and wherein the second differential pair is configured to receive a signal (in/ip or on/op of Fig. 7), meeting claim 6.
Regarding claim 7, Ref~759 discloses the method of claim 6, wherein the reference level voltage is a DC voltage, and wherein the signal is an alternating voltage as seen from Fig. 7, meeting claim 7.
Regarding claim 11, Ref~759 discloses the method of claim 1, wherein the determining the first offset calibration, the determining the second offset calibration, and the determining the third offset calibration is performed by a comparator (424 of Fig. 4), meeting claim 11.
Allowable Subject Matter
Claims 2-4, 8-9 and 13-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/HIEU P NGUYEN/Primary Examiner, Art Unit 2843