DETAILED ACTION
This office action is in response to the amendments filed on January 12, 2026. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
The present office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are currently pending in this application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/7/2023, 2/7/2026 are being considered by the examiner. The information disclosure statement filed 2/5/2026 fails to comply with 37 CFR 1.97(c) because it lacks a timing statement as specified in 37 CFR 1.97(e). It has been placed in the application file, but the information referred to therein has not been considered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8, 12-14, 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0225708) in view of Lee (US 8,604,615) and in further view of Vadhavkar (US 2016/0343687).
With respect to Claim 1, Lee ‘708 shows (Fig. 7A) most aspects of the current invention including a semiconductor package, comprising:
a plurality of first semiconductor chips (stack of chips 251 minus the uppermost chip 251) sequentially stacked, each of the plurality of first semiconductor chips including a circuit layer (696; layer comprising circuitry) on a first surface of a first substrate, a through-silicon via (157) passing through the first substrate, and a bump pad (pads connected by bumps 168) connected to the through-silicon via;
a second semiconductor chip (uppermost chip 251) on an uppermost first semiconductor chip, the second semiconductor chip including a circuit layer (696; layer comprising circuitry) on a first surface of a second substrate, and a via (157) in the second substrate
Furthermore, although Lee ‘708 shows the second semiconductor chip includes a via (157) in the second substrate, Lee ‘708 fails to disclose the via is a thermal path via, and an adhesive material filling a gap between the second semiconductor chip and the plurality of first semiconductor chips and gaps between adjacent ones of the plurality of first semiconductor chips and contacting side surfaces of the second semiconductor chip and each of the plurality of first semiconductor chips; and a sealing member covering the adhesive material, the second semiconductor chip and each of the plurality of first semiconductor chips.
On the other hand, and in the same field of endeavor, Lee ‘615 teaches (Fig 16) a semiconductor package, comprising a plurality of first semiconductor chips (stack of chips 10,50,70,80) sequentially stacked, each of the first semiconductor chips including a through-silicon via (82) passing through a first substrate, a second semiconductor chip (uppermost chip 90) on an uppermost first semiconductor chip, an adhesive material (88) filling a gap between the second semiconductor chip and the plurality of first semiconductor chips and gaps between adjacent ones of the plurality of first semiconductor chips and contacting side surfaces of the second semiconductor chip and each of the plurality of first semiconductor chips and a sealing member (89) covering the adhesive material, the second semiconductor chip and each of the plurality of first semiconductor chips. Lee ‘615 teaches the adhesive material filling a gap between the second semiconductor chip and the plurality of first semiconductor chips, protects the plurality of semiconductor chips from external moisture on their side surfaces and fix the second semiconductor chip to the uppermost first semiconductor chip.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to modify the device of Lee ‘708 to include an adhesive material filling a gap between the second semiconductor chip and the plurality of first semiconductor chips and gaps between adjacent ones of the plurality of first semiconductor chips and contacting side surfaces of the second semiconductor chip and each of the plurality of first semiconductor chips; and a sealing member covering the adhesive material, the second semiconductor chip and each of the plurality of first semiconductor chips, as taught by Lee ‘615 because the adhesive material filling a gap between the second semiconductor chip and the plurality of first semiconductor chips, protects the plurality of semiconductor chips from external moisture on their side surfaces and fix the second semiconductor chip to the uppermost first semiconductor chip.
However, the combination of references do not teach the second semiconductor chip includes via is a thermal path via.
On the other hand, and in the same field of endeavor, Vadhavkar teaches (Fig 1) a semiconductor package, comprising a plurality of first semiconductor chips (stack 128 of chips 108 minus the uppermost chip 108) sequentially stacked, each of the first semiconductor chips including a through-silicon via (140) passing through a first substrate, a second semiconductor chip (uppermost chip 108) on an uppermost first semiconductor chip, the second semiconductor chip including and a thermal path via (140) in a second substrate. Vadhavkar teaches in addition to electrical communication, the TSVs transfer heat away from the die stack and toward the semiconductor material encapsulating the die stack, which can provide enhanced thermal properties that lower the operating temperatures of the first and second dies in the assembly (par 14-15).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate wherein the via is a thermal path via in the device of Lee ‘708 and Lee ‘615, as taught by Vadhavkar because in addition to electrical communication, the TSVs transfer heat away from the die stack and toward the semiconductor material encapsulating the die stack, which can provide enhanced thermal properties that lower the operating temperatures of the first and second dies in the assembly.
With respect to Claim 2, Vadhavkar teaches (Fig 1) wherein the thermal path via includes a material having a thermal conductivity higher than a thermal conductivity of a material of the second substrate.
With respect to Claim 3, Lee ‘708 shows (Fig. 7A) wherein the through-silicon via includes a first metal, and the thermal path via includes a second metal the same as the first metal of the through-silicon via.
With respect to Claim 5, Lee ‘708 shows (Fig. 7A) wherein the thermal path via includes copper, aluminum, tungsten, nickel, molybdenum, gold, silver, graphene, or diamond (par 114-115; conductive material 156)
With respect to Claim 6, Lee ‘708 shows (Fig. 7A) wherein the thermal path via includes PETEOS, SiCOH, SiN, or SiCN (par 114-115; liner 153)
With respect to Claim 7, Lee ‘708 shows (Fig. 7A) wherein: the thermal path via is in a hole extending into an inside of the second substrate, and the thermal path via includes a conductive pattern in the hole and an insulation liner (153) surrounding a sidewall, and an upper surface of the conductive pattern.
With respect to Claim 8, Lee ‘708 shows (Fig. 7A) wherein: the thermal path via includes a plurality of thermal path vias, and the through-silicon via includes a plurality of through-silicon vias, and a layout of the plurality of the thermal path vias is the same as a layout of the plurality of the through-silicon vias.
With respect to Claim 12, Lee ‘708 shows (Fig. 7A) wherein a first vertical height of the thermal path via is 10% to 90% of a total thickness of the second substrate.
With respect to Claim 13, Lee ‘708 shows (Fig. 7A) most aspects of the current invention including a semiconductor package, comprising:
a first semiconductor chip (see illustration) including a circuit layer (696; layer comprising circuitry) on a first surface of a first substrate, a first through-silicon via (157; via of the first semiconductor chip) passing through the first substrate, and a first lower bump pad (168; bump on lower surface of first chip) on the first surface of the first substrate and connected to the first through-silicon via, and a first upper bump pad (pad on upper surface of chip connected by bumps 168) on a second surface opposite the first surface of the first substrate connected to the first through-silicon via
a second semiconductor chip (see illustration) including a circuit layer (696; layer comprising circuitry) on a first surface of a second substrate, a second through-silicon via (157; via of the second semiconductor chip) passing through the second substrate, a second lower bump pad (168; bump on lower surface of second chip) on the first surface of the second substrate and connected to the second through-silicon via, a second upper bump pad (pad on upper surface of chip connected by bumps 168) on a second surface opposite the first surface of the second substrate connected to the second through-silicon via, and a first conductive bump (168) bonding the first and second semiconductor chips between the first upper bump pad and the second lower bump pad;
a third semiconductor chip (see illustration) including a circuit layer (696; layer comprising circuitry) on a first surface of a third substrate, a via (157; via of the third semiconductor chip) extending from the first surface of the third substrate to an inside of the third substrate, a third lower bump pad (168; bump on lower surface of third chip) on the first surface of the third substrate, and a second conductive bump (168) for bonding the second and third semiconductor chips between the second upper bump pad and the third lower bump pad,
wherein the third semiconductor chip is an uppermost chip
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Furthermore, although Lee ‘708 shows the second semiconductor chip includes a via (157) in the second substrate, Lee ‘708 fails to disclose the via is a thermal path via, and an adhesive material filling a gap between the first semiconductor chip and second semiconductor chip and a gap between the second semiconductor chip and the third semiconductor chip, and contacting side surfaces of the first, second and third semiconductor chips, and a sealing member covering the first to third semiconductor chips and the adhesive material.
On the other hand, and in the same field of endeavor, Lee ‘615 teaches (Fig 16) a semiconductor package, comprising a plurality of semiconductor chips including a first semiconductor chip (70), a second semiconductor chip (80), and a third semiconductor chip (90), an adhesive material (88) filling a gap between the first semiconductor chip and second semiconductor chip and a gap between the second semiconductor chip and the third semiconductor chip, and contacting side surfaces of the first, second and third semiconductor chips, and a sealing member (89) covering the first to third semiconductor chips and the adhesive material. Lee ‘615 teaches the adhesive material filling a gap between the second semiconductor chip and the plurality of first semiconductor chips, protects the plurality of semiconductor chips from external moisture on their side surfaces and fix the second semiconductor chip to the uppermost first semiconductor chip.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to modify the device of Lee ‘708 to include an adhesive material filling a gap between the first semiconductor chip and second semiconductor chip and a gap between the second semiconductor chip and the third semiconductor chip, and contacting side surfaces of the first, second and third semiconductor chips, and a sealing member covering the first to third semiconductor chips and the adhesive material, as taught by Lee ‘615 because the adhesive material filling a gap between the second semiconductor chip and the plurality of first semiconductor chips, protects the plurality of semiconductor chips from external moisture on their side surfaces and fix the second semiconductor chip to the uppermost first semiconductor chip.
However, the combination of references do not teach the third semiconductor chip includes via is a thermal path via.
On the other hand, and in the same field of endeavor, Vadhavkar teaches (Fig 1) a semiconductor package, comprising a plurality of first semiconductor chips (stack 128 of chips 108 minus the uppermost chip 108) sequentially stacked, each of the first semiconductor chips including a through-silicon via (140) passing through a first substrate, a second semiconductor chip (uppermost chip 108) on an uppermost first semiconductor chip, the second semiconductor chip including and a thermal path via (140) in a second substrate. Vadhavkar teaches in addition to electrical communication, the TSVs transfer heat away from the die stack and toward the semiconductor material encapsulating the die stack, which can provide enhanced thermal properties that lower the operating temperatures of the first and second dies in the assembly (par 14-15).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have it would have been obvious at the time the invention was filed to one of ordinary skill in the art to incorporate wherein the via is a thermal path via in the device of Lee ‘708 and Lee ‘615, as taught by Vadhavkar because in addition to electrical communication, the TSVs transfer heat away from the die stack and toward the semiconductor material encapsulating the die stack, which can provide enhanced thermal properties that lower the operating temperatures of the first and second dies in the assembly.
With respect to Claim 14, Lee ‘708 shows (Fig. 7A) wherein the thermal path via is aligned with the third lower bump pad in a vertical direction.
With respect to Claim 17, Vadhavkar teaches (Fig 1) wherein the thermal path via includes a first material having a first thermal conductivity higher than a second thermal conductivity of the third substrate.
With respect to Claim 18, Lee ‘708 shows (Fig. 7A) wherein a first vertical height of the thermal path via is 10% to 90% of a total thickness of the third substrate
With respect to Claim 19, Lee ‘708 shows (Fig. 7A) most aspects of the current invention including a semiconductor package, comprising:
a plurality of first semiconductor chips (stack of chips 251 minus the uppermost chip 251) sequentially stacked, each of the plurality of first semiconductor chips including a circuit layer (696; layer comprising circuitry) on a first surface of a first substrate, a through-silicon via (157) passing through the first substrate, and a bump pad (pads connected by bumps 168) connected to the through-silicon via;
a second semiconductor chip (uppermost chip 251) on an uppermost first semiconductor chip, the second semiconductor chip including a circuit layer (696; layer comprising circuitry) on a first surface of a second substrate, and a via (157) extending from the first surface of the second substrate to an inside of the second substrate and the via in the second substrate,
wherein the through-silicon via includes a first conductive pattern (conductive material 156) passing through the first substrate and a first insulation liner (153) surrounding a sidewall of the first conductive pattern, wherein the second semiconductor chip is an uppermost chip, and wherein the via includes a second conductive pattern (conductive material 156) in a hole extending to the inside of the second substrate
Furthermore, although Lee ‘708 shows the second semiconductor chip includes a via (157) in the second substrate, Lee ‘708 fails to disclose the via is a thermal path via and an adhesive material filling a gap between the second semiconductor chip and plurality of first semiconductor chips and gaps between adjacent ones of the plurality of first semiconductor chips, and contacting side surfaces of the second semiconductor chip and each of the plurality of first semiconductor chips, and a sealing member covering the second semiconductor chip and each of the plurality of first semiconductor chips.
On the other hand, and in the same field of endeavor, Lee ‘615 teaches (Fig 16) a semiconductor package, comprising a plurality of first semiconductor chips (stack of chips 10,50,70,80) sequentially stacked, a second semiconductor chip (uppermost chip 90) on an uppermost first semiconductor chip, an adhesive material (88) filling a gap between the second semiconductor chip and plurality of first semiconductor chips and gaps between adjacent ones of the plurality of first semiconductor chips, and contacting side surfaces of the second semiconductor chip and each of the plurality of first semiconductor chips, a sealing member (89) covering the second semiconductor chip and each of the plurality of first semiconductor chips. Lee ‘615 teaches the adhesive material filling a gap between the second semiconductor chip and the plurality of first semiconductor chips, protects the plurality of semiconductor chips from external moisture on their side surfaces and fix the second semiconductor chip to the uppermost first semiconductor chip.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to modify the device of Lee ‘708 to include an adhesive material filling a gap between the second semiconductor chip and plurality of first semiconductor chips and gaps between adjacent ones of the plurality of first semiconductor chips, and contacting side surfaces of the second semiconductor chip and each of the plurality of first semiconductor chips, and a sealing member covering the second semiconductor chip and each of the plurality of first semiconductor chips, as taught by Lee ‘615 because the adhesive material filling a gap between the second semiconductor chip and the plurality of first semiconductor chips, protects the plurality of semiconductor chips from external moisture on their side surfaces and fix the second semiconductor chip to the uppermost first semiconductor chip.
However, the combination of references do not teach the second semiconductor chip includes via is a thermal path via.
On the other hand, and in the same field of endeavor, Vadhavkar teaches (Fig 1) a semiconductor package, comprising a plurality of first semiconductor chips (stack 128 of chips 108 minus the uppermost chip 108) sequentially stacked, each of the first semiconductor chips including a through-silicon via (140) passing through a first substrate, a second semiconductor chip (uppermost chip 108) on an uppermost first semiconductor chip, the second semiconductor chip including and a thermal path via (140) in a second substrate. Vadhavkar teaches in addition to electrical communication, the TSVs transfer heat away from the die stack and toward the semiconductor material encapsulating the die stack, which can provide enhanced thermal properties that lower the operating temperatures of the first and second dies in the assembly (par 14-15).
Therefore, it would have been obvious at the time the invention was filed to one of ordinary skill in the art to incorporate wherein the via is a thermal path via in the device of Lee ‘708 and Lee ‘615, as taught by Vadhavkar because in addition to electrical communication, the TSVs transfer heat away from the die stack and toward the semiconductor material encapsulating the die stack, which can provide enhanced thermal properties that lower the operating temperatures of the first and second dies in the assembly.
With respect to Claim 20, Lee ‘708 shows (Fig. 7A) wherein the thermal path via further includes a second insulation liner (153) surrounding a sidewall and an upper surface of the second conductive pattern.
Claims 4, 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘708 in view of Lee ‘615 and in further view of Vadhavkar and Ngai (US 8,941,233).
With respect to Claim 4, Lee ‘708 in view of Lee ‘615 and in further view of Vadhavkar show most aspects of the current invention. However, the combination of references do not show wherein the thermal path via includes a second conductive material different from a first conductive material of the through-silicon via.
On the other hand, and in the same field of endeavor, Ngai teaches (Fig 2) a semiconductor package, comprising a plurality of first semiconductor chips (stack 102A-102C) sequentially stacked, each of the first semiconductor chips including a through-silicon via (110) passing through a first substrate, a second semiconductor chip (202) on an uppermost first semiconductor chip, the second semiconductor chip including and a thermal path via (210) in a second substrate, wherein the thermal path via includes a second conductive material different from a first conductive material of the through-silicon via. Ngai teaches the plurality of TSVs 110 may be used to transfer signals between dies, while the plurality of TSVs 210 may be used to dissipate heat vertically from the stack of dies.
Therefore, it would have been obvious at the time the invention was filed to one of ordinary skill in the art to incorporate wherein the thermal path via includes a second conductive material different from a first conductive material of the through-silicon via, in the device of Lee ‘708, Lee ‘615 and Vadhavkar, as taught by Ngai because the plurality of TSVs 110 may be used to transfer signals between dies, while the plurality of TSVs 210 may be used to dissipate heat vertically from the stack of dies.
With respect to Claim 9, Lee ‘708 in view of Lee ‘615 and in further view of Vadhavkar show most aspects of the current invention. However, the combination of references do not show wherein the thermal path via includes a plurality of thermal path vias, and the through- silicon via includes a plurality of through-silicon vias, and a first layout of the plurality of the thermal path vias is different from a second layout of the plurality of the through-silicon vias.
On the other hand, and in the same field of endeavor, Ngai teaches (Fig 5) a semiconductor package, comprising a plurality of first semiconductor chips (stack 502A-502B,550) sequentially stacked, each of the first semiconductor chips including a through-silicon via (110) passing through a first substrate, a second semiconductor chip (502C) on an uppermost first semiconductor chip, the second semiconductor chip including and a thermal path via (510) in a second substrate, wherein the thermal path via includes a plurality of thermal path vias, and the through- silicon via includes a plurality of through-silicon vias, and a first layout of the plurality of the thermal path vias is different from a second layout of the plurality of the through-silicon vias. Ngai teaches the plurality of TSVs 110 may be used to transfer signals between dies, while the plurality of TSVs 510 may be used to dissipate heat vertically from the stack of dies.
Therefore, it would have been obvious at the time the invention was filed to one of ordinary skill in the art to incorporate wherein the thermal path via includes a plurality of thermal path vias, and the through- silicon via includes a plurality of through-silicon vias, and a first layout of the plurality of the thermal path vias is different from a second layout of the plurality of the through-silicon vias, in the device of Lee ‘708, Lee ‘615 and Vadhavkar, as taught by Ngai because the plurality of TSVs 110 may be used to transfer signals between dies, while the plurality of TSVs 510 may be used to dissipate heat vertically from the stack of dies.
With respect to Claim 10, Lee ‘708 in view of Lee ‘615 and in further view of Vadhavkar show most aspects of the current invention. However, the combination of references do not show wherein: the thermal path via has a first diameter the same as a second diameter of the through-silicon via, and the thermal path via has a first vertical height the same as a second vertical height of the through-silicon via.
On the other hand, and in the same field of endeavor, Ngai teaches (Fig 2) a semiconductor package, comprising a plurality of first semiconductor chips (stack 102A-102C) sequentially stacked, each of the first semiconductor chips including a through-silicon via (110) passing through a first substrate, a second semiconductor chip (202) on an uppermost first semiconductor chip, the second semiconductor chip including and a thermal path via (210) in a second substrate, wherein: the thermal path via has a first diameter the same as a second diameter of the through-silicon via, and the thermal path via has a first vertical height the same as a second vertical height of the through-silicon via. Ngai teaches doing so to include more dies in a single package without substantially increasing the size of the substrate, stacking the dies in a vertical configuration to allow for faster interconnect communication between the dies in the device as the connection paths between one IC to another may be relatively shorter.
Therefore, it would have been obvious at the time the invention was filed to one of ordinary skill in the art to incorporate wherein the thermal path via has a first diameter the same as a second diameter of the through-silicon via, and the thermal path via has a first vertical height the same as a second vertical height of the through-silicon via in the device of Lee ‘708, Lee ‘615 and Vadhavkar, as taught by Ngai to include more dies in a single package without substantially increasing the size of the substrate, stacking the dies in a vertical configuration to allow for faster interconnect communication between the dies in the device as the connection paths between one IC to another may be relatively shorter.
Claims 11, 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘708 in view of Lee ‘615 and in further view of Vadhavkar and Gambino (US 2016/0181174).
With respect to Claim 11, Lee ‘708 in view of Lee ‘615 and in further view of Vadhavkar show most aspects of the current invention. However, the combination of references do not show wherein the thermal path via has a first volume different from a second volume of the through-silicon via.
On the other hand, and in the same field of endeavor, Gambino teaches (Fig 3A,5) a semiconductor package, comprising a first semiconductor chip (116B) including a through-silicon via (135) passing through a first substrate, a second semiconductor chip (116C) on the first semiconductor chip, the second semiconductor chip including a through-silicon via (135) passing through a second substrate, a third semiconductor chip (116D), chip including a thermal path via (150) on a third substate, a third lower bump (124) on the first surface of the third substrate, wherein the thermal path via has a first volume different from a second volume of the through-silicon via. Gambino teaches the thermal path vias may be useful in providing an efficient thermal path for the removal of heat produced by active devices such as transistors within active device region, and to provide adequate electrical insulation between thermal path vias and active circuits, in active device region, useful because it can allow for the use of various TCPV fill materials that are efficient electrical and thermal conductors (par 40-42).
Therefore, it would have been obvious at the time the invention was filed to one of ordinary skill in the art to incorporate wherein the thermal path via has a first volume different from a second volume of the through-silicon via, in the device of Lee ‘708, Lee ‘615 and Vadhavkar, as taught by Gambino because the thermal path vias may be useful in providing an efficient thermal path for the removal of heat produced by active devices such as transistors within active device region, and to provide adequate electrical insulation between thermal path vias and active circuits, in active device region, useful because it can allow for the use of various TCPV fill materials that are efficient electrical and thermal conductors.
However, it is noted that the specification fails to provide teachings about the criticality of having the first volume different from a second volume, as claimed in the instant application.
Regarding claim 11, the courts have held that differences in the volumes will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such volumes are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Criticality: Since the applicant has not established the criticality of the volumes and similar volumes are known in the art (see e.g. Gambino), it would have been obvious to one of the ordinary skill in the art to use these values in the device Lee ‘708, Lee ‘615 and Vadhavkar. The specification contains no disclosure of either the critical nature of the claimed volumes or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 15, Lee ‘708 in view of Lee ‘615 and in further view of Vadhavkar show most aspects of the current invention. However, the combination of references do not show wherein the thermal path via is not aligned with the third lower bump pad in a vertical direction.
On the other hand, and in the same field of endeavor, Gambino teaches (Fig 3A,5) a semiconductor package, comprising a first semiconductor chip (116B) including a through-silicon via (135) passing through a first substrate, a second semiconductor chip (116C) on the first semiconductor chip, the second semiconductor chip including a through-silicon via (135) passing through a second substrate, a third semiconductor chip (116D), chip including a thermal path via (150) on a third substate, a third lower bump (124) on the first surface of the third substrate, wherein the thermal path via is not aligned with the third lower bump pad in a vertical direction. Gambino teaches the thermal path vias may be useful in providing an efficient thermal path for the removal of heat produced by active devices such as transistors within active device region, and to provide adequate electrical insulation between thermal path vias and active circuits, in active device region, useful because it can allow for the use of various TCPV fill materials that are efficient electrical and thermal conductors (par 40-42).
Therefore, it would have been obvious at the time the invention was filed to one of ordinary skill in the art to incorporate wherein the thermal path via is not aligned with the third lower bump pad in a vertical direction, in the device of Lee ‘708, Lee ‘615 and Vadhavkar, as taught by Gambino because the thermal path vias may be useful in providing an efficient thermal path for the removal of heat produced by active devices such as transistors within active device region, and to provide adequate electrical insulation between thermal path vias and active circuits, in active device region, useful because it can allow for the use of various TCPV fill materials that are efficient electrical and thermal conductors.
With respect to Claim 16, , Lee ‘708 in view of Lee ‘615 and in further view of Vadhavkar show most aspects of the current invention. However, the combination of references do not show wherein the thermal path via is not electrically connected to the third lower bump pad.
On the other hand, and in the same field of endeavor, Gambino teaches (Fig 3A,5) a semiconductor package, comprising a first semiconductor chip (116B) including a through-silicon via (135) passing through a first substrate, a second semiconductor chip (116C) on the first semiconductor chip, the second semiconductor chip including a through-silicon via (135) passing through a second substrate, a third semiconductor chip (116D), chip including a thermal path via (150) on a third substate, a third lower bump (124) on the first surface of the third substrate, wherein the thermal path via is not electrically connected to the third lower bump pad. Gambino teaches the thermal path vias may be useful in providing an efficient thermal path for the removal of heat produced by active devices such as transistors within active device region, and to provide adequate electrical insulation between thermal path vias and active circuits, in active device region, useful because it can allow for the use of various TCPV fill materials that are efficient electrical and thermal conductors (par 40-42).
Therefore, it would have been obvious at the time the invention was filed to one of ordinary skill in the art to incorporate wherein the thermal path via is not electrically connected to the third lower bump pad, in the device of Lee ‘708, Lee ‘615 and Vadhavkar, as taught by Gambino because the thermal path vias may be useful in providing an efficient thermal path for the removal of heat produced by active devices such as transistors within active device region, and to provide adequate electrical insulation between thermal path vias and active circuits, in active device region, useful because it can allow for the use of various TCPV fill materials that are efficient electrical and thermal conductors.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection above in which discloses the teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814