Prosecution Insights
Last updated: April 19, 2026
Application No. 18/230,858

LIGHT EMITTING DEVICE AND DISPLAY APPARATUS INCLUDING THE SAME

Final Rejection §102§103
Filed
Aug 07, 2023
Examiner
YEUNG LOPEZ, FEIFEI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
2y 6m
To Grant
78%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
858 granted / 1060 resolved
+12.9% vs TC avg
Minimal -3% lift
Without
With
+-3.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
47 currently pending
Career history
1107
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
52.0%
+12.0% vs TC avg
§102
26.1%
-13.9% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1060 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1,10-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shen et al (PG Pub 2005/0067627 A1). Regarding claim 1, Shen teaches a light emitting device, comprising: a first light emitting element (6c, 11, 4c, fig. 7) configured to emit light of a first wavelength (blue, fig. 7); a PN junction layer (9) provided on the first light emitting element; and a second light emitting element (6b, 10, 4b) provided on the PN junction layer and configured to emit light of a second wavelength (green) different from the first wavelength, wherein the PN junction layer comprises: a first conductivity type semiconductor layer (p++ in TJ 9, fig. 7) provided on the first light emitting element and doped with impurities of a first conductivity type; and a second conductivity type semiconductor layer (n++ in TJ 9, fig. 7) provided on the first conductivity type semiconductor layer and doped with impurities of a second conductivity type electrically opposite to the first conductivity type, wherein each of the first light emitting element and the second light emitting element comprises: a first semiconductor layer ;a second semiconductor layer; and an active layer provided between the first semiconductor layer and the second semiconductor layer (fig. 7), wherein the first conductivity type semiconductor layer (p++) is provided on an upper surface of the second semiconductor layer of the first light emitting element, wherein the first semiconductor layer of the second light emitting element is provided on an upper surface of the second conductivity type semiconductor layer (paragraphs [0006][0019] teach light is emitted when the three LEDs are in forward bias while the tunnel junctions are in reverse bias, which mean that the n++ layer is on top of the p++ layer in each layers 9), wherein the first semiconductor layer of the first light emitting element and the first semiconductor layer of the second light emitting element are doped with impurities of the first conductivity type (p type: 4b and 4c, fig. 7), and wherein the second semiconductor layer of the first light emitting element and the second semiconductor layer of the second light emitting element are doped with impurities of the second conductivity type (n type: 6c and 6b). Regarding claim 10, Shen teaches the light emitting device of claim 1, wherein: the PN junction layer provided on the first light emitting element is a first PN junction layer, and the light emitting device further comprises: a second PN junction layer (9, fig. 7) provided on the second light emitting element; and a third light emitting element (6a, 5, 4a) provided on the second PN junction layer and configured to emit light of a third wavelength (red, abstract) different from the first wavelength and the second wavelength, and the second PN junction layer comprises: a first conductivity type semiconductor layer provided on the second light emitting element and doped with impurities of the first conductivity type (p, fig. 7); and a second conductivity type semiconductor layer provided on the first conductivity type semiconductor layer of the second PN junction layer and doped with impurities of the second conductivity type (n, fig. 7). Regarding claim 11, Shen teaches the light emitting device of claim 10, wherein: each of the first light emitting element, the second light emitting element, and the third light emitting element comprises: a first semiconductor layer; a second semiconductor layer; and an active layer provided between the first semiconductor layer and the second semiconductor layer (fig. 7). Regarding claim 12, Shen teaches the light emitting device of claim 11, wherein: the first conductivity type semiconductor layer of the first PN junction layer is provided on an upper surface of the second semiconductor layer of the first light emitting element, the first semiconductor layer of the second light emitting element is provided on an upper surface of the second conductivity type semiconductor layer of the first PN junction layer, the first conductivity type semiconductor layer of the second PN junction layer is provided on an upper surface of the second semiconductor layer of the second light emitting element, and the first semiconductor layer of the third light emitting element is provided on an upper surface of the second conductivity type semiconductor layer of the second PN junction layer (fig. 7). Regarding claim 13, Shen teaches the light emitting device of claim 12, wherein: the first semiconductor layer of the first light emitting element, the first conductivity type semiconductor layer of the first PN junction layer, the first semiconductor layer of the second light emitting element, the first conductivity type semiconductor layer of the second PN junction layer, and the first semiconductor layer of the third light emitting element are doped with impurities of the first conductivity type, and the second semiconductor layer of the first light emitting element, the second conductivity type semiconductor layer of the first PN junction layer, the second semiconductor layer of the second light emitting element, the second conductivity type semiconductor layer of the second PN junction layer, and the second semiconductor layer of the third light emitting element are doped with impurities of the second conductivity type (fig. 7). Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al (PG Pub 2005/0067627 A1) as applied to claim 1 above, and further in view of Moros et al (PG Pub 2021/0234063 A1). Regarding claim 2, Shen does not teach the thickness of the first and second conductivity type semiconductor layers. In the same field of endeavor, Maros teaches a first thickness of the first conductivity type semiconductor layer and a second thickness of the second conductivity type semiconductor layer are each about 1 nanometer (nm) or more and about 1 micrometer (µm) or less (paragraph [0043]), for the benefit of allowing current to flow through the light emitting devices under forward bias (paragraph [0043]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make a first thickness of the first conductivity type semiconductor layer and a second thickness of the second conductivity type semiconductor layer to be each about 1 nanometer (nm) or more and about 1 micrometer (µm) or less, for the benefit of allowing current to flow through the light emitting devices under forward bias. Regarding claim 3, Shen does not teach each of doping concentrations of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer ranges from 1016/cm3 to 1020/cm3. In the same field of endeavor, Maros teaches each of doping concentrations of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer ranges from 1016/cm3 to 1020/cm3 (paragraph [0043]), for the benefit of allowing current to flow through the light emitting devices under forward bias (paragraph [0043]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make each of doping concentrations of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer range from 1016/cm3 to 1020/cm3, for the benefit of allowing current to flow through the light emitting devices under forward bias. Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al (PG Pub 2005/0067627 A1) as applied to claim 12 above, and further in view of Lo et al (PG Pub 2014/0110664 A1) and Sugawara et al (US Patent 6,538,265 B1). Regarding claim 15, Shen remains as applied in claim 12. Shen further teaches the light emitting device of claim 12, wherein: the active layer of the first light emitting element and the active layer of the second light emitting element each comprise a nitride semiconductor material including indium (In) (fig. 7). Shen does not each an indium content in the active layer of the first light emitting element is less than an indium content in the active layer of the second light emitting element, and an indium content in the active layer of the second light emitting element is less than an indium content in the active layer of the third light emitting element. Shen teaches the first to third light emitting elements are to emit blue, green (fig. 7, and red light (abstract), respectively. In the same field of endeavor, Lo teaches to make indium content in a blue-light-emitting layer less than that in a green-light-emitting layer, and to make the indium content in a green-light-emitting layer less than that in a red-light-emitting layer (paragraph [0096]). Shen does not teach the active layer of the third light emitting element to comprise nitride semiconductor. In the same field of endeavor, Sugawara teaches nitride semiconductor with indium provides an efficient active region for a red light emitting device (column 4, lines 29-45). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make an indium content in the active layer of the first light emitting element is less than an indium content in the active layer of the second light emitting element, and an indium content in the active layer of the second light emitting element is less than an indium content in the active layer of the third light emitting element, for the benefit of providing layers that could emit blue, green, and red, light, respectively, and to make the third light emitting element to comprise nitride semiconductor, for the benefit of providing an efficient active region for a red light emitting device. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chae et al (PG Pub 2015/0206472 A1) and Shen et al (PG Pub 2005/0067627 A1). Regarding claim 20, Chae teaches a display apparatus, comprising: a pixel array including a plurality of pixels (fig. 1) provided in a two-dimensional array; a scan driving circuit (200) for providing a scan signal; a data driving circuit (300) for providing a data signal; and a processor (500 and 100, fig. 1) configured to control operations of the scan driving circuit and the data driving circuit. Chae does not teach wherein each of the plurality of pixels in the pixel array comprises: a first light emitting element configured to emit light of a first wavelength; a PN junction layer provided on the first light emitting element; and a second light emitting element provided on the PN junction layer and configured to emit light of a second wavelength different from the first wavelength, wherein the PN junction layer comprises: a first conductivity type semiconductor layer provided on the first light emitting element and doped with impurities of a first conductivity type; and a second conductivity type semiconductor layer provided on the first conductivity type semiconductor layer and doped with impurities of a second conductivity type electrically opposite to the first conductivity type, wherein each of the first light emitting element and the second light emitting element comprises: a first semiconductor layer; a second semiconductor layer; and an active laver provided between the first semiconductor laver and the second semiconductor layer, wherein the first conductivity type semiconductor layer is provided on an upper surface of the second semiconductor layer of the first light emitting element, wherein the first semiconductor laver of the second light emitting element is provided on an upper surface of the second conductivity type semiconductor layer, wherein the first semiconductor layer of the first light emitting element and the first semiconductor layer of the second light emitting element are doped with impurities of the first conductivity type, and wherein the second semiconductor laver of the first light emitting element and the second semiconductor layer of the second light emitting element are doped with impurities of the second conductivity type. In the same field of endeavor, Shen teaches each pixel comprises: a first light emitting element (6c, 11, 4c, fig. 7) configured to emit light of a first wavelength (blue, fig. 7); a PN junction layer (9) provided on the first light emitting element; and a second light emitting element (6b, 10, 4b) provided on the PN junction layer and configured to emit light of a second wavelength (green) different from the first wavelength, wherein the PN junction layer comprises: a first conductivity type semiconductor layer (p++, fig. 7) provided on the first light emitting element and doped with impurities of a first conductivity type; and a second conductivity type semiconductor layer (n++, fig. 7) provided on (paragraphs [0006][0019] teach light is emitted when the three LEDs are in forward bias while the tunnel junctions are in reverse bias, which mean that the n++ layer is on top of the p++ layer in each layers 9) the first conductivity type semiconductor layer and doped with impurities of a second conductivity type electrically opposite to the first conductivity type, for the benefit of providing a white LED with low cost and high lifetime (paragraph [0005]), wherein each of the first light emitting element and the second light emitting element comprises: a first semiconductor layer; a second semiconductor layer; and an active laver provided between the first semiconductor layer (fig. 7) and the second semiconductor layer, wherein the first conductivity type semiconductor layer is provided on an upper surface of the second semiconductor layer of the first light emitting element, wherein the first semiconductor layer of the second light emitting element is provided on an upper surface of the second conductivity type semiconductor layer, wherein the first semiconductor layer (4c) of the first light emitting element and the first semiconductor layer (4b) of the second light emitting element are doped with impurities of the first conductivity type (p), and wherein the second semiconductor layer (6c) of the first light emitting element and the second semiconductor layer (6b) of the second light emitting element are doped with impurities of the second conductivity type (n). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make each pixel to comprise a first light emitting element configured to emit light of a first wavelength; a PN junction layer provided on the first light emitting element; and a second light emitting element provided on the PN junction layer and configured to emit light of a second wavelength different from the first wavelength, wherein the PN junction layer comprises: a first conductivity type semiconductor layer provided on the first light emitting element and doped with impurities of a first conductivity type; and a second conductivity type semiconductor layer provided on the first conductivity type semiconductor layer and doped with impurities of a second conductivity type electrically opposite to the first conductivity type, and ]), wherein each of the first light emitting element and the second light emitting element comprises: a first semiconductor layer; a second semiconductor layer; and an active laver provided between the first semiconductor layer (fig. 7) and the second semiconductor layer, wherein the first conductivity type semiconductor layer is provided on an upper surface of the second semiconductor layer of the first light emitting element, wherein the first semiconductor layer of the second light emitting element is provided on an upper surface of the second conductivity type semiconductor layer, wherein the first semiconductor layer (4c) of the first light emitting element and the first semiconductor layer (4b) of the second light emitting element are doped with impurities of the first conductivity type (p), and wherein the second semiconductor layer (6c) of the first light emitting element and the second semiconductor layer (6b) of the second light emitting element are doped with impurities of the second conductivity type (n), for the benefit of providing a white LED with low cost and high lifetime. Claim(s) 8,14,16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al (PG Pub 2005/0067627 A1) as applied to claims 1,12,13 above, and further in view of Fan et al (PG Pub 2009/0078955 A1). Regarding claim 8, Shen remains as applied in claim 1. Furthermore, Shen teaches the light emitting device of claim 1, wherein: the first light emitting element, the PN junction layer, and the second light emitting element operate as a first diode, a second diode, and a third diode in an equivalent circuit of the light emitting device, a cathode of the second diode is coupled to an anode of the first diode, a cathode of the third diode is coupled to an anode of the second diode (fig. 7). Shen does not teach a common ground is coupled to a cathode of the first diode, the anode of the second diode, and the cathode of the third diode, and an individual driving voltage line is coupled to each of the anode of the first diode and the anode of the third diode. In the same field of endeavor, Fan teaches coupling the cathode of each of three LEDs to a common ground (fig. 2C) and coupling an individual driving voltage line to each of their anode (VR, VG, VB, fig.2C), for the benefit of independently turning each LED on/off (paragraph [0014]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to couple a common ground to a cathode of the first diode and the cathode of the third diode, and an individual driving voltage line is coupled to each of the anode of the first diode and the anode of the third diode, for the benefit of independently turning each LED on/off. Shen in view of Fan teaches coupling the “common ground to the anode of the second diode” because the anode of the second diode (p-GaN in 9, fig.7) is connected to the cathode of the second light emitting element (7b/6b), which Fan teaches to be coupled to the common ground. Regarding claim 14, Shen remains as applied in claim 13. Furthermore, Shen teaches the light emitting device of claim 13, wherein: the first light emitting element, the first PN junction layer, the second light emitting element, the second PN junction layer, and the third light emitting element operate as a first diode, a second diode, a third diode, a fourth diode, and a fifth diode in an equivalent circuit of the light emitting device, a cathode of the second diode is coupled to an anode of the first diode, a cathode of the third diode is coupled to an anode of the second diode, a cathode of the fourth diode is coupled to an anode of the third diode, a cathode of the fifth diode is coupled to an anode of the fourth diode (fig. 7). Shen does not teach a common ground is coupled to the cathode of the first diode, the anode of the second diode, the cathode of the third diode, the anode of the fourth diode, and the cathode of the fifth diode, and an individual driving voltage line is coupled to each of the anode of the first diode, the anode of the third diode, and the anode of the fifth diode. In the same field of endeavor, Fan teaches coupling the cathode of each of three LEDs to a common ground (fig. 2C) and coupling an individual driving voltage line to each of their anode (VR, VG, VB, fig.2C), for the benefit of independently turning each LED on/off (paragraph [0014]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to couple a common ground to the cathode of each of the first, third, and fifth diodes and to couple an individual driving voltage line to each of the anode of the first diode, the anode of the third diode, and the anode of the fifth diode, for the benefit of independently turning each LED on/off. Shen in view of Fan teaches coupling the common ground to the anode of the second diode and the anode of the fourth diode because they are coupled to the cathodes (6a and 7a; 6b and 7b, fig. 7) of the first and the fifth diodes, which, in view of Fan, are connected to the common ground. Regarding claim 16, Shen remains as applied in claim 12. Shen does not teaches the light emitting device of claim 12, wherein: a first edge region of the upper surface of the first semiconductor layer of the first light emitting element, a first edge region of the upper surface of the first semiconductor layer of the second light emitting element, a first edge region of the upper surface of the first semiconductor layer of the third light emitting element are exposed, a second edge region of the upper surface of the second semiconductor layer of the first light emitting element, and a second edge region of the upper surface of the second semiconductor layer of the second light emitting element are exposed, and the light emitting device further comprises: a first electrode provided in the second edge region of the upper surface of the second semiconductor layer of the first light emitting element; a second electrode provided in the second edge region of the upper surface of the second semiconductor layer of the second light emitting element; a third electrode provided on the upper surface of the second semiconductor layer of the third light emitting element; and a common electrode integrally provided in the first edge region of the upper surface of the first semiconductor layer of the first light emitting element, the first edge region of the upper surface of the first semiconductor layer of the second light emitting element, and the first edge region of the upper surface of the first semiconductor layer of the third light emitting element. In the same field of endeavor, Fan teaches coupling the cathode of each of three LEDs to a common ground (fig. 2C) and coupling an individual driving voltage line to each of their anode (VR, VG, VB, fig.2C) by exposing the edges of each exposing the upper surface of each the first and second semiconductor layers (206,210,214,218,222, fig. 2A) of each light emitting elements (208,216,220, figs. 2B and 2C) and providing individual electrodes on the anodes (p-type layers:222,214,210) and electrodes that connected to a common ground to their cathodes (n-type layers: 218,206), for the benefit of independently turning each LED on/off (paragraph [0014]). Shen in view of Fan teaches “a first edge region of the upper surface of the first semiconductor layer of the first light emitting element, a first edge region of the upper surface of the first semiconductor layer of the second light emitting element, a first edge region of the upper surface of the first semiconductor layer of the third light emitting element are exposed, a second edge region of the upper surface of the second semiconductor layer of the first light emitting element, and a second edge region of the upper surface of the second semiconductor layer of the second light emitting element are exposed, and the light emitting device further comprises: a first electrode provided in the second edge region of the upper surface of the second semiconductor layer of the first light emitting element; a second electrode provided in the second edge region of the upper surface of the second semiconductor layer of the second light emitting element; a third electrode provided on the upper surface of the second semiconductor layer of the third light emitting element; and a common electrode integrally provided in the first edge region of the upper surface of the first semiconductor layer of the first light emitting element, the first edge region of the upper surface of the first semiconductor layer of the second light emitting element, and the first edge region of the upper surface of the first semiconductor layer of the third light emitting element”, for the benefit of independently turning each LED on/off. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al (PG Pub 2005/0067627 A1) and Fan et al (PG Pub 2009/0078955 A1) as applied to claim 8 above, and further in view of Lo et al (PG Pub 2014/0110664 A1). Regarding claim 9, Shen remains as applied in claim 8. Shen further teaches the light emitting device of claim 12, wherein: the active layer of the first light emitting element, the active layer of the second light emitting element comprise a nitride semiconductor material including indium (In) (fig. 7). Shen does not each an indium content in the active layer of the first light emitting element is less than an indium content in the active layer of the second light emitting element. Shen teaches the first and third light emitting elements are to emit blue and green light (fig. 7), respectively. In the same field of endeavor, Lo teaches to make indium content in a blue-light-emitting layer less than that in a green-light-emitting layer (paragraph [0096]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make an indium content in the active layer of the first light emitting element is less than an indium content in the active layer of the second light emitting element for the benefit of providing layers that could emit blue and green light, respectively. Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al (PG Pub 2005/0067627 A1) and Fan et al (PG Pub 2009/0078955 A1) as applied to claim 16 above, and further in view of Armitage (PG Pub 2023/0420627 A1). Regarding claim 17, the previous combination remains as applied in claim 16. Shen further teaches the light emitting device of claim 16, wherein: a first side surface of the active layer of the first light emitting element, a first side surface of the second semiconductor layer of the first light emitting element, a first side surface of the first conductivity type semiconductor layer of the first PN junction layer, a first side surface of the second conductivity type semiconductor layer of the first PN junction layer, and a first side surface of the first semiconductor layer of the second light emitting element form a first plane continuously extending in a vertical direction, a first side surface of the active layer of the second light emitting element, a first side surface of the second semiconductor layer of the second light emitting element, a first side surface of the second conductivity type semiconductor layer of the second PN junction layer, a first side surface of the second conductivity type semiconductor layer of the second PN junction layer, and a first side surface of the first semiconductor layer of the third light emitting element form a second plane continuously extending in the vertical direction (fig. 7). Shen does not teach the light emitting device further comprises an insulating layer extending in the vertical direction along each of the first plane and the second plane. In the same field of endeavor, Armitage teaches an insulating layer (112, fig. 6) extending in the vertical direction along each of the first plane and the second plane, for the known benefit of protecting the device from external elements such as moisture. Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include an insulating layer extending in the vertical direction along each of the first plane and the second plane for the known benefit of protecting the device from external elements such as moisture. Regarding claim 18, Shen in view of Fan and Armitage teaches “the common electrode integrally extends along the first edge region of the upper surface of the first semiconductor layer of the first light emitting element, the insulating layer on the first plane, the first edge region of the upper surface of the first semiconductor layer of the second light emitting element, the insulating layer on the second plane, and the first edge region of the upper surface of the first semiconductor layer of the third light emitting element.” Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen (PG Pub 2005/0067627 A1) and Fan et al (PG Pub 2009/0078955 A1). Regarding claim 19, Shen teaches a display apparatus, comprising: a first light emitting device (LED), a second LED, and a third LED that are stacked (with active layers 11, 10, 5, respectively fig. 7) in a vertical direction and configured to emit light of different wavelengths (fig. 7); a first PN junction layer (9) provided between the first LED and the second LED; and a second PN junction layer (9) provided between the second LED and the third LED; wherein each of the first PN junction layer and the second PN junction layer comprises a first conductivity type semiconductor layer (p++, fig. 7) and a second conductivity type semiconductor layer (n++) with opposite conductivity types, wherein the first conductivity type semiconductor layer of the first PN junction layer and the second nitride semiconductor material of the first LED are adjacent (near but do not share a border) to each other and have conductive types opposite to each other (p++ in 9 and n 6c), wherein the second conductivity type semiconductor layer of the first PN junction laver and the first nitride semiconductor material of the second LED are adjacent (near but do not share a border) to each other and have conductive types opposite to each other (n++ in 9 and p 4b), wherein the first conductivity type semiconductor layer of the second PN junction layer and the second nitride semiconductor material of the second LED are adjacent (near but do not share a border) to each other and have conductive types opposite to each other (p++ in 9 and n 6b), and wherein the second conductivity type semiconductor layer of the second PN junction layer and the first nitride semiconductor material of the third LED are adjacent (near but do not share a border) to each other and have conductive types opposite to each other (n++ in 9 and p 4a). Shen does not teach two opposing edge regions on an upper surface of each of the first LED, the second LED, and the third LED are etched away to be exposed, and wherein each of the first LED, the second LED, and the third LED comprises: a first nitride semiconductor material and a second nitride semiconductor material with opposite conductivity types; an active layer configured to emit light and provided between the first light emitting element and the second nitride semiconductor material in the vertical direction; a common n-type electrode provided on one of the two opposing edge regions on the upper surface of each of the first LED, the second LED, and the third LED; and a plurality of p-type electrodes provided on another one of the two opposing edge regions on the upper surface of each of the first LED, the second LED, and the third LED. In the same field of endeavor, Fan teaches coupling the cathode of each of three LEDs to a common ground (fig. 2C) and coupling an individual driving voltage line to each of their anode (VR, VG, VB, fig.2C) by exposing the edges of each exposing the upper surface of each the first and second semiconductor layers (206,210,214,218,222, fig. 2A) of each light emitting elements (208,216,220, figs. 2B and 2C) and providing individual electrodes on the anodes (p-type layers:222,214,210) and electrodes that connected to a common ground to their cathodes (n-type layers: 218,206), for the benefit of independently turning each LED on/off (paragraph [0014]). Shen in view of Fan teaches “two opposing edge regions on an upper surface of each of the first LED, the second LED, and the third LED are etched away to be exposed, and wherein each of the first LED, the second LED, and the third LED comprises: a first nitride semiconductor material and a second nitride semiconductor material with opposite conductivity types; an active layer configured to emit light and provided between the first light emitting element and the second nitride semiconductor material in the vertical direction; a common n-type electrode provided on one of the two opposing edge regions on the upper surface of each of the first LED, the second LED, and the third LED; and a plurality of p-type electrodes provided on another one of the two opposing edge regions on the upper surface of each of the first LED, the second LED, and the third LED” for the benefit of providing electrical bias to the LEDs to turn them on/off. Response to Arguments Applicant's arguments filed January 7, 2026 have been fully considered but they are not persuasive because the previously cited references still teach the amended features. See rejection above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
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Prosecution Timeline

Aug 07, 2023
Application Filed
Oct 03, 2025
Non-Final Rejection — §102, §103
Dec 03, 2025
Interview Requested
Dec 23, 2025
Applicant Interview (Telephonic)
Dec 23, 2025
Examiner Interview Summary
Jan 07, 2026
Response Filed
Mar 05, 2026
Final Rejection — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
78%
With Interview (-3.0%)
2y 6m
Median Time to Grant
Moderate
PTA Risk
Based on 1060 resolved cases by this examiner. Grant probability derived from career allow rate.

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