DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I and Species II in the reply filed on 8 December 2025 is reacknowledged and maintained. Claims 3, 5, 6, 16, 17 and 20 are still withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species or invention, there being no allowable generic or linking claim. The requirement is still deemed proper and is therefore made FINAL.
Response to Arguments
Applicant's arguments filed 13 April 2026 have been fully considered but they are not persuasive.
Regarding the amendments to claims 1 and 12, the applicant states that support can be found in Fig. 1 and paragraphs 20-22. The examiner provides the figure and paragraphs below.
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[0020] A gate structure 105 may be provided over the nanowire fin 101. In embodiments, the gate structure 105 includes gate electrode 105a and gate dielectric material(s) 105b, which cover a portion of the nanowire fin 100, over both the critical dimension of width 'a' and the critical dimension of width 'b'. As should be understood by those of skill in the art, the portion of the nanowire fin 100 covered by the gate structure 105 will act as a channel region, with a depletion region 111 being on the thinner portion, e.g., width 'b', of the nanowire fin 101.
[0021] As should also be understood by those of ordinary skill in the art, the narrow section (e.g., width 'b') near the source region 109 will control the Vt (Ioff) of the device. For example, the asymmetric JL FINFET device 100 will turn off when the depletion region 111 is fully depleted, e.g., by preventing current to flow through the nanowire fin 101; whereas the drain region 107 of the device will control the on-state resistance. In other words, when the gate voltage (VG) is less than a threshold (Vth), the depletion region 111 is fully depleted of electrons; when the VG is about the same as the Vth a string-shaped channel of neutral n-type silicon connects the source and drain regions; and when the VG is greater than the Vth, but less than a flat-band voltage (VFB) the channel of neutral n-type semiconductor material expands in width and thickness.
[0022] In embodiments, the gate electrode 105a may be polysilicon material and the gate dielectric material(s) 105b may be a low-k or high-k dielectric material as is known in the art such that no further explanation is required herein for a complete understanding of the present disclosure. The polysilicon material may be doped with a p-type dopant or n-type dopant, depending on the device type. For example, in embodiments, the gate structure 105 may be heavily doped with a p-type dopant (e.g., boron), with the source region 109, drain region 107 and nanowire fin 111 being heavily doped with an n-type dopant (e.g., antimony, phosphorus or arsenic).
Regarding the “depletion region,” it is unclear how applicant is attempting to structurally define it with any specificity without defining the sidewall spacers, dopant type(s), concentration, profile, relative locations or application of voltages (which is based on use of the device and not a structural feature). The figures depict a bracket that encompasses a portion of the nanowire fin (101) that is overlapped by the gate structure (105) and sidewall spacers (103; not claimed), but does not show or describe any particular additional structure or boundaries other than the existing nanowire fin shape itself and its relationship with the gate structure and sidewall spacers. The disclosure does not physically define any dopant concentrations, profiles or physical boundaries thereof with any specificity within the nanowire fin, let alone in the claim.
A depletion region is not static physical structure but an area of charges that changes with respect to how the device is used, particularly, with voltages applied to gate, source and/or drain. The manner of operating the device does not differentiate an apparatus claim from the prior art. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987) See MPEP §2114. It has been held that when the claimed and prior art products are identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. See MPEP § 2112.01. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997).
The applicant’s disclosed structure is a nanowire fin (101; any suitable semiconductor material; par. 17) with a gate dielectric (105b; low-k or high-k dielectric material as is known in the art; par. 21), gate electrode (105a; p or n type polysilicon material as is known in the art; par. 21), sidewall spacers (103; not claimed; SiN or other low-k dielectric materials; par. 24), a source region (109) and a drain region (107). These structural features are provided for by the prior art.
Furthermore, the examiner does not find support for the new recitation of “semiconductor material underneath the gate structure is devoid of the depletion region” of claims 1 and 12. It’s unclear if “semiconductor material” is required to be comprised by the structure or not since it is within a “wherein” clause (see MPEP 2111.04). Even if amended such that the claimed structure comprises “semiconductor material” the recitation lacks structural relationship with required elements comprised by the claimed structure. Does the semiconductor material refer to the nanowire fin or some other unclaimed element? This is also a negative limitation that depends on the presence of a depletion region which is based on the device functional use (not an inherent structural feature with defined boundaries), i.e. applying a gate voltage or not. It’s unclear as to what structure is required to achieve the intended function and when is the function required to be present (does it always exist or only under particular conditions of operation). If the “semiconductor material” is referencing the nanowire fin itself, it’s unclear how the depletion region both exists and does not exist in the same area at the same time.
Notwithstanding the permissible instances, the use of functional language in a claim may fail "to provide a clear-cut indication of the scope of the subject matter embraced by the claim" and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). In this case, the structural scope of the claimed structure based on the presence or not of the depletion is not clear. The structural relationship between the required claim elements of the nanowire fin, source region, drain region, gate structure and/or semiconductor material at any given point in time before, during or after operation is unclear based on the depletion region recitations.
Applicant may resolve the ambiguities of a functional limitation in a number of ways. For example: (1) "the ambiguity might be resolved by using a quantitative metric (e.g., numeric limitation as to a physical property) rather than a qualitative functional feature" (see Halliburton Energy Servs., 514 F.3d at 1255-56, 85 USPQ2d at 1663); (2) applicant could demonstrate that the "specification provide[s] a formula for calculating a property along with examples that meet the claim limitation and examples that do not" (see id. at 1256, 85 USPQ2d at 1663 (citing Oakley, Inc. v. Sunglass Hut Int’l, 316 F.3d 1331, 1341, 65 USPQ2d 1321, 1326 (Fed. Cir. 2003))); (3) applicant could demonstrate that the specification provides a general guideline and examples sufficient to teach a person skilled in the art when the claim limitation was satisfied (see Marosi, 710 F.2d at 803, 218 USPQ at 292); or (4) applicant could amend the claims to recite the particular structure that accomplishes the function. See MPEP 2173.05(g).
Regarding the prior art reference to Sreenivasulu, the depletion region is enhanced due to the fringe electric field through the spacer. This is providing for the limitation of the depletion region extending beyond the gate structure due to the sidewall spacers, the same structure that the applicant discloses. As it pertains to claim 1 (not claim 12), the distinction from the applicant’s structure is that Sreenivasulu does not teach the first width and the second width being different dimensions. However, this asymmetry of the channel, relative position of the gate structure, and advantages thereof are known in the art as previously provided (i.e. Horch U.S. Patent 8,373,167 - Fig. 4-5; Lin et al. U.S. Patent 8,373,167 - Fig. 2-3; Kumashiro U.S. Patent 6,566,695 - Fig. 3; Lee et al. U.S. Patent Application Publication 2005/0269629 - Fig. 2).
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 2, 4, 7, 8, 10-15, 18, 19 and 21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 and 12 each now recite “semiconductor material underneath the gate structure is devoid of the depletion region” which is not supported in the originally filed disclosure. As explained above in the response to arguments, if the “semiconductor material” is referencing the nanowire fin itself, then it’s unclear how the depletion region (111) both present and not present in the same area at the same time. Claims 2, 4, 7, 8, 10, 11 and 21 include the limitations and do not cure the deficiencies of claim 1. Claims 13-15, 18 and 19 include the limitations and do not cure the deficiencies of claim 12.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 4, 7, 8, 10-15, 18, 19 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 12 each now recite limitations directed towards a depletion region. As explained above in the response to arguments, the structural relationship between the required claim elements of the nanowire fin, source region, drain region, gate structure and/or semiconductor material at any given point in time before, during or after operation is unclear based on the depletion region recitations.
It’s unclear if “semiconductor material” is required to be comprised by the structure or not since it is within a “wherein” clause (see MPEP 2111.04). Even if amended such that the claimed structure comprises “semiconductor material” the recitation lacks structural relationship with required elements comprised by the claimed structure. Does the semiconductor material refer to the nanowire fin or some other unclaimed element? This is also a negative limitation that depends on the presence of a depletion region which is based on the device use (not an inherent structural feature with defined boundaries), i.e. applying a gate voltage or not. It’s unclear as to what structure is required to achieve the intended function and/or when is the function required to be present.
Claims 2, 4, 7, 8, 10, 11 and 21 include the limitations and do not cure the deficiencies of claim 1. Claims 13-15, 18 and 19 include the limitations and do not cure the deficiencies of claim 12.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 12, 18 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sreenivasulu et al. (Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes).
As insofar as Claim 12 is supported and definite, Sreenivasulu teaches in Fig. 1 for example, a structure comprising: a nanowire fin comprising a first region (left half of the fin under spacer) and a second region (right half of the fin under spacer) which is different (in disposition) than the first region (left half of the fin under spacer); and a gate structure (gate electrode and gate dielectric) over the nanowire fin and which spans over both the first region (left half of the fin under spacer) and the second region (right half of the fin under spacer), wherein the first region (left half of the fin under spacer) of the nanowire fin inherently comprises a depletion region that extends beyond an edge of the gate structure (gate electrode and gate dielectric), and semiconductor material (SOI substrate) underneath the gate structure (gate electrode and gate dielectric) is devoid of the depletion region.
As insofar as Claim 18 is supported and definite, Sreenivasulu further teaches wherein the nanowire fin comprises semiconductor material (e.g. silicon).
As insofar as Claim 19 is supported and definite, Sreenivasulu further teaches wherein the gate structure comprises a junctionless field effect transistor (JL n-FinFET).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 4, 7, 8, 11 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sreenivasulu et al. (Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes) in view of Lee et al. (U.S. Patent Application Publication 2005/0269629).
As insofar as Claim 1 is supported and definite, Sreenivasulu teaches in Fig. 1 for example, a structure comprising: a nanowire fin comprising a first width (left half of the fin) adjacent to a source region and a second width (right half of the fin) adjacent to a drain region, the first width and the second width being different in disposition; and a gate structure over the nanowire fin, the gate structure spanning over the first width (left half of the fin) and the second width (right half of the fin) and being between the source region and the drain region, wherein the first region (left half of the fin under spacer) of the nanowire fin inherently comprises a depletion region that extends beyond an edge of the gate structure (gate electrode and gate dielectric), and semiconductor material (SOI substrate) underneath the gate structure (gate electrode and gate dielectric) is devoid of the depletion region.
Sreenivasulu does not explicitly state wherein the first width and the second width are different dimensions.
Lee teaches in Fig. 2, 4 and 10A-11 a structure comprising: a nanowire fin (112 / 200) comprising a first width adjacent to a source region (112s / 202s) and a second width adjacent to a drain region (112d / 202d), the first width and the second width being different dimensions; and a gate structure (110 / 210) over the nanowire fin (112 / 200), the gate structure (110 / 210) spanning over the first width and the second width and being between the source region (112s / 202s) and the drain region (112d / 202d).
Therefore, it would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the shape as taught by Lee for the fin of Sreenivasulu in order to adjust the desired threshold voltage of the transistor, reduce leakage current or increase drive current (par. 9 and 48).
As insofar as Claim 2 is supported and definite, as modified above, Lee further teaches wherein the first width is smaller than the second width. Lee teaches that the narrow width can be adjacent the source region or the drain region. If the narrow width is adjacent the source region, source junction leakage current is lowered. If the narrow width is adjacent the drain region, the drive current may be increased with little or no increase in drain current (par. 48).
As insofar as Claim 4 is supported and definite, as modified above, Lee further teaches wherein the nanowire fin includes a T-shape.
As insofar as Claim 7 is supported and definite, as modified above, Sreenivasulu further teaches wherein the gate structure comprises a junctionless (JL) fin field-effect transistor (FINFET) structure.
As insofar as Claim 8 is supported and definite, as modified above, Lee further teaches wherein the second width is smaller than the first width. Lee teaches that the narrow width can be adjacent the source region or the drain region. If the narrow width is adjacent the source region, source junction leakage current is lowered. If the narrow width is adjacent the drain region, the drive current may be increased with little or no increase in drain current (par. 48).
As insofar as Claim 11 is supported and definite, as modified above, Sreenivasulu further teaches wherein the gate structure includes multiple gate dielectric materials (SiO2 and HfTiO2) over the nanowire fin.
As insofar as Claim 13-15 are supported and definite, Sreenivasulu teaches the limitations of claim 12, but does not explicitly state wherein the first region of the nanowire fin has a width smaller than the second region (claim 13), wherein the first region is adjacent to a source region of the gate structure (claim 14) or wherein the nanowire fin includes a T-shape (claim 15).
Lee teaches in Fig. 2, 4 and 10A-11 for example, a structure comprising: a nanowire fin (112 / 200) comprising a first region (112a) and a second region (112b) which is different than the first region (112a); and a gate structure (110 / 210) over the nanowire fin (112 / 200) and which spans over both the first region (112a) and the second region (112b). Referring to Claim 13, Lee further teaches wherein the first region of the nanowire fin (112 / 200) has a width smaller than the second region. Referring to Claim 14, Lee further teaches wherein the first region is adjacent to a source region of the gate structure (110 / 210). Referring to Claim 15, Lee further teaches wherein the nanowire fin (112 / 200) includes a T-shape.
Therefore, it would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the shape as taught by Lee for the fin of Sreenivasulu in order to adjust the desired threshold voltage of the transistor, reduce leakage current or increase drive current (par. 9 and 48).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Sreenivasulu et al. (Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes) Sreenivasulu et al. (Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes) in view of Lee et al. (U.S. Patent Application Publication 2005/0269629) in further view of Colinge et al. (U.S. Patent Application Publication 2018/0059992).
As insofar as Claim 10 is supported and definite Sreenivasulu in view of Lee teach the limitations of claim 1 wherein the nanowire fin comprises an n-type dopant but does not explicitly state wherein the gate structure comprises a p-type dopant.
Colinge teaches wherein the nanowire fin comprises an n-type dopant and the gate structure comprises a p-type dopant (par. 27 and 45; Fig. 2, 4A-4C and 5F).
Therefore, it would have been obvious to one having ordinary skill in the art before the invention was effectively filed to provide the nanowire fin of Sreenivasulu in view of Lee to comprise an n-type dopant and provide the gate structure to comprise a p-type dopant as taught by Colinge as well-known materials in the art for forming transistors of desired electrical characteristics. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims 10 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Sreenivasulu et al. (Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes) Sreenivasulu et al. (Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes) in view of Lee et al. (U.S. Patent Application Publication 2005/0269629) in further view of Colinge et al. (U.S. Patent Application Publication 2012/0305893).
As insofar as Claims 10 and 21 are supported and definite Sreenivasulu in view of Lee teach the limitations of claim 1 wherein the nanowire fin comprises an n-type dopant but does not explicitly state wherein the gate structure comprises a p-type dopant (claim 10) or n-type dopant (claim 21).
Colinge teaches wherein the nanowire fin comprises an n-type dopant and the gate structure comprises a p-type dopant or n-type dopant (par. 25).
Therefore, it would have been obvious to one having ordinary skill in the art before the invention was effectively filed to provide the nanowire fin of Sreenivasulu in view of Lee to comprise an n-type dopant and provide the gate structure to comprise a p-type dopant or n-type dopant as taught by Colinge in order to achieve postivie or negative operating threshold voltages, as well-known materials in the art for forming transistors of desired electrical characteristics. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Asymmetry of the channel, relative position of the gate structure, and advantages thereof are known in the art as previously provided (Horch U.S. Patent 8,373,167 - Fig. 4-5; Lin et al. U.S. Patent 8,373,167 - Fig. 2-3; Kumashiro U.S. Patent 6,566,695 - Fig. 3) (all previously cited).
Munjal (Evolution of Junctionless Field Effect Transistors in Semiconductor Industry: A Review) (previously cited) teaches the well-known function of junctionless field effect transistors (same as that of Sreenivasulu) and that gate sidewall spacers enhance the depletion region (bottom of page 98, 2nd to last paragraph); see also Fig. 14 and related text on page 101. The space charge region is also known as the depletion region, which can change based on application of a drain voltage.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896
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