DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I and Species II (claims 1, 2, 4, 7-15 and 18-19) in the reply filed on 8 December 2025 is acknowledged. Claims 3, 5, 6, 16, 17 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species or invention, there being no allowable generic or linking claim.
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statement (IDS) filed on 7 August 2023. The references cited on the PTOL 1449 form have been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites “wherein the gate structure comprises a junctionless fin field-effect transistor (FINFET) structure” which does not make sense. According to the applicant’s disclosure, and general knowledge in the art, a gate structure does not comprise a transistor; but rather a transistor comprises a gate structure. Furthermore, it’s unclear as to what limiting structure is required by the added device label as the claim does not recite additional elements or limit any existing antecedent elements in the body of the claim.
Claim 19 recites “wherein the gate structure comprises a junctionless field effect transistor” which does not make sense. According to the applicant’s disclosure, and general knowledge in the art, a gate structure does not comprise a transistor; but rather a transistor comprises a gate structure. Furthermore, it’s unclear as to what limiting structure is required by the added device label as the claim does not recite additional elements or limit any existing antecedent elements in the body of the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 8, 9, 12-15 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (U.S. Patent Application Publication 2005/0269629).
Referring to Claim 1, Lee teaches in Fig. 2, 4 and 10A-11 a structure comprising: a nanowire fin (112 / 200) comprising a first width adjacent to a source region (112s / 202s) and a second width adjacent to a drain region (112d / 202d), the first width and the second width being different dimensions; and a gate structure (110 / 210) over the nanowire fin (112 / 200), the gate structure (110 / 210) spanning over the first width and the second width and being between the source region (112s / 202s) and the drain region (112d / 202d).
Referring to Claim 2, Lee further teaches (par. 11, 15, 17, 51, 67) wherein the first width (adjacent to the source region 112s / 202s) is smaller than the second width (adjacent to the drain region 112d / 202d).
Referring to Claim 4, Lee further teaches wherein the nanowire fin (112 / 200) includes a T-shape.
Referring to Claim 8, Lee further teaches wherein the second width (adjacent to the drain region) is smaller than the first width (adjacent to the source region). Lee teaches that the narrow width can be adjacent the source region or the drain region. If the narrow width is adjacent the source region, source junction leakage current is lowered. If the narrow width is adjacent the drain region, the drive current may be increased with little or no increase in drain current (par. 48).
Referring to Claim 9, Lee further teaches wherein the first width (adjacent to the source region 112s / 202s) of the nanowire fin (112 / 200) comprises a depletion region, as it is overlapped by the gate structure (110 / 210).
Referring to Claim 12, Lee teaches in Fig. 2, 4 and 10A-11 for example, a structure comprising: a nanowire fin (112 / 200) comprising a first region (112a) and a second region (112b) which is different than the first region (112a); and a gate structure (110 / 210) over the nanowire fin (112 / 200) and which spans over both the first region (112a) and the second region (112b).
Referring to Claim 13, Lee further teaches wherein the first region of the nanowire fin (112 / 200) has a width smaller than the second region.
Referring to Claim 14, Lee further teaches wherein the first region is adjacent to a source region of the gate structure (110 / 210).
Referring to Claim 15, Lee further teaches wherein the nanowire fin (112 / 200) includes a T-shape.
Referring to Claim 18, Lee further teaches wherein the nanowire fin (112 / 200) comprises semiconductor material (par. 20-22 and 54).
Claims 12, 18 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (Design of Poly-Si Junctionless Fin-Channel FET with Quantum-Mechanical Drift-Diffusion Models for Sub-10-nm Technology Nodes).
Referring to Claim 12, Lee teaches in Fig. 1 and 2 for example, a structure comprising: a nanowire fin comprising a first region (left half of the fin) and a second region (right half of the fin) which is different (in disposition) than the first region (left half of the fin); and a gate structure over the nanowire fin and which spans over both the first region (left half of the fin) and the second region (right half of the fin).
Referring to Claim 18, Lee further teaches wherein the nanowire fin comprises semiconductor material (poly-si).
As insofar as Claim 19 is definite, Lee further teaches wherein the gate structure comprises a junctionless field effect transistor (JLFinFET).
Claims 12, 18 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sreenivasulu et al. (Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes).
Referring to Claim 12, Sreenivasulu teaches in Fig. 1 for example, a structure comprising: a nanowire fin comprising a first region (left half of the fin) and a second region (right half of the fin) which is different (in disposition) than the first region (left half of the fin); and a gate structure over the nanowire fin and which spans over both the first region (left half of the fin) and the second region (right half of the fin).
Referring to Claim 18, Sreenivasulu further teaches wherein the nanowire fin comprises semiconductor material (e.g. silicon).
As insofar as Claim 19 is definite, Sreenivasulu further teaches wherein the gate structure comprises a junctionless field effect transistor (JL n-FinFET).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 4, 7-9 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sreenivasulu et al. (Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes) in view of Lee et al. (U.S. Patent Application Publication 2005/0269629).
Referring to Claim 1, Sreenivasulu teaches in Fig. 1 for example, a structure comprising: a nanowire fin comprising a first width (left half of the fin) adjacent to a source region and a second width (right half of the fin) adjacent to a drain region, the first width and the second width being different in disposition; and a gate structure over the nanowire fin, the gate structure spanning over the first width (left half of the fin) and the second width (right half of the fin).
Sreenivasulu does not explicitly state wherein the first width and the second width are different dimensions.
Lee teaches in Fig. 2, 4 and 10A-11 a structure comprising: a nanowire fin (112 / 200) comprising a first width adjacent to a source region (112s / 202s) and a second width adjacent to a drain region (112d / 202d), the first width and the second width being different dimensions; and a gate structure (110 / 210) over the nanowire fin (112 / 200), the gate structure (110 / 210) spanning over the first width and the second width and being between the source region (112s / 202s) and the drain region (112d / 202d).
Therefore, it would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the shape as taught by Lee for the fin of Sreenivasulu in order to adjust the desired threshold voltage of the transistor, reduce leakage current or increase drive current (par. 9 and 48).
Referring to Claim 2, as modified above, Lee further teaches wherein the first width is smaller than the second width. Lee teaches that the narrow width can be adjacent the source region or the drain region. If the narrow width is adjacent the source region, source junction leakage current is lowered. If the narrow width is adjacent the drain region, the drive current may be increased with little or no increase in drain current (par. 48).
Referring to Claim 4, as modified above, Lee further teaches wherein the nanowire fin includes a T-shape.
As insofar as Claim 7 is definite, as modified above, Sreenivasulu further teaches wherein the gate structure comprises a junctionless (JL) fin field-effect transistor (FINFET) structure.
Referring to Claim 8, as modified above, Lee further teaches wherein the second width is smaller than the first width. Lee teaches that the narrow width can be adjacent the source region or the drain region. If the narrow width is adjacent the source region, source junction leakage current is lowered. If the narrow width is adjacent the drain region, the drive current may be increased with little or no increase in drain current (par. 48).
Referring to Claim 9, as modified above, Sreenivasulu in view of Lee further teach wherein the first width of the nanowire fin comprises a depletion region.
Referring to Claims 13-15, Sreenivasulu teaches the limitations of claim 12, but does not explicitly state wherein the first region of the nanowire fin has a width smaller than the second region (claim 13), wherein the first region is adjacent to a source region of the gate structure (claim 14) or wherein the nanowire fin includes a T-shape (claim 15).
Lee teaches in Fig. 2, 4 and 10A-11 for example, a structure comprising: a nanowire fin (112 / 200) comprising a first region (112a) and a second region (112b) which is different than the first region (112a); and a gate structure (110 / 210) over the nanowire fin (112 / 200) and which spans over both the first region (112a) and the second region (112b). Referring to Claim 13, Lee further teaches wherein the first region of the nanowire fin (112 / 200) has a width smaller than the second region. Referring to Claim 14, Lee further teaches wherein the first region is adjacent to a source region of the gate structure (110 / 210). Referring to Claim 15, Lee further teaches wherein the nanowire fin (112 / 200) includes a T-shape.
Therefore, it would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the shape as taught by Lee for the fin of Sreenivasulu in order to adjust the desired threshold voltage of the transistor, reduce leakage current or increase drive current (par. 9 and 48).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Patent Application Publication 2005/0269629) in view of Colinge et al. (U.S. Patent Application Publication 2018/0059992).
Referring to claim 10, Lee teaches the limitations of claim 1 wherein the nanowire fin comprises an n-type dopant but does not explicitly state wherein the gate structure comprises a p-type dopant.
Colinge teaches wherein the nanowire fin comprises an n-type dopant and the gate structure comprises a p-type dopant (par. 27 and 45; Fig. 2, 4A-4C and 5F).
Therefore, it would have been obvious to one having ordinary skill in the art before the invention was effectively filed to provide the nanowire channel of Lee to comprise an n-type dopant as taught by Colinge and as provide the gate structure of Lee to comprise a p-type dopant as taught by Colinge as well-known materials in the art for forming transistors of desired electrical characteristics. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Referring to Claim 11, Lee teaches the limitations of claim 1, wherein the gate structure (110 / 210) includes a gate dielectric material (208 / 59) over the nanowire fin (112 / 200) (par. 45 and 63). Lee does not explicitly state wherein the gate structure includes multiple gate dielectric materials over the nanowire fin, per se.
Colinge teaches nanowire finfet transistors wherein the gate structure includes multiple gate dielectric materials (206’) over the nanowire fin (504) (par. 44).
Therefore, it would have been obvious to one having ordinary skill in the art before the invention was effectively filed to provide multiple gate dielectric materials as taught by Colinge as the gate dielectric of the gate structure of Lee as well-known gate insulator materials in the art for forming transistors of desired electrical characteristics. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896