DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I—Claims 1 – 15—in the reply filed on 1 December 2025 is acknowledged.
Claims 16 – 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1 December 2025.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7 August 2023 has been considered by the examiner.
Claim Objections
Claim 2 is objected to because of what appears to be a grammatical error. This claim cites “the plurality of support structures each include”. However, “plurality” itself is singular. The Examiner suggests the alternate language “the plurality of support structures includes”.
Claim 10 is objected to because of what appears to be a grammatical error. This claim cites “each of the plurality of support structures include”. However, “plurality” itself is singular. The Examiner suggests the alternate language “the plurality of support structures includes”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claims 1, 4, 7, 8, 9, 12, 13, 15, and their dependent claims, where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “sacrificial layer” in the above listed claims is used by these claims to mean “a layer that is still present after the fabrication of the associated product”, while the accepted meaning is “a layer that is consumed during the fabrication of the associated product”. The term is indefinite because the specification does not clearly redefine the term.
For the purposes of examination, every instance of “sacrificial layer” that appears in the claims will be interpreted as “first layer”.
Claim 13 recites the limitation "a lower end portion sidewall of the third support structure". However, this limitation was introduced in Claim 9, upon which this claim depends, making the antecedent basis unclear.
For the purposes of examination, this limitation will be interpreted as “the lower end portion sidewall of the third support structure”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 15 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by MITO (US 20230072833 A1).
Regarding Claim 1,
MITO discloses:
A semiconductor device (Fig. 1: 1) comprising:
a stack (Fig. 9: horizontal layers between and including 24 & 22) including a plurality of interlayer insulating layers (Fig. 9: 34s) and a plurality of gate conductive layers (Fig. 9: 23s) alternately stacked;
a channel plug (Fig. 9: MP) formed on a cell region (Fig. 9: MA1) by vertically passing through the stack;
a plurality of support structures (Fig. 9: OSTs, as each is present during the “replacement process”, Par. 101, and helps to suppress “distortion” of the stack, Par. 114) formed on a contact region (Fig. 9: CA) by vertically passing through the stack (Fig. 9: the OSTs vertically pass through the 23s & 34s which are both layers of which the stack is comprised); and
a first layer (Fig. 9: 33) surrounding a lower end portion sidewall of each of the plurality of support structures (Fig. 9: 33 surrounds the vertical sidewall of the lower end portion of the OSTs penetrating 33).
Regarding Claim 2,
MITO discloses:
The semiconductor device of claim 1,
wherein the plurality of support structures each include a first support structure of a line shape (Fig. 9: left OST has the shape of a vertical line in the YZ-plane) and a second support structure of a hole shape (Fig. 9: right OST is formed in a hole—Fig. 19 – 21—thus giving it a “hole shape”).
Regarding Claim 3,
MITO discloses:
The semiconductor device of claim 1,
further comprising:
a contact plug (Fig. 9: C4) formed on the contact region by vertically passing through the stack (Fig. 9: C4 formed on CA by vertically passing through the 34s where the 34s are layers of which the stack is comprised).
Regarding Claim 4,
MITO discloses:
The semiconductor device of claim 3,
wherein the first layer surrounds a lower end portion sidewall of the contact plug (Fig. 9: 33 surrounds the vertical sidewall of the lower end portion of C4 penetrating 33).
Regarding Claim 5,
MITO discloses:
The semiconductor device of claim 1,
further comprising:
a first vertical structure (Fig. 9: SHE) of a line shape (Fig. 9: SHE has the shape of a vertical line in the YZ-plane) passing through an upper portion of the stack (Fig. 9: SHE passes completely through 24 and partially through 35) at a central portion of the cell region (Fig. 8: portion of MA1—in the Y-direction—comprising each SHE); and
a second vertical structure (Fig. 9: portion of SLT in MA1) of a line shape (Fig. 9: SLT has the shape of a vertical line in the YZ-plane) passing through the stack at both ends of the cell region (Fig. 8: SLT is at both ends of MA1 in the Y-direction).
Regarding Claim 6,
MITO discloses:
The semiconductor device of claim 1,
further comprising:
a third vertical structure (Fig. 8 & 9: portion of SLT in CA) extending in a horizontal direction by vertically passing through the stack on the contact region (Fig. 8 & 9: the portion of SLT in CA extends in the X-direction by passing through the stack—as seen by the portion of SLT in MA1—on CA).
Regarding Claim 7,
MITO discloses:
The semiconductor device of claim 6,
wherein the first layer contacts a lower end portion sidewall of the third vertical structure (Fig. 8 & 9: 33 contacts the vertical sidewall of the lower end portion of the portion of SLT in CA penetrating 33 as seen by 33 contacting the vertical sidewall of the lower end portion of the portion of SLT in MA1 penetrating 33).
Regarding Claim 8,
MITO discloses:
The semiconductor device of claim 1,
wherein the first layer includes an oxide layer (Par. 93: 33 may be a “silicon oxide film”).
Regarding Claim 9,
MITO discloses:
A semiconductor device (Fig. 1: 1) comprising:
a stack (Fig. 9: horizontal layers between and including 24 & 22) including a plurality of interlayer insulating layers (Fig. 9: 34s) and a plurality of gate conductive layers (Fig. 9: 23s) alternately stacked;
a channel plug (Fig. 9: MP) formed on a cell region (Fig. 9: MA1) by vertically passing through the stack;
a plurality of support structures (Fig. 9: the OSTs and the portion of OA extending vertically from the topmost surface of the topmost SM to the bottommost surface of the bottommost SM, as each is present during the “replacement process”, Par. 101, and helps to suppress “distortion” of the stack, Par. 114 & 117) formed on a contact region (Fig. 9: CA) by vertically passing through the stack (Fig. 9: the OSTs vertically pass through the 23s & 34s while the portion of OA—as previously described—vertically passes through the 23s where the 23s and the 34s are both layers of which the stack is comprised);
a plurality of contact plugs (Fig. 8: C4s) formed on the contact region by vertically passing through the stack (Fig. 8 & 9: each C4 formed on CA by vertically passing through 34s); and
a first layer (Fig. 9: 33)
contacting a lower end portion sidewall of each of the plurality of support structures (Fig. 9: 33 contacts the vertical sidewall of the lower end portion of the OSTs penetrating 33 as well as the horizontal sidewall of the lower end portion of the portion of OA—as previously described—i.e. the bottommost surface of the bottommost SM of OA)
and a lower end portion sidewall of each of the plurality of contact plugs (Fig. 8 & 9: 33 contacts the vertical sidewall of the lower end portion of each C4 penetrating 33)
and having a line shape by extending in a horizontal direction (Fig. 8 & 9: 33 extends predominantly in a single horizontal direction—the X-direction—giving it a line shape).
Regarding Claim 10,
MITO discloses:
The semiconductor device of claim 9,
wherein each of the plurality of support structures include a first support structure (Fig. 9: the portion of OA, as previously described) and a second support structure of a line shape (Fig. 9: left OST, which has the shape of a vertical line in the YZ-plane), and a third support structure of a hole shape (Fig. 9: right OST, which is formed in a hole—Fig. 19 – 21—thus giving it a “hole shape”).
Regarding Claim 11,
MITO discloses:
The semiconductor device of claim 10,
wherein a width of the first support structure and a width of the second support structure are different from each other (Fig. 9: the full width in the Y-direction of OA and the full width in the Y-direction of left OST are different from each other).
Regarding Claim 12,
MITO discloses:
The semiconductor device of claim 10,
wherein the first layer extends in the horizontal direction along a sidewall of the first support structure and the second support structure (Fig. 8 & 9: 33 extends in the X-direction along the vertical sidewall of the first support structure and the second support structure extending in the X-direction).
Regarding Claim 13,
MITO discloses:
The semiconductor device of claim 10,
wherein the first layer surrounds the lower end portion sidewall of the third support structure (Fig. 8 & 9: 33 surrounds the lower end portion sidewall—as previously described—of the right OST).
Regarding Claim 14,
MITO discloses:
The semiconductor device of claim 9,
further comprising:
a vertical structure (Fig. 8 & 9: portion of SLT in CA) extending in the horizontal direction by passing through the stack on the contact region (Fig. 8 & 9: the portion of SLT in CA extends in the X-direction by passing through the stack—as seen by the portion of SLT in MA1—on CA).
Regarding Claim 15,
MITO discloses:
The semiconductor device of claim 14,
wherein the first layer extends along a lower end portion sidewall of the vertical structure (Fig. 8 & 9: 33 extends along the vertical sidewall of the lower end portion of the portion of SLT in CA penetrating 33 as seen by 33 extending along the vertical sidewall of the lower end portion of the portion of SLT in MA1 penetrating 33).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview—preferably at 4 P.M. (EST)—applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898