DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding the objections to the claims in the Office Action filed 11 February 2026, Applicant’s amendments in the reply filed 11 May 2026 are acknowledged and overcome the associated objections. As such, the associated objections are withdrawn.
Regarding the rejections to the claims under 35 U.S.C. 112(b) in the Office Action filed 11 February 2026, Applicant’s amendments in the reply filed 11 May 2026 are acknowledged and overcome the associated rejections. As such, the associated rejections are withdrawn.
Applicant’s arguments in the reply filed 11 May 2026 against the rejections of these claims under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) in the Office Action filed 11 February 2026 are acknowledged and have been fully considered but are moot in light of the new grounds of rejection based on the newly cited reference SHIMOMURA.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 3, 5 – 6, & 8 are rejected under 35 U.S.C. 103 as being unpatentable over MITO (US 20230072833 A1) in view of SHIMOMURA (US 20220352196 A1).
Regarding Claim 1,
MITO discloses:
A semiconductor device (Fig. 1: 1) comprising:
a stack (Fig. 9: horizontal layers between and including 24 & 22) including a plurality of interlayer insulating layers (Fig. 9: 34s) and a plurality of gate conductive layers (Fig. 9: 23s) alternately stacked;
a channel plug (Fig. 9: MP) formed on a cell region (Fig. 9: MA1) by vertically passing through the stack;
a plurality of support structures (Fig. 9: OSTs, as each is present during the “replacement process”, Par. 101, and helps to suppress “distortion” of the stack, Par. 114) formed on a contact region (Fig. 9: CA) by vertically passing through the stack (Fig. 9: the OSTs vertically pass through the 23s & 34s which are both layers of which the stack is comprised); and
MITO does not disclose:
a first layer surrounding a lower end portion sidewall of each of the plurality of support structures,
wherein the first layer extends vertically through at least one interlayer insulating layer disposed at a lowermost portion among the plurality of interlayer insulating layers and at least one gate conductive layer disposed at a lowermost portion among the plurality of gate conductive layers.
SHIMOMURA discloses:
a first layer (Fig. 23A: 52’) surrounding a lower end portion sidewall (Fig. 23A: from 116 to the bottommost 46) of each of the plurality of support structures (Fig. 23A: 20),
wherein the first layer (Fig. 23A: 52’) extends vertically through at least one interlayer insulating layer (Fig. 23A: 32) disposed at a lowermost portion among the plurality of interlayer insulating layers and at least one gate conductive layer (Fig. 23A: 46) disposed at a lowermost portion among the plurality of gate conductive layers.
(As seen in Fig. 23A, 52’ extends vertically through each 32 and 46, including those disposed at a lowermost portion among the plurality of 32s and 46s.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of MITO with those of SHIMOMURA such that the plurality of the support structures of MITO comprise the multi-layer configuration of the plurality of the support structures of SHIMOMURA to enable a first layer surrounding a lower end portion sidewall of each of the plurality of support structures, wherein the first layer extends vertically through at least one interlayer insulating layer disposed at a lowermost portion among the plurality of interlayer insulating layers and at least one gate conductive layer disposed at a lowermost portion among the plurality of gate conductive layers in MITO according to the teachings of SHIMOMURA for the further advantage of added protection against short circuiting the device during fabrication, SHIMOMURA Par. 232. Further still, SHIMOMURA discloses said support structures having “a larger horizontal cross-sectional size” may still further protect against the same issue, Par. 232, where the chosen embodiment of SHIMOMURA in Fig. 23A and 23B shows the support structures may be elongated—providing said larger horizontal cross-sectional size—similar to the geometry of the support structures of MITO as opposed to being confined to only cylindrical shapes.
Regarding Claim 2,
MITO discloses:
The semiconductor device of claim 1,
wherein the plurality of support structures each includes a first support structure of a line shape (Fig. 9: left OST has the shape of a vertical line in the YZ-plane) and a second support structure of a hole shape (Fig. 9: right OST is formed in a hole—Fig. 19 – 21—thus giving it a “hole shape”).
Regarding Claim 3,
MITO discloses:
The semiconductor device of claim 1,
further comprising:
a contact plug (Fig. 9: C4) formed on the contact region by vertically passing through the stack (Fig. 9: C4 formed on CA by vertically passing through the 34s where the 34s are layers of which the stack is comprised).
Regarding Claim 5,
MITO discloses:
The semiconductor device of claim 1,
further comprising:
a first vertical structure (Fig. 9: SHE) of a line shape (Fig. 9: SHE has the shape of a vertical line in the YZ-plane) passing through an upper portion of the stack (Fig. 9: SHE passes completely through 24 and partially through 35) at a central portion of the cell region (Fig. 8: portion of MA1—in the Y-direction—comprising each SHE); and
a second vertical structure (Fig. 9: portion of SLT in MA1) of a line shape (Fig. 9: SLT has the shape of a vertical line in the YZ-plane) passing through the stack at both ends of the cell region (Fig. 8: SLT is at both ends of MA1 in the Y-direction).
Regarding Claim 6,
MITO discloses:
The semiconductor device of claim 1,
further comprising:
a third vertical structure (Fig. 8 & 9: portion of SLT in CA) extending in a horizontal direction by vertically passing through the stack on the contact region (Fig. 8 & 9: the portion of SLT in CA extends in the X-direction by passing through the stack—as seen by the portion of SLT in MA1—on CA).
Regarding Claim 8,
MITO does not disclose:
The semiconductor device of claim 1,
wherein the first layer includes an oxide layer.
SHIMOMURA discloses:
wherein the first layer (Fig. 23A: 52’) includes an oxide layer (Par. 100).
Allowable Subject Matter
Claims 4 & 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 4,
The closest prior art is MITO in view of SHIMOMURA, which discloses the claimed invention up to but not including the first layer surrounding a lower end portion sidewall of the contact plug. While MITO in view of SHIMOMURA does teach the claimed first layer, MITO in view of SHIMOMURA does not teach or suggest said first layer is anywhere within the claimed invention beyond immediately surrounding the claimed plurality of support structures.
Regarding Claim 7,
The closest prior art is MITO in view of SHIMOMURA, which discloses the claimed invention up to but not including the first layer contacting a lower end portion sidewall of the third vertical structure. While MITO in view of SHIMOMURA does teach the claimed first layer, MITO in view of SHIMOMURA does not teach or suggest said first layer is anywhere within the claimed invention beyond immediately surrounding the claimed plurality of support structures.
Claims 9 – 15 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 9,
The closest prior art is MITO in view of SHIMOMURA, which discloses the claimed invention up to but not including the first layer contacting a lower end portion sidewall of each of the plurality of contact plugs. While MITO in view of SHIMOMURA does teach the claimed first layer, MITO in view of SHIMOMURA does not teach or suggest said first layer is anywhere within the claimed invention beyond immediately surrounding the claimed plurality of support structures.
Regarding Claims 10 – 15,
These claims are allowed based on their dependency upon Claim 9.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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