DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 07/06/2026 has been accepted and entered. Claims 1-10 and 19-28 remain pending in this application. Applicant’s amendments to the Claims have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed on 04/06/2026.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2 and 19-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 5-9 of copending Application No. 18/360,459 Roy et al. (US 20240055257 A1-Roy57). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-2 of copending Application No. 18/360,459 teach each limitation of claims 1-2 and 19-20. See below table.
Application 18/231,176 Joshi et al. (US20240055256A1-Joshi56)
Application 18/360,459 Roy et al. (US 20240055257 A1-Roy57)
Claim 1
A method, comprising:
providing a crystalline silicon carbide semiconductor substrate;
depositing a metallic contact material layer onto the crystalline silicon carbide semiconductor substrate; and
irradiating, with a thermal annealing laser beam,
at least a part of the crystalline silicon carbide semiconductor substrate and
at least a part of the metallic contact material layer
to generate a contact phase portion, comprising a ternary phase of a metal, a metalloid, and carbon
at an interface of the metallic contact material layer and the crystalline silicon carbide semiconductor substrate.
Claim 1
A method for manufacturing a contact on a silicon carbide substrate, the method comprising:
providing a crystalline silicon carbide substrate; modifying a crystal structure in a surface area of the crystalline silicon carbide substrate such that a carbon-enriched silicon carbide portion is generated in the surface area;
forming a contact layer on the crystalline silicon carbide substrate by depositing a metallic contact material onto the surface area comprising the carbon-enriched silicon carbide portion; and
thermal annealing
at least a part of the carbon-enriched silicon carbide portion of the crystalline silicon carbide substrate and
at least a part of the contact layer, such that a ternary metallic phase portion comprising at least the metallic contact material, silicon, and carbon is generated.
Claim 1
irradiating,
with a thermal annealing laser beam
Claim 2
The method of claim 1,
wherein the modifying comprises
irradiating a surface area of the crystalline silicon carbide substrate with at least one first thermal annealing laser beam.
Claim 2
The method of claim 1,
wherein the contact phase portion comprises a silicon.
Claim 1
A method for manufacturing a contact on a silicon carbide substrate, the method comprising:
providing a crystalline silicon carbide substrate; modifying a crystal structure in a surface area of the crystalline silicon carbide substrate such that a carbon-enriched silicon carbide portion is generated in the surface area;
forming a contact layer on the crystalline silicon carbide substrate by depositing a metallic contact material onto the surface area comprising the carbon-enriched silicon carbide portion; and
thermal annealing
at least a part of the carbon-enriched silicon carbide portion of the crystalline silicon carbide substrate and
at least a part of the contact layer, such that a ternary metallic phase portion comprising at least the metallic contact material, silicon, and carbon is generated.
Claim 19
A method, comprising:
providing a crystalline silicon carbide semiconductor substrate;
depositing a metallic contact material layer onto the crystalline silicon carbide semiconductor substrate; and
irradiating
at least a part of the crystalline silicon carbide semiconductor substrate and
at least a part of the metallic contact material layer
to generate a contact phase portion, comprising a ternary phase of a metal, a metalloid, and carbon,
at an interface of the metallic contact material layer and the crystalline silicon carbide semiconductor substrate.
Claim 1
A method for manufacturing a contact on a silicon carbide substrate, the method comprising:
providing a crystalline silicon carbide substrate;
modifying a crystal structure in a surface area of the crystalline silicon carbide substrate such that a carbon-enriched silicon carbide portion is generated in the surface area;
forming a contact layer on the crystalline silicon carbide substrate by depositing a metallic contact material onto the surface area comprising the carbon-enriched silicon carbide portion; and
thermal annealing
at least a part of the carbon-enriched silicon carbide portion of the crystalline silicon carbide substrate and
at least a part of the contact layer, such that a ternary metallic phase portion comprising at least the metallic contact material, silicon, and carbon is generated.
Claim 20
The method of claim 19,
wherein the contact phase portion comprises silicon.
Claim 1
A method for manufacturing a contact on a silicon carbide substrate, the method comprising:
providing a crystalline silicon carbide substrate; modifying a crystal structure in a surface area of the crystalline silicon carbide substrate such that a carbon-enriched silicon carbide portion is generated in the surface area;
forming a contact layer on the crystalline silicon carbide substrate by depositing a metallic contact material onto the surface area comprising the carbon-enriched silicon carbide portion; and
thermal annealing
at least a part of the carbon-enriched silicon carbide portion of the crystalline silicon carbide substrate and
at least a part of the contact layer, such that a ternary metallic phase portion comprising at least the metallic contact material, silicon, and carbon is generated.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 9, 19-21, 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26).
Regarding claim 1, Okumura51 discloses a method ([0025] L1), comprising:
providing a crystalline silicon carbide semiconductor substrate (Providing a crystalline silicon carbide semiconductor 1-Fig 4A, [0030] L 5, [0025] L1-9);
depositing a metallic contact material layer onto the crystalline silicon carbide semiconductor substrate (depositing a metallic contact material layer 110-Fig 4B, [0025] L1-9, [0049]); and
irradiating, with a thermal annealing laser beam (irradiating with a thermal annealing using laser beam 50 at least a part of the crystalline silicon carbide semiconductor substrate 1 and a part of the metallic material layer 110 to generate a contact phase portion at an interface of metallic contact material layer 110 and the crystalline silicon carbide semiconductor substrate 1-Fig 4C, Fig 6a, Fig 6B , [0051] L1-10),
at least a part of the crystalline silicon carbide semiconductor substrate (irradiating with a thermal annealing using laser beam 50 at least a part of the crystalline silicon carbide semiconductor substrate 1 and a part of the metallic material layer 110 to generate a contact phase portion at an interface of metallic contact material layer 110 and the crystalline silicon carbide semiconductor substrate 1-Fig 4C, Fig ^a, Fig 6B , [0051] L1-10) and
at least a part of the metallic contact material layer ((irradiating with a thermal annealing using laser beam 50 at least a part of the crystalline silicon carbide semiconductor substrate 1 and a part of the metallic material layer 110 to generate a contact phase portion at an interface of metallic contact material layer 110 and the crystalline silicon carbide semiconductor substrate 1-Fig 4C, Fig ^a, Fig 6B , [0051] L1-10)
to generate a contact phase portion at an interface of the metallic contact material layer and the crystalline silicon carbide semiconductor substrate ( generating contact phase portion 11a at the interface 1b-Fig 6A, Fig 6B, [0051] L1-10).
Okumura51 does not disclose a method comprising
to generate a contact phase portion, comprising a ternary phase of a metal, a metalloid, and carbon.
Seki26 teaches a method (Title) comprising
to generate a contact phase portion, comprising a ternary phase of a metal, a metalloid, and carbon (to form so produce a contact phase portion/ ohmic electrode layer, comprising a ternary mixed film that includes Ti, Si, and C so comprising a ternary phase of a metal, a metalloid, and carbon-Abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Okumura51, as taught by Seiki26 for the purpose of improving ohmic electrode layer surface smoothness and its ohmic characteristic (Seki26:[0013]).
Regarding claim 2, Okumura51 and Seki26 combination discloses all the elements of claim 1, as noted above.
Okumura51 further discloses a method ([0025] L1)
wherein the contact phase portion comprises silicon (forming an alloy layer 11 of at least one of metal silicide and metal carbide so the contact phase portion 11a comprise a metal, silicon, and carbon-[0037] L2-9).
Regarding claim 3, Okumura51 and Seki26 combination discloses all the elements of claim 2, as noted above.
Okumura51 further discloses a method ([0025] L1)
wherein the metal is a transition metal comprising at least one of titanium, molybdenum, zirconium, niobium, hafnium, tantalum, vanadium, chromium, or tungsten (a metal forming the drain electrode 11, nickel (Ni), molybdenum (Mo), titanium (Ti), tungsten (W), niobium (Nb), tantalum (Ta), or the like-[0038] L1-6).
Regarding claim 9, Okumura51 and Seki26 combination discloses all the elements of claim 1, as noted above.
Okumura51 further discloses a method ([0025] L1)
wherein providing a crystalline silicon carbide semiconductor substrate comprises at least one of thinning or grinding a silicon carbide semiconductor wafer (Grinding the crystalline silicon carbide semiconductor substrate 1-[0048] L1-4).
Regarding claim 19, Okumura51 discloses a method ([0025] L1) , comprising:
providing a crystalline silicon carbide semiconductor substrate (Providing a crystalline silicon carbide semiconductor 1-Fig 4A, [0030] L 5, [0025] L1-9);
depositing a metallic contact material layer onto the crystalline silicon carbide semiconductor substrate (depositing a metallic contact material layer 110-Fig 4B, [0025] L1-9, [0049]); and
irradiating (irradiating with a thermal annealing using laser beam 50 at least a part of the crystalline silicon carbide semiconductor substrate 1 and a part of the metallic material layer 110 to generate a contact phase portion at an interface of metallic contact material layer 110 and the crystalline silicon carbide semiconductor substrate 1-Fig 4C, Fig 6a, Fig 6B , [0051] L1-10),
at least a part of the crystalline silicon carbide semiconductor substrate (irradiating with a thermal annealing using laser beam 50 at least a part of the crystalline silicon carbide semiconductor substrate 1 and a part of the metallic material layer 110 to generate a contact phase portion at an interface of metallic contact material layer 110 and the crystalline silicon carbide semiconductor substrate 1-Fig 4C, Fig ^a, Fig 6B , [0051] L1-10) and
at least a part of the metallic contact material layer (irradiating with a thermal annealing using laser beam 50 at least a part of the crystalline silicon carbide semiconductor substrate 1 and a part of the metallic material layer 110 to generate a contact phase portion at an interface of metallic contact material layer 110 and the crystalline silicon carbide semiconductor substrate 1-Fig 4C, Fig 6A, Fig 6B , [0051] L1-10)
to generate a contact phase portion at an interface of the metallic contact material layer and the crystalline silicon carbide semiconductor substrate ( generating contact phase portion 11a at the interface 1b-Fig 6A, Fig 6B, [0051] L1-10).
Okumura51 does not disclose a method comprising
to generate a contact phase portion, comprising a ternary phase of a metal, a metalloid, and carbon.
Seki26 teaches a method (Title) comprising
to generate a contact phase portion, comprising a ternary phase of a metal, a metalloid, and carbon (to form so produce a contact phase portion/ ohmic electrode layer, comprising a ternary mixed film that includes Ti, Si, and C so comprising a ternary phase of a metal, a metalloid, and carbon-Abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Okumura51, as taught by Seiki26 for the purpose of improving ohmic electrode layer surface smoothness and its ohmic characteristic (Seki26:[0013]).
Regarding claim 20, Okumura51 and Seki26 combination discloses all the elements of claim 19, as noted above.
Okumura51 further discloses a method ([0025] L1)
wherein the contact phase portion comprises silicon (forming an alloy layer 11 of at least one of metal silicide and metal carbide so the contact phase portion 11a comprise a metal, silicon, and carbon-[0037] L2-9).
Regarding claim 21, Okumura51 and Seki26 combination discloses all the elements of claim 19, as noted above.
Okumura51 further discloses a method ([0025] L1)
wherein the metal is a transition metal comprising at least one of titanium, molybdenum, zirconium, niobium, hafnium, tantalum, vanadium, chromium, or tungsten (a metal forming the drain electrode 11, nickel (Ni), molybdenum (Mo), titanium (Ti), tungsten (W), niobium (Nb), tantalum (Ta), or the like-[0038] L1-6).
Regarding claim 25, Okumura51 and Seki26 combination discloses all the elements of claim 19, as noted above.
Okumura51 further discloses a method ([0025] L1)
wherein providing a crystalline silicon carbide semiconductor substrate comprises at least one of thinning or grinding a silicon carbide semiconductor wafer (Grinding the crystalline silicon carbide semiconductor substrate 1-[0048] L1-4).
Claim(s) 4-5 , 7, 22-23, and 27is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), and further in view of Kushibe et al. (JP 2003101038 A-Kushibe38 from IDS with Annotated Machine translation).
Regarding claim 4, Okumura51 and Seki26 combination discloses all the elements of claim 1, as noted above.
Okumura51 and Seki26 combination does not disclose a method
wherein the contact phase portion comprises grains comprising a crystal structure having a lattice constant similar or identical to a lattice constant of the crystalline silicon carbide semiconductor substrate.
Kushibe38 teaches a method
wherein the contact phase portion comprises grains comprising a crystal structure having a lattice constant similar or identical to a lattice constant of the crystalline silicon carbide semiconductor substrate (having little lattice mismatch so having similar lattice constant-[Description] [0005] page 2 L25-27, [Description] [0005] page 3 L27-29).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Okumura51 in view of Seki26, as taught by Kushibe38 for the purpose of preventing a large number of dislocations to occur near the interface between the substrate and the electrode material when subjected to heat cycle (Kushibe38: [Description] [0005] page 2 L17-20, [Description] [0005] page 3 L15-17).
Regarding claim 5, Okumura51 and Seki26 combination discloses all the elements of claim 1, as noted above.
Okumura51 further discloses a method
wherein the contact phase portion (11-Fig2) comprises a layer of grains (Layer of grain 11a and 11b of layer 11-Fig 2),
Okumura51 and Seki26 combination does not disclose a method
wherein at least some of the grains of the layer have a hexagonal crystal structure having a lattice constant similar or identical to a lattice constant of the crystalline silicon carbide semiconductor substrate.
Kushibe38 teaches a method
wherein at least some of the grains of the layer have a hexagonal crystal structure having a lattice constant similar or identical to a lattice constant of the crystalline silicon carbide semiconductor substrate (functional element has been interpretated as the contact phase portion which is provided with a SiC layer, which has a c-axis surface of hexagonal crystal structure having similar lattice constant-[Abstract] §SOLUTION, [Description] [0005] page 3 L27-29) .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Okumura51 in view of Seki26, as taught by Kushibe38 for the purpose of preventing a large number of dislocations to occur near the interface between the substrate and the electrode material when subjected to heat cycle (Kushibe38: [Description] [0005] page 2 L17-20, [Description] [0005] page 3 L15-17).
Regarding claim 7, Okumura51, Seki26 , and Kushibe38 combination discloses all the elements of claim 5, as noted above.
Okumura51 further discloses a method
wherein at least some of the grains comprise a transition metal carbide crystal structure intercalated with between 0% and 25% silicon (Ohmic contact layer 11 of and NiSi 11a MoC 11b- so a transition metal carbide crystal structure with 25% of silicon-[0053], Fig 2).
Regarding claim 22, Okumura51 and Seki26 combination discloses all the elements of claim 19, as noted above.
Okumura51 and Seki26 combination does not disclose a method
wherein the contact phase portion comprises grains comprising a crystal structure having a lattice constant similar or identical to a lattice constant of the crystalline silicon carbide semiconductor substrate.
Kushibe38 teaches a method
wherein the contact phase portion comprises grains comprising a crystal structure having a lattice constant similar or identical to a lattice constant of the crystalline silicon carbide semiconductor substrate (having little lattice mismatch so having similar lattice constant-[Description] [0005] page 2 L25-27, [Description] [0005] page 3 L27-29).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Okumura51 in view of Seki26, as taught by Kushibe38 for the purpose of preventing a large number of dislocations to occur near the interface between the substrate and the electrode material when subjected to heat cycle (Kushibe38: [Description] [0005] page 2 L17-20, [Description] [0005] page 3 L15-17).
Regarding claim 23, Okumura51 and Seki26 combination discloses all the elements of claim 19, as noted above.
Okumura51 further discloses a method
wherein the contact phase portion (11-Fig2) comprises a layer of grains (Layer of grain 11a and 11b of layer 11-Fig 2),
Okumura51 and Seki26 combination does not disclose a method
wherein at least some of the grains of the layer have a hexagonal crystal structure having a lattice constant similar or identical to a lattice constant of the crystalline silicon carbide semiconductor substrate.
Kushibe38 teaches a method
wherein at least some of the grains of the layer have a hexagonal crystal structure having a lattice constant similar or identical to a lattice constant of the crystalline silicon carbide semiconductor substrate (functional element has been interpretated as the contact phase portion which is provided with a SiC layer, which has a c-axis surface of hexagonal crystal structure having similar lattice constant-[Abstract] §SOLUTION, [Description] [0005] page 3 L27-29) .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Okumura51 in view of Seki26, as taught by Kushibe38 for the purpose of preventing a large number of dislocations to occur near the interface between the substrate and the electrode material when subjected to heat cycle (Kushibe38: [Description] [0005] page 2 L17-20, [Description] [0005] page 3 L15-17).
Regarding claim 27, Okumura51 discloses a method ([0025] L1) , comprising:
providing a crystalline silicon carbide semiconductor substrate (Providing a crystalline silicon carbide semiconductor 1-Fig 4A, [0030] L 5, [0025] L1-9);
depositing a metallic contact material layer onto the crystalline silicon carbide semiconductor substrate (depositing a metallic contact material layer 110-Fig 4B, [0025] L1-9, [0049]); and
irradiating (irradiating with a thermal annealing using laser beam 50 at least a part of the crystalline silicon carbide semiconductor substrate 1 and a part of the metallic material layer 110 to generate a contact phase portion at an interface of metallic contact material layer 110 and the crystalline silicon carbide semiconductor substrate 1-Fig 4C, Fig 6a, Fig 6B , [0051] L1-10),
at least a part of the crystalline silicon carbide semiconductor substrate (irradiating with a thermal annealing using laser beam 50 at least a part of the crystalline silicon carbide semiconductor substrate 1 and a part of the metallic material layer 110 to generate a contact phase portion at an interface of metallic contact material layer 110 and the crystalline silicon carbide semiconductor substrate 1-Fig 4C, Fig ^a, Fig 6B , [0051] L1-10) and
at least a part of the metallic contact material layer ((irradiating with a thermal annealing using laser beam 50 at least a part of the crystalline silicon carbide semiconductor substrate 1 and a part of the metallic material layer 110 to generate a contact phase portion at an interface of metallic contact material layer 110 and the crystalline silicon carbide semiconductor substrate 1-Fig 4C, Fig ^a, Fig 6B , [0051] L1-10)
to generate a contact phase portion
at an interface of the metallic contact material layer and the crystalline silicon carbide semiconductor substrate ( generating contact phase portion 11a at the interface 1b-Fig 6A, Fig 6B, [0051] L1-10).
Okumura51 does not disclose a method comprising
to generate a contact phase portion, comprising a ternary phase
and a crystal structure having a lattice constant similar or identical to a lattice constant of the crystalline silicon carbide semiconductor substrate.
Seki26 teaches a method (Title) comprising
to generate a contact phase portion, comprising a ternary phase (to form so produce a contact phase portion/ ohmic electrode layer, comprising a ternary mixed film that includes Ti, Si, and C so comprising a ternary phase of a metal, a metalloid, and carbon-Abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Okumura51, as taught by Seiki26 for the purpose of improving ohmic electrode layer surface smoothness and its ohmic characteristic (Seki26:[0013]).
Okumura51 and Seki26 combination does not disclose a method
a crystal structure having a lattice constant similar or identical to a lattice constant of the crystalline silicon carbide semiconductor substrate.
Kushibe38 teaches a method
wherein the contact phase portion comprises grains comprising a crystal structure having a lattice constant similar or identical to a lattice constant of the crystalline silicon carbide semiconductor substrate (having little lattice mismatch so having similar lattice constant-[Description] [0005] page 2 L25-27, [Description] [0005] page 3 L27-29).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Okumura51 in view of Seki26, as taught by Kushibe38 for the purpose of preventing a large number of dislocations to occur near the interface between the substrate and the electrode material when subjected to heat cycle (Kushibe38: [Description] [0005] page 2 L17-20, [Description] [0005] page 3 L15-17).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), in view of Kushibe et al. (JP 2003101038 A-Kushibe38 from IDS with Annotated Machine translation), and further in view of Pham et al. (US 20200044031 A1-Pham31 from IDS).
Regarding claim 6, Okumura51, Seki26, and Kushibe38 combination discloses all the elements of claim 5, as noted above.
Okumura51 further discloses a method
wherein the contact phase portion comprises a second layer of grains (First layer of grain 11a and second layer of grain 11b of layer 11-Fig 2).
Okumura51, Seki26, and Kushibe38 combination does not disclose a method
wherein at least some of the grains of the second layer have a hexagonal crystal structure comprising at least a metal, silicon, and carbon in a different stoichiometric ratio than the layer.
Pham31 teaches a method
wherein at least some of the grains of the second layer have a hexagonal crystal structure comprising at least a metal, silicon, and carbon in a different stoichiometric ratio than the layer (contact phase portion 875 comprising a first layer of grains 877a, and a second layer of grains 878a with carbon clusters or graphene, and graphene has a hexagonal crystal structure. Additionally, a concentration of larger graphene grains in 877a being higher than in layer 878a so having different stochiometric ratio-[0005] L13-15, Fig 7B, Fig 8A, Fig 8C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Okumura51 in view of Seki26, and further in view of Kushibe38 , as taught by Pham31 for the purpose of Improving the integrity of the backside contact for thinned SiC power devices (Pham31:[0062]).
Claim(s) 8 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), and further in view of Pham et al. (US 20200044031 A1-Pham31 from IDS).
Regarding claim 8, Okumura51 and Seki26 combination discloses all the elements of claim 1, as noted above.
Okumura51 and Seki26 combination does not disclose a method
wherein the irradiation is adjusted to melt the metallic contact material layer and enable diffusion of metal atoms with the crystalline silicon carbide semiconductor substrate at least partially at the interface.
Pham31 teaches a method
wherein the irradiation is adjusted to melt the metallic contact material layer and enable diffusion of metal atoms with the crystalline silicon carbide semiconductor substrate at least partially at the interface (Rapid Thermal processing or RTP enhanced by using laser at the melting point of Titanium/metallic contact material on SiC substrate so adjusting the irradiation to melt the metallic contact material at the interface- Fig 8A, Fig 8C, [0058] L1-9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Okumura51 in view of Seki26 , as taught by Pham31 for the purpose of Improving the integrity of the backside contact for thinned SiC power devices (Pham31:[0062]).
Regarding claim 24, Okumura51 and Seki26 combination discloses all the elements of claim 19, as noted above.
Okumura51 and Seki26 combination does not disclose a method
wherein the irradiation is adjusted to melt the metallic contact material layer and enable diffusion of metal atoms with the crystalline silicon carbide semiconductor substrate at least partially at the interface.
Pham31 teaches a method
wherein the irradiation is adjusted to melt the metallic contact material layer and enable diffusion of metal atoms with the crystalline silicon carbide semiconductor substrate at least partially at the interface (Rapid Thermal processing or RTP enhanced by using laser at the melting point of Titanium/metallic contact material on SiC substrate so adjusting the irradiation to melt the metallic contact material at the interface- Fig 8A, Fig 8C, [0058] L1-9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Okumura51 in view of Seki26 , as taught by Pham31 for the purpose of Improving the integrity of the backside contact for thinned SiC power devices (Pham31:[0062]).
Claim(s) 10 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), in view of Kushibe et al. (JP 2003101038 A-Kushibe38 from IDS with Annotated Machine translation), and further in view of Pham et al. (US 20200044031 A1-Pham31 from IDS).
Regarding claim 10, Okumura51, Seki26 , and Kushibe38 combination discloses all the elements of claim 5, as noted above.
Okumura51, Seki26 , and Kushibe38 combination does not disclose a method
comprising depositing a second metal layer on the metallic contact material layer.
Pham31 teaches a method
comprising depositing a second metal layer on the metallic contact material layer (Step 316 deposition of a second metal layer/Solder metal 181 on the metallic contact material layer 175-Fig 1A, Fig 3A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Okumura51 in view of Seki26, and further in view of Kushibe38 , as taught by Pham31 for the purpose of Improving the integrity of the backside contact for thinned SiC power devices (Pham31:[0062]).
Regarding claim 28, Okumura51, Seki26 , and Kushibe38 combination discloses all the elements of claim 27, as noted above.
Okumura51, Seki26 , and Kushibe38 combination does not disclose a method
comprising depositing a second metal layer on the metallic contact material layer.
Pham31 teaches a method
comprising depositing a second metal layer on the metallic contact material layer (Step 316 deposition of a second metal layer/Solder metal 181 on the metallic contact material layer 175-Fig 1A, Fig 3A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Okumura51 in view of Seki26, and further in view of Kushibe38 , as taught by Pham31 for the purpose of Improving the integrity of the backside contact for thinned SiC power devices (Pham31:[0062]).
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), , and further in view of Pham et al. (US 20200044031 A1-Pham31 from IDS).
Regarding claim 26, Okumura51 and Seki26 combination discloses all the elements of claim 19, as noted above.
Okumura51 and Seki26 combination does not disclose a method
comprising depositing a second metal layer on the metallic contact material layer.
Pham31 teaches a method
comprising depositing a second metal layer on the metallic contact material layer (Step 316 deposition of a second metal layer/Solder metal 181 on the metallic contact material layer 175-Fig 1A, Fig 3A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Okumura51 in view of Seki26, as taught by Pham31 for the purpose of Improving the integrity of the backside contact for thinned SiC power devices (Pham31:[0062]).
Response to Arguments
Applicant’s arguments see pages 6-13 of Remarks, filed on 07/06/2026 with respect to claim(s) 1-2 and 19-20 nonstatutory double patenting rejection have been considered but are not persuasive. The new added limitation can also be found in the co-pending application as explained above.
Therefore, claim(s) 1-2 and 19-20 stand rejected under nonstatutory double patenting.
Applicant’s arguments see pages 6-13 of Remarks, filed on 07/06/2026 with respect to claim(s) 1-10 and 19-28 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim(s) 1-3, 9, 19-21, 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), as noted above.
Therefore, claim(s) 1-3, 9, 19-21, 25 stand rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26).
Claim(s) 4-5, 7, 22-23, and 27is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), and further in view of Kushibe et al. (JP 2003101038 A-Kushibe38 from IDS with Annotated Machine translation), as noted above.
Therefore, claim(s) 4-5, 7, 22-23, and 27stand rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), and further in view of Kushibe et al. (JP 2003101038 A-Kushibe38 from IDS with Annotated Machine translation).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), in view of Kushibe et al. (JP 2003101038 A-Kushibe38 from IDS with Annotated Machine-translation), and further in view of Pham et al. (US 20200044031 A1-Pham31 from IDS), as noted above.
Therefore, claim(s) 6 stands rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), in view of Kushibe et al. (JP 2003101038 A-Kushibe38 from IDS with Annotated Machine translation), and further in view of Pham et al. (US 20200044031 A1-Pham31 from IDS).
Claim(s) 8 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), and further in view of Pham et al. (US 20200044031 A1-Pham31 from IDS), as noted above.
Therefore claim(s) 8 and 24 stand rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), and further in view of Pham et al. (US 20200044031 A1-Pham31 from IDS).
Claim(s) 10 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), in view of Kushibe et al. (JP 2003101038 A-Kushibe38 from IDS with Annotated Machine translation), and further in view of Pham et al. (US 20200044031 A1-Pham31 from IDS), as noted above.
Therefore, claim(s) 10 and 28 stand rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), in view of Kushibe et al. (JP 2003101038 A-Kushibe38 from IDS with Annotated Machine translation), and further in view of Pham et al. (US 20200044031 A1-Pham31 from IDS).
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), , and further in view of Pham et al. (US 20200044031 A1-Pham31 from IDS), as noted above.
Therefore, claim(s) 26 stands rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (US 20210111251 A1-Okumura51 from IDS) in view of Seki et al. (US 20110287626 A1-Seki26), , and further in view of Pham et al. (US 20200044031 A1-Pham31 from IDS).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 08/28/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights