Attorney’s Docket Number: IE2022050271US0
Filing Date: 08/08/2023
Claimed Foreign Priority Date: 09/08/2022 (KR 10-2022-0114413)
Applicants: Ahn et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Amendment filed on 12/30/2025.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
Applicant's amendment filed on 12/30/2025, responding to the Office action mailed on 10/02/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant cancelled claim 19 and added new claim 21. Accordingly, pending in this application are claims 1-18 and 20-21.
Response to Amendment
Applicant’s amendments to the Claims have overcome the claim rejections under 35 U.S.C. 102 and 35 U.S.C. 103, as previously formulated in the Non-Final Office action mailed on 10/02/2025. Accordingly, all previous claim rejections are hereby withdrawn, and new grounds of rejection are presented below, as necessitated by applicant’s amendment to the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US2022/0157831).
Regarding Claim 1, Baek (see, e.g., Figs. 3B and 4B) shows most aspects of the instant invention, including vertical memory device, comprising:
- a lower pad pattern (e.g., peripheral circuit lines 104) disposed on a substrate (e.g., substrate 100)
- a cell stack structure (e.g., cell array structure CS) disposed on the lower pad pattern, wherein the cell stack structure includes first insulation layers and gate patterns (e.g., inter-electrode dielectric layers 12 and electrodes layers EL) alternately and repeatedly stacked, wherein the cell stack structure extends in a first direction (e.g., D2) parallel to an upper surface of the substrate, and has a stepped shape (e.g., connection region CNR)
- a through cell contact including a first through portion and a first protrusion (e.g., cell contacts CC including a columnar part CP1 and connection part CP2 laterally protruding from CP1), wherein the first through portion extends in a vertical direction and passes through a portion of the cell stack structure having the stepped shape, and wherein the first protrusion protrudes from the first through portion and contacts a sidewall of an uppermost gate pattern, of the gate patterns, that is adjacent to the first through portion
- a first insulation pattern (e.g., contact dielectric pattern 16) at least partially surrounding a sidewall, of the first through portion, that is positioned below the first protrusion
- wherein the first insulation pattern is longer than the first protrusion in a horizontal direction from the first through portion (see, e.g., Par. [0106]: W2 greater than W1)
- wherein a vertical thickness of the first protrusion of the through cell contact is greater than a maximum vertical thickness of the uppermost gate pattern that contacts the first protrusion (see, e.g., Fig. 4B: vertical thickness of CP2 vs. maximum vertical thickness of PP/EL)
- wherein an upper surface of the first protrusion of the through cell contact is higher than an uppermost surface of the uppermost gate pattern that contacts the first protrusion, and a lower surface of the first protrusion of the through cell contact is lower than a lower surface of the uppermost gate pattern that contacts the first protrusion (see, e.g., Fig. 4B: upper and lower surfaces of CP2 vs. upper and lower surfaces of PP/EL)
However, Baek (see, e.g., Fig. 4B) shows that a sidewall of PP and a sidewall of CP2 contacting the sidewall of PP have vertical profiles. Therefore, Baek shows all aspects of the instant invention (see, e.g., paragraph 7 above), except: wherein along the vertical direction, each of the sidewall of the uppermost gate pattern and a sidewall of the first protrusion that contacts the sidewall of the uppermost gate pattern has an angular profile with an upper oblique side and a lower oblique side with respect to the vertical direction.
Nonetheless, it is noted that the specification fails to provide teachings about the criticality of said sidewall profiles being shaped as claimed or any unexpected results therefrom. As such, absent any criticality, this limitation is only considered to be an obvious modification of the sidewall profile shape disclosed by Baek, as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular sidewall profile shape claimed by applicant is nothing more than one of numerous sidewall profile shapes that a person having ordinary skill in the art will find obvious to provide as a matter of choice or using routine experimentation based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Regarding Claim 2, Baek (see, e.g., Figs. 3B and 4B) shows that the first insulation pattern (e.g., 16) contacts a sidewall of a gate pattern, of the gate patterns, that is disposed below the uppermost gate pattern.
Regarding Claim 3, Baek (see, e.g., Figs. 3B and 4B) shows that the vertical thickness of the uppermost gate pattern that contacts the first protrusion is greater than a vertical thickness of a gate pattern, of the gate patterns, disposed below the uppermost gate pattern.
Regarding Claim 4, Baek (see, e.g., Figs. 3B and 4B) shows a positive horizontal distance between a contacting portion that is between the first protrusion and the uppermost gate pattern and a contacting portion that is between the first insulation pattern and a gate pattern, of the gate patterns, disposed below the uppermost gate pattern.
Furthermore, Baek (see, e.g., Par. [0106]-[0108]) discloses that contact dielectric pattern 16 extends between the cell contact CC and each of the electrodes layers EL formed under the uppermost gate pattern EL, and has a horizonal distance such that connection part CP2 of CC does not overlap the electrode parts EP of the electrode layers EL, to minimize interference between the electrodes EL and prevent breakdown voltage drop, thus prohibiting operating errors and increasing reliability of the three-dimensional semiconductor memory device. Therefore, Baek recognizes that the lateral dimension of contact dielectric pattern 16 is a result effective variable.
Accordingly, the specific horizontal distance between the contacting portions claimed by the applicant, i.e., being about 15 nm or more, is only considered to be the “optimum” horizontal distance disclosed by Baek that a person having ordinary skill in the art would have been able to obtain using routine experimentation based, among other things, on needs for reducing coupling/crosstalk between the cell contact and each of the unconnected gate electrodes (see In re Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the horizontal dimensions of the insulation pattern are chosen such that the lower gate patterns are “pushed back” far enough from the cell contact to avoid overlap, thus preventing or mitigating interference/parasitic coupling, as already suggested by Baek.
Therefore, Baek teaches that a horizontal distance between a contacting portion that is between the first protrusion and the uppermost gate pattern and a contacting portion that is between the first insulation pattern and a gate pattern, of the gate patterns, disposed below the uppermost gate pattern is about 15 nm or more.
Regarding Claim 5, Baek (see, e.g., Fig. 4B and 4C) shows that the first protrusion of the through cell contact (e.g., CP2) has annular shape surrounding the first through portion.
Regarding Claim 6, Baek (see, e.g., Figs. 3B and 4B) shows that at least a portion of a bottom surface of the uppermost gate pattern (e.g., uppermost EL) that contacts the through cell contact faces the first insulation pattern (e.g., 16).
Regarding Claim 7, Baek (see, e.g., Figs. 3B and 4B) shows that an end of the first protrusion of the through cell contact (e.g., CP2) contacts the uppermost gate pattern, and a sidewall of the through cell contact contacts an insulation material (e.g., dielectric layer 18).
Regarding Claim 8, Baek (see, e.g., Fig. 4B) shows that the first protrusion of the through cell contact (e.g., CP2) protrudes beyond upper and lower surfaces of the uppermost gate pattern (e.g., PP) that contacts the first protrusion.
Regarding Claim 9, Baek (see, e.g., Fig. 3B) shows that a bottom surface of the through cell contact (e.g., CC) contacts the lower pad pattern (e.g., 104).
Regarding Claim 10, Baek (see, e.g., Figs. 3B and 4B) shows most aspects of the instant invention, including vertical memory device, comprising:
- lower circuit patterns (e.g., peripheral circuit transistors PTR) disposed on a substrate (e.g., substrate 100)
- a lower pad pattern (e.g., peripheral circuit lines 104) electrically connected to the lower circuit patterns
- a base pattern (e.g., cell substrate 10 or source structure SCL) disposed on the lower pad pattern
- a cell stack structure (e.g., cell array structure CS) disposed on the base pattern, wherein the cell stack structure includes first insulation layers and gate patterns (e.g., inter-electrode dielectric layers 12 and electrodes layers EL) alternately and repeatedly stacked, wherein the cell stack structure extends in a first direction (e.g., D2) parallel to an upper surface of the substrate, and having a stepped shape (e.g., connection region CNR)
- a channel structure (e.g., cell vertical pattern VS) extending to the base pattern and passing through the cell stack structure
- an insulating interlayer (e.g., dielectric layer 18) covering the cell stack structure
- a through cell contact including a first through portion and a first protrusion (e.g., cell contacts CC including a columnar part CP1 and connection part CP2 laterally protruding from CP1), wherein the first through portion extends in a vertical direction to the lower pad pattern and passes through the insulating interlayer and a portion having the stepped shape in the cell stack structure, and wherein the first protrusion protrudes from the first through portion and contacts a sidewall of an uppermost gate pattern, of the gate patterns, that is adjacent to the first through portion
- a first insulation pattern (e.g., contact dielectric pattern 16) at least partially surrounding a sidewall, of the first through portion, that is positioned below the first protrusion
- wherein the first insulation pattern has a length in the first direction that is greater than a length, in the first direction, of the first protrusion from the first through portion (see, e.g., Par. [0106]: W2 greater than W1)
- wherein a vertical thickness of the first protrusion of the through cell contact is greater than a maximum vertical thickness of the uppermost gate pattern that contacts the first protrusion (see, e.g., Fig. 4B: vertical thickness of CP2 vs. maximum vertical thickness of PP/EL)
- wherein an upper surface of the first protrusion of the through cell contact is higher than an uppermost surface of the uppermost gate pattern that contacts the first protrusion, and a lower surface of the first protrusion of the through cell contact is lower than a lower surface of the uppermost gate pattern that contacts the first protrusion (see, e.g., Fig. 4B: upper and lower surfaces of CP2 vs. upper and lower surfaces of PP/EL)
However, Baek (see, e.g., Fig. 4B) shows that a sidewall of PP and a sidewall of CP2 contacting the sidewall of PP have vertical profiles. Also, see comments stated above in Par. 8-9 with regards to Claim 1, which are considered repeated here.
Furthermore, Baek (see, e.g., Figs. 3B and 4B) shows a positive horizontal distance between a contacting portion that is between the first protrusion and the uppermost gate pattern and a contacting portion that is between the first insulation pattern and a gate pattern, of the gate patterns, disposed below the uppermost gate pattern. Also, see comments stated above in Par. 13-15 with regards to Claim 4, which are considered repeated here.
Regarding Claim 11, Baek (see, e.g., Fig. 4B) shows wherein a vertical thickness of the first protrusion of the through cell contact is greater than a vertical thickness of the uppermost gate pattern that contacts the first protrusion (see, e.g., Fig. 4B: vertical thickness of CP2 vs. vertical thickness of uppermost PP/EL).
Regarding Claim 12, Baek (see, e.g., Figs. 3B and 4B) shows that the first insulation pattern (e.g., 16) contacts a sidewall of a gate pattern that is disposed below the uppermost gate pattern.
Regarding Claim 13, Baek (see, e.g., Figs. 3B and 4B) shows that a vertical thickness of an uppermost gate pattern that contacts the first protrusion is greater than a vertical thickness of the gate pattern that is disposed below the uppermost gate pattern.
Regarding Claim 14, Baek (see, e.g., Fig. 4B) shows that the first protrusion of the through cell contact (e.g., CP2) protrudes beyond upper and lower surfaces of the uppermost gate pattern (e.g., upper EL/PP) that contacts the first protrusion.
Regarding Claim 15, Baek (see, e.g., Fig. 3B) shows a protective pattern (e.g., dielectric layer 102 or dielectric pattern 8) disposed on the lower pad pattern, and wherein the through cell contact passes through the protective pattern.
Regarding Claim 16, Baek (see, e.g., Par. [0095],[0104]) disclose that electrode layers EL include metal, e.g., tungsten; and that cell contacts CC include metal, e.g., tungsten, copper, or aluminum. Therefore, Baek also shows that the gate patterns include a metal, and the through cell contact includes a metal.
Regarding Claim 17, Baek (see, e.g., Figs. 3B and 4B) shows that an end of the first protrusion of the through cell contact (e.g., CP2) contacts the uppermost gate pattern, and a sidewall of the through cell contact contacts an insulation material (e.g., dielectric layer 18).
Regarding Claim 18, Baek (see, e.g., Figs. 3B and 4B) shows most aspects of the instant invention, including vertical memory device, comprising:
- a cell stack structure (e.g., cell array structure CS) disposed on a substrate (e.g., substrate 100), wherein the cell stack structure includes first insulation layers and gate patterns alternately and repeatedly stacked (e.g., inter-electrode dielectric layers 12 and electrodes layers EL), wherein the cell stack structure has a stepped shape at an edge thereof (e.g., connection region CNR), and wherein a thickness of an uppermost gate pattern (e.g., uppermost EL/PP), of the gate patterns, that is exposed at the edge is greater than that of the gate pattern, of the gate patterns, that is disposed below the uppermost gate pattern (see, e.g., Fig. 4B)
- a through cell contact including a first through portion and a first protrusion (e.g., cell contacts CC including a columnar part CP1 and connection part CP2 laterally protruding from CP1), wherein the first through portion extends in a vertical direction and passes through the cell stack structure, and wherein the first protrusion protrudes from the first through portion and contacts a sidewall of the uppermost gate pattern that is adjacent to the first through portion
- a first insulation pattern (e.g., contact dielectric pattern 16) at least partially surrounding a sidewall, of the first through portion, that is positioned below the first protrusion
- wherein a vertical thickness of the first protrusion of the through cell contact is greater than a maximum vertical thickness of the uppermost gate pattern that contacts the first protrusion (see, e.g., Fig. 4B: vertical thickness of CP2 vs. maximum vertical thickness of PP/EL)
- wherein an upper surface of the first protrusion of the through cell contact is higher than an uppermost surface of the uppermost gate pattern that contacts the first protrusion, and a lower surface of the first protrusion of the through cell contact is lower than a lower surface of the uppermost gate pattern that contacts the first protrusion (see, e.g., Fig. 4B: upper and lower surfaces of CP2 vs. upper and lower surfaces of PP/EL)
However, Baek (see, e.g., Fig. 4B) shows that a sidewall of PP and a sidewall of CP2 contacting the sidewall of PP have vertical profiles. Also, see comments stated above in Par. 8-9 with regards to Claim 1, which are considered repeated here.
Furthermore, Baek (see, e.g., Figs. 3B and 4B) shows a positive horizontal distance between a contacting portion that is between the first protrusion and the uppermost gate pattern and a contacting portion that is between the first insulation pattern and a gate pattern, of the gate patterns, disposed below the uppermost gate pattern. Also, see comments stated above in Par. 13-15 with regards to Claim 4, which are considered repeated here.
Regarding Claim 20, Baek (see, e.g., Fig. 4B) shows that a length of the first protrusion in a horizontal direction is bigger than the horizontal distance between the contacting portion that is between the first protrusion and the uppermost gate pattern and the contacting portion that is between the first insulation pattern and the gate pattern that is disposed below the uppermost gate pattern. Therefore, Baek is silent about said length of the first protrusion being a same as or less than the horizontal distance, as claimed.
However, it is also noted that the specification fails to provide teachings about the criticality of having the length of the first protrusion as claimed, and the courts have held that differences in lengths will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such lengths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed length, and since Baek teaches a length known in the art, it would have been obvious to one of ordinary skill in the art to use the claimed length in the device of Baek.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed length or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimension or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1939 (Fed. Cir. 1990).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US2022/0157831) in view of Kim et al. (US2022/0216151).
Regarding Claim 21, Baek is silent about the through cell contact further including a second protrusion protruding horizontally from an upper end portion of the first through portion. Kim (see, e.g., Figs. 6-7 and Par. [0099],[0104]), on the other hand and in the same field of endeavor, teaches having word line contacts C2 extending through stack structure ST, wherein contacts C2 comprise a vertical portion C2a, a protruding part C2c, and a top portion C2b at an upper end of C2a having a width greater than a width of C2a, wherein C2b implements a broadened contact landing area for contact plugs CP2 formed thereupon.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a second protrusion protruding as claimed in the structure of Baek, because it is known in the semiconductor memory art that word line contacts can be formed with protrusions protruding horizontally from an upper end portion thereof, to implement a broadened contact landing areas for contact plugs formed thereupon, as suggested by Kim, and implementing a known electrical connection structure for its conventional use would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant’s remarks with respect to the claims filed on 12/30/25 have been considered but are moot in view of the new grounds of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references of record disclose vertical memory devices with through cell contacts having a protrusion therefrom, and having aspects similar to the instant inventions.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul whose telephone number is (571) 270-5514. The examiner can normally be reached Monday-Friday 9am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814