DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 08/26/2026, with respect to the rejection(s) of claim(s) 1-5, 7-17 and 19-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an updated prior art search.
Applicant's arguments filed 08/26/2026 with respect to the use of Chen have been fully considered but they are not persuasive. The cited Figure 19 of Chen teaches the package configuration of a redistribution structure disposed between conductive posts and a semiconductor chip. This configuration is well-known and is an obvious swap with the configuration taught by Du. The rejection of record is amended in accordance with Applicant’s amendment to claim 19.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites the limitation “wherein the plurality of conductive posts extend through a first molding layer surrounding the lower buffer chip and electrically connect the first redistribution structure to the upper buffer chip”, which is contrary to the limitation “a first redistribution structure disposed between the lower buffer chip and an upper buffer chip, the first redistribution structure contacting the lower buffer chip and the plurality of conductive posts, the first redistribution structure electrically connecting the lower buffer chip and the plurality of conductive posts to the upper buffer chip” already required by claim 19, from which claim 21 depends. The conductive posts cannot electrically connect the first redistribution structure to the upper buffer chip if the first redistribution structure is already electrically connecting the conductive posts to the upper buffer chip. Correction or clarification is required. If clarifying, please point to the drawing that depicts the claimed limitations of claim 21.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-5, 7 and 11-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Du (US-20240321854-A1) in view of Yu et al. (US-20210066279-A1 – hereinafter Yu), and further in view of Kobayashi (US-20240006389-A1).
Regarding claim 1, Du teaches a semiconductor device (Fig.75 600; ¶0284) comprising:
a first lower buffer chip (Fig.75 6110; ¶0269);
an upper buffer chip (Fig.75 6140; ¶0269) disposed on an upper surface of the first lower buffer chip (6110);
a plurality of conductive posts (Fig.75 6150; ¶0269) spaced apart from the first lower buffer chip (6110) and disposed on a lower surface of the upper buffer chip (6140).
Du does not teach a first memory chip stack structure disposed on the upper buffer chip and including a plurality of first memory chips, and
wherein each of the first lower buffer chip and the upper buffer chip comprises an arithmetic circuit configured to calculate data stored in the plurality of first memory chips
Yu teaches a memory chip stack (Fig.1E MD; ¶0038 of Yu) with a plurality of memory chips (Fig.1E 162; ¶0038 of Yu) disposed on top of an upper buffer chip (Fig.1E 164; ¶0038 of Yu) with a redistribution structure in between (Fig.1E 150; ¶0038 of Yu), the upper buffer chip disposed on top of a lower buffer chip (Fig.1E LD1; ¶0038 of Yu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to dispose the memory chip stack of Yu (MD of Yu) on top of the upper buffer chip of Du (6140 of Du) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of providing memory functionality (¶0038 of Yu) without increasing the horizontal footprint of the package structure.
Du in view of Yu does not teach wherein each of the first lower buffer chip and the upper buffer chip comprises an arithmetic circuit configured to calculate data stored in the plurality of first memory chips.
Kobayashi discloses an arithmetic circuit (¶0057 of Kobayashi) being a well-known type of integrated circuit die, specifically for a processor which is a type of logic die.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include an arithmetic circuit in both the upper (6140 of Du and 164 of Yu) and lower (6110 of Du and LD1 of Yu) buffer chips of Du in view of Yu to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit high speed arithmetic processing in both the upper and lower buffer chips, which are both logic chips, compared to chips that do not have arithmetic circuits such as those relying on software for arithmetic processing.
Regarding claim 2, the aforementioned combination of Du in view of Yu, and further in view of Kobayashi from claim 1 teaches the semiconductor device of claim 1, wherein a horizontal area of the upper buffer chip (6140 of Du) is different from a horizontal area of the first lower buffer chip (6110 of Du).
Regarding claim 3, the aforementioned combination of Du in view of Yu, and further in view of Kobayashi from claim 1 teaches the semiconductor device of claim 1, wherein a horizontal area of the upper buffer chip (6140 of Du) is greater than a horizontal area of the first lower buffer chip (6110 of Du).
Regarding claim 4, the aforementioned combination of Du in view of Yu, and further in view of Kobayashi from claim 1 teaches the semiconductor device of claim 1, wherein the first lower buffer chip (6110 of Du) comprises a first through electrode (Fig.75 6130; ¶0266 of Du) extending in a first direction (vertical direction) perpendicular to the upper surface of the first lower buffer chip (6110 of Du)
The aforementioned combination does not teach the upper buffer chip comprising a second through electrode extending in the first direction.
Yu teaches the upper buffer chip (164 of Yu) comprising through electrodes (Fig.1E 116; ¶0032 of Yu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the upper buffer chip of Du (6140 of Du) to include through electrodes (164 of Yu) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of enabling communication between the previously combined memory stack (MD of Yu) with the lower buffer chip of Du (6110 of Du).
Regarding claim 5, the aforementioned combination of Du in view of Yu, and further in view of Kobayashi from claim 4 teaches the semiconductor device of claim 4, wherein a width of the plurality of conductive posts (6150 of Du) is greater than a width of the first through electrode (6130 of Du) and a width of the second through electrode (164 of Yu).
Regarding claim 7, the aforementioned combination of Du in view of Yu, and further in view of Kobayashi from claim 1 teaches the semiconductor device of claim 1, further comprising:
a second molding layer (Fig.75 6160; ¶0269 of Du) surrounding the upper buffer chip (6140 of Du), and the first memory chip stack structure (MD of Yu).
The aforementioned combination does not teach a first molding layer surrounding the first lower buffer chip and the conductive posts; and
wherein the second molding layer surrounds the first molding layer (610).
An alternative embodiment of Du (Fig.60 of Du) teaches a first molding layer (Fig.60 5160; ¶0215 of Du) that surrounds the first buffer chip (5110 of Du) and the conductive posts (5150 of Du) with the second molding layer (5170 of Du) surrounding the upper buffer chip (5140 of Du) and the first molding layer (5160 of Du).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the two-encapsulant embodiment of the alternative embodiment (Fig.60 of Du) instead of the primary embodiment with only one encapsulant (Fig.75 of Du) to arrive at the claimed invention. This difference is a matter of design choice and does not patentably distinguish claim 7 over claim 1.
Regarding claim 11, the aforementioned combination of Du in view of Yu, and further in view of Kobayashi from claim 1 teaches the semiconductor device of claim 1, wherein the first lower buffer chip (6110 of Du) overlaps a center of the upper buffer chip (6140 of Du) in a first direction (vertical direction) perpendicular to the upper surface of the first lower buffer chip (6110 of Du).
Regarding claim 12, the aforementioned combination of Du in view of Yu, and further in view of Kobayashi from claim 1 teaches the semiconductor device of claim 1.
The aforementioned combination does not teach wherein the first lower buffer chip overlaps an edge portion of the upper buffer chip in a first direction perpendicular to the upper surface of the first lower buffer chip.
Fig.1E of Yu depicts the lower buffer chip (LD1 of Yu) being wider than the upper buffer chip (164 of Yu) and therefore overlapping an edge portion of the upper buffer chip (164 of Yu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the lower buffer chip (6110 of Du) to be wider than the upper buffer chip (6140 of Du) as taught by Yu (Fig.1E of Yu) as a matter of design choice.
Regarding claim 13, the aforementioned combination of Du in view of Yu, and further in view of Kobayashi from claim 1 teaches the semiconductor device of claim 1, further comprising a second redistribution structure (150 of Yu) disposed between the upper buffer chip (6140 of Du) and the first memory chip stack structure (MD of Yu) and configured to connect the upper buffer chip (6140 of Du) to the first memory chip stack structure (MD of Yu).
Regarding claim 14, the aforementioned combination of Du in view of Yu, and further in view of Kobayashi from claim 1 teaches the semiconductor device of claim 1.
The aforementioned combination does not teach the semiconductor device further comprising:
a second lower buffer chip disposed on a lower surface of the upper buffer chip and spaced apart from the first lower buffer chip; and
a second memory chip stack structure disposed on an upper surface of the upper buffer chip and including a plurality of second memory chips, and
wherein each of the second lower buffer chip and the upper buffer chip comprises an arithmetic circuit configured to calculate data stored in the plurality of second memory chips of the second memory chip stack structure.
Yu teaches an alternative embodiment (Fig.3 of Yu) comprising a second lower buffer chip (Fig.3 LD2; ¶0044 of Yu) and multiple memory stacks (Fig.3 MD of Yu), with the second lower buffer chip (LD2 of Yu) spaced apart from the first lower buffer chip (LD1 of Yu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the configuration taught by Figure 3 of Yu including duplicates of previously taught components to arrive at the claimed invention. This modification is obvious because it is a matter of design choice.
Du in view of Yu, and further in view of Kobayashi does not teach wherein each of the second lower buffer chip and the upper buffer chip comprises an arithmetic circuit configured to calculate data stored in the plurality of second memory chips of the second memory chip stack structure.
Kobayashi discloses an arithmetic circuit (¶0057 of Kobayashi) being a well-known type of integrated circuit die, specifically for a processor which is a type of logic die.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include an arithmetic circuit in both the second instance of the upper (6140 of Du and 164 of Yu) and lower (6110 of Du and LD1 of Yu) buffer chips of Du in view of Yu to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit high speed arithmetic processing in both the upper and lower buffer chips, which are both logic chips, compared to chips that do not have arithmetic circuits such as those relying on software for arithmetic processing.
Regarding claim 15, Du teaches a semiconductor package (Fig.75 600; ¶0284) comprising:
a redistribution structure (Fig.75 6180; ¶0275);
a semiconductor device (the chip stack depicted in Fig.75 is a semiconductor device) disposed on the redistribution structure (6180); and
wherein the semiconductor device comprises:
a lower buffer chip (Fig.75 6110; ¶0269) disposed on the redistribution structure (6180);
an upper buffer chip (Fig.75 6140; ¶0269) disposed on an upper surface of the lower buffer chip (6110);
a plurality of conductive posts (Fig.75 6150; ¶0269) spaced apart from the lower buffer chip (6110) and disposed on a lower surface of the upper buffer chip (6140).
Du does not teach a semiconductor chip disposed on the redistribution structure and spaced apart from the semiconductor device in a horizontal direction;
a memory chip stack structure disposed on the upper buffer chip and including a plurality of memory chips, and
wherein each of the lower buffer chip and the upper buffer chip comprises an arithmetic circuit configured to calculate data stored in the plurality of memory chips.
Yu teaches a memory chip stack (Fig.1E MD; ¶0038 of Yu) with a plurality of memory chips (Fig.1E 162; ¶0038 of Yu) disposed on top of an upper buffer chip (Fig.1E 164; ¶0038 of Yu) with a redistribution structure in between (Fig.1E 150; ¶0038 of Yu), the upper buffer chip disposed on top of a lower buffer chip (Fig.1E LD1; ¶0038 of Yu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to dispose the memory chip stack of Yu (MD of Yu) on top of the upper buffer chip of Du (6140 of Du) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of providing memory functionality (¶0038 of Yu) without increasing the horizontal footprint of the package structure.
Du in view of Yu does not teach a semiconductor chip disposed on the redistribution structure and spaced apart from the semiconductor device in a horizontal direction.
Yu teaches an alternative embodiment (Fig.3 of Yu) comprising a second lower buffer chip (Fig.3 LD2; ¶0044 of Yu) and multiple memory stacks (Fig.3 MD of Yu), with the second lower buffer chip (LD2 of Yu) spaced apart from the first lower buffer chip (LD1 of Yu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the configuration taught by Figure 3 of Yu including duplicates of previously taught components to arrive at the claimed invention. This modification is obvious because it is a matter of design choice.
Du in view of Yu does not teach wherein each of the lower buffer chip and the upper buffer chip comprises an arithmetic circuit configured to calculate data stored in the plurality of memory chips.
Kobayashi discloses an arithmetic circuit (¶0057 of Kobayashi) being a well-known type of integrated circuit die, specifically for a processor which is a type of logic die.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include an arithmetic circuit in both the upper (6140 of Du and 164 of Yu) and lower (6110 of Du and LD1 of Yu) buffer chips of Du in view of Yu to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit high speed arithmetic processing in both the upper and lower buffer chips, which are both logic chips, compared to chips that do not have arithmetic circuits such as those relying on software for arithmetic processing.
Regarding claim 16, the aforementioned combination of Du in view of Yu, and further in view of Kobayashi from claim 15 teaches the semiconductor package of claim 15.
The aforementioned combination does not teach wherein at least one of the lower buffer chip and the upper buffer chip comprises arithmetic circuits configured to operate on data stored in the plurality of memory chips, wherein the plurality of memory chips comprise only memory cells.
Yu teaches wherein the upper buffer chip (164 of Yu) is a memory controller (¶0038 of Yu), which is an arithmetic circuit for calculating stored data.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for either buffer chip of Du in view of Yu to have this memory controller function to arrive at the claimed invention. A practitioner would have been motivated to make this modification to ensure proper function of the combined memory stack of Yu.
Regarding claim 17, the aforementioned combination of Du in view of Yu, and further in view of Kobayashi from claim 15 teaches the semiconductor package of claim 15, wherein the redistribution structure (6180 of Du) is configured to be connected to the lower buffer chip (6110 of Du) and the plurality of conductive posts (6150 of Du).
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Du in view of Yu, and further in view of Kobayashi, and further in view of Chen et al. (US-20220310470-A1 – hereinafter Chen).
Regarding claim 8, the aforementioned combination of Du in view of Yu, and further in view of Kobayashi from claim 7 teaches the semiconductor device of claim 7.
The aforementioned combination does not teach wherein the first molding layer and the second molding layer comprise different materials.
Chen teaches a first encapsulant (Fig.19 304; ¶0067 of Chen) and a second encapsulant (Fig.20 96; ¶0041 of Chen) for a similar chip structure as taught by Du (see Fig.20 of Chen), wherein the first and second encapsulants could comprise different materials as suggested by ¶0067 and ¶0041 of Chen.
It would be obvious for the first encapsulant (5160 of Du) and the second encapsulant (6160 of Du) of the primary reference to comprise different materials because it is a matter of design choice.
Regarding claim 9, the aforementioned combination of Du in view of Yu, and further in view of Kobayashi from claim 1 teaches the semiconductor device of claim 1.
The aforementioned combination does not teach the semiconductor device further comprising a first redistribution structure disposed between the first lower buffer chip and the upper buffer chip.
Chen teaches a redistribution layer (Fig.19 54; ¶0018 of Chen) disposed on a first chip (Fig.18 50B; ¶0062 of Chen) and under a second chip (Fig.18 50A; ¶0062 of Chen).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a redistribution structure (54 of Chen) between the lower buffer chip (6110 of Du) and the upper buffer chip (6140 of Du) as taught by Chen (Fig.19 of Chen) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of rerouting signals between both the lower and upper buffer chips as required for a given application.
Regarding claim 10, the aforementioned combination of Du in view of Yu, and further in view of Kobayashi, and further in view of Chen from claim 9 teaches the semiconductor device of claim 9, wherein the first redistribution structure (54 of Chen) is configured to be connected to the first lower buffer chip (6110 of Du), the upper buffer chip (6140 of Du), and the plurality of conductive posts (6150 of Du).
Claim(s) 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Du in view of Yu, and further in view of Chen et al. (US-20220310470-A1 – hereinafter Chen), and further in view of Kobayashi.
Regarding claim 19, Du teaches a semiconductor device (Fig.75 600; ¶0284) comprising:
a lower buffer chip (Fig.75 6110; ¶0269) including a first through electrode (Fig.75 6130; ¶0266);
a plurality of conductive posts (Fig.75 6150; ¶0269) spaced apart from the lower buffer chip (6110) and disposed along a periphery of the lower buffer chip (6110);
an upper buffer chip (Fig.75 6140; ¶0269); and
wherein a horizontal area of the upper buffer chip (6140) is greater than a horizontal area of the lower buffer chip (6110) and a vertical length of the upper buffer chip (6140) is greater than a vertical length of the lower buffer chip (6110), wherein a width of the plurality of conductive posts (6150) is greater than a width of the first through electrode (6130) and a width of the second through electrode (420).
Du does not teach a first redistribution structure disposed between the lower buffer chip and an upper buffer chip, the first redistribution structure contacting the lower buffer chip and the plurality of conductive posts, the first redistribution structure electrically connecting the lower buffer chip and the plurality of conductive posts to the upper buffer chip;
wherein the upper buffer chip is disposed on the first redistribution structure and including a second through electrode;
a memory chip stack structure disposed on the upper buffer chip and including a plurality of memory chips, wherein the width of the plurality of conductive posts is greater than a width of the second through electrode, and
wherein the lower buffer chip comprises an arithmetic circuit configured to calculate data stored in the plurality of memory chips.
Yu teaches a memory chip stack (Fig.1E MD; ¶0038 of Yu) with a plurality of memory chips (Fig.1E 162; ¶0038 of Yu) disposed on top of an upper buffer chip (Fig.1E 164; ¶0038 of Yu) with a redistribution structure in between (Fig.1E 150; ¶0038 of Yu), the upper buffer chip disposed on top of a lower buffer chip (Fig.1E LD1; ¶0038 of Yu); and
wherein the upper buffer chip comprises through electrodes (Fig.1E 116; ¶0032 of Yu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to dispose the memory chip stack of Yu (MD of Yu) on top of the upper buffer chip of Du (6140 of Du) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of providing memory functionality (¶0038 of Yu) without increasing the horizontal footprint of the package structure.
It would further be obvious to one of ordinary skill in the art to include through electrodes (164 of Yu) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of enabling communication between the previously combined memory stack (MD of Yu) with the lower buffer chip of Chen (50B of Chen). It would be reasonable to assume the combined second through electrodes would have a similar width to the first through electrodes (6130 of Du), and would therefore have a smaller width than the conductive posts (6150 of Du).
Du in view of Yu does not teach a first redistribution structure disposed between the lower buffer chip and an upper buffer chip, the first redistribution structure contacting the lower buffer chip and the plurality of conductive posts, the first redistribution structure electrically connecting the lower buffer chip and the plurality of conductive posts to the upper buffer chip;
wherein the upper buffer chip is disposed on the first redistribution structure, and
wherein the lower buffer chip comprises an arithmetic circuit configured to calculate data stored in the plurality of memory chips.
Chen teaches a redistribution layer (Fig.19 54; ¶0018 of Chen) disposed between a first chip (Fig.18 50B; ¶0062 of Chen) and a second chip (Fig.18 52; ¶0022 of Chen), the redistribution layer (54 of Chen) contacting the first chip (50B of Chen) and a plurality of conductive posts (Fig.17 302; ¶0066 of Chen), the redistribution layer (54 of Chen) electrically connecting the first chip (50B of Chen) and the plurality of conductive posts (302 of Chen) to the second chip (52 of Chen).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a redistribution structure (54 of Chen) between the lower buffer chip (6110 of Du), the upper buffer chip (6140 of Du) and the conductive posts (6150 of Du) as taught by Chen (Fig.19 of Chen) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of rerouting signals between both the lower and upper buffer chips as required for a given application.
Du in view of Yu, and further in view of Chen does not teach wherein the lower buffer chip comprises an arithmetic circuit configured to calculate data stored in the plurality of memory chips.
Kobayashi discloses an arithmetic circuit (¶0057 of Kobayashi) being a well-known type of integrated circuit die, specifically for a processor which is a type of logic die.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include an arithmetic circuit in both the upper (6140 of Du and 164 of Yu) and lower (6110 of Du and LD1 of Yu) buffer chips of Du in view of Yu to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit high speed arithmetic processing in both the upper and lower buffer chips, which are both logic chips, compared to chips that do not have arithmetic circuits such as those relying on software for arithmetic processing.
Regarding claim 20, the aforementioned combination of Du in view of Yu, and further in view of Chen, and further in view of Kobayashi from claim 19 teaches the semiconductor device of claim 19, further comprising:
a second molding layer (Fig.75 6160; ¶0269 of Du) surrounding a portion of sidewalls of the upper buffer chip (6140 of Du), a portion of an upper surface of the upper buffer chip (6140 of Du), and the memory chip stack structure (MD of Yu).
The aforementioned combination does not teach a first molding layer surrounding the lower buffer chip and the conductive posts;
wherein the second molding layer surrounds a portion of sidewalls of the first molding layer; and
wherein the first molding layer and the second molding layer comprise different materials.
An alternative embodiment of Du (Fig.60 of Du) teaches a first molding layer (Fig.60 5160; ¶0215 of Du) that surrounds the first buffer chip (5110 of Du) and the conductive posts (5150 of Du) with the second molding layer (5170 of Du) surrounding the upper buffer chip (5140 of Du) and the first molding layer (5160 of Du).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the two-encapsulant embodiment of the alternative embodiment (Fig.60 of Du) instead of the primary embodiment with only one encapsulant (Fig.75 of Du) to arrive at the claimed invention. This difference is a matter of design choice and does not patentably distinguish claim 7 over claim 1.
The aforementioned combination does not teach wherein the first molding layer and the second molding layer comprise different materials.
Chen teaches a first encapsulant (Fig.19 304; ¶0067 of Chen) and a second encapsulant (Fig.20 96; ¶0041 of Chen) for a similar chip structure as taught by Du (see Fig.20 of Chen), wherein the first and second encapsulants could comprise different materials as suggested by ¶0067 and ¶0041 of Chen.
It would be obvious for the first encapsulant (5160 of Du) and the second encapsulant (6160 of Du) of the primary reference to comprise different materials because it is a matter of design choice.
Regarding claim 21, the aforementioned combination of Du in view of Yu, and further in view of Chen, and further in view of Kobayashi from claim 19 teaches the semiconductor device of claim 19, wherein the plurality of conductive posts (6150 of Du) are surrounding the lower buffer chip (6110 of Du) and electrically connect the first redistribution structure (54 of Chen) to the upper buffer chip (6140 of Du), and
wherein the plurality of conductive posts (6150 of Du) are configured to supply power from the first redistribution structure (54 of Chen) to the upper buffer chip (6140 of Du) and the memory chip stack structure (MD of Yu).
The aforementioned combination does not teach wherein the plurality of conductive posts extend through a first molding layer.
An alternative embodiment of Du (Fig.60 of Du) teaches a first molding layer (Fig.60 5160; ¶0215 of Du) that surrounds the first buffer chip (5110 of Du) and the conductive posts (5150 of Du) with the second molding layer (5170 of Du) surrounding the upper buffer chip (5140 of Du) and the first molding layer (5160 of Du).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the two-encapsulant embodiment of the alternative embodiment (Fig.60 of Du) instead of the primary embodiment with only one encapsulant (Fig.75 of Du) to arrive at the claimed invention. This difference is a matter of design choice and does not patentably distinguish claim 7 over claim 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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