DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US-20220310470-A1 – hereinafter Chen) in view of Yu et al. (US-20210066279-A1 – hereinafter Yu).
Regarding claim 1, Chen teaches a semiconductor device (Fig.20; ¶0075) comprising:
a first lower buffer chip (Fig.18 50B; ¶0062);
an upper buffer chip (Fig.18 50A; ¶0062) disposed on an upper surface of the first lower buffer chip (50B);
a plurality of conductive posts (Fig.19 302; ¶0066) spaced apart from the first lower buffer chip (50B) and disposed on a lower surface of the upper buffer chip (50A); and
a first chip stack structure (Fig.23 94-A-C; ¶0059) disposed on the upper buffer chip (50A).
Chen does not teach wherein the first chip stack structure is a memory chip stack structure and including a plurality of first memory chips.
Yu teaches a memory chip stack (Fig.1E MD; ¶0038 of Yu) with a plurality of memory chips (Fig.1E 162; ¶0038 of Yu) disposed on top of an upper buffer chip (Fig.1E 164; ¶0038 of Yu) with a redistribution structure in between (Fig.1E 150; ¶0038 of Yu), the upper buffer chip disposed on top of a lower buffer chip (Fig.1E LD1; ¶0038).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the memory chip stack of Yu (MD of Yu) be the chip stack disposed on top of the upper buffer chip of Chen (50A of Chen) to arrive at the claimed invention. This modification is a matter of design choice to yield semiconductor packages for different applications and/or sizes and shapes.
Regarding claim 2, the aforementioned combination of Chen in view of Yu from claim 1 teaches the semiconductor device of claim 1, wherein a horizontal area of the upper buffer chip (50A of Chen) is different from a horizontal area of the first lower buffer chip (50B of Chen).
Regarding claim 3, the aforementioned combination of Chen in view of Yu from claim 1 teaches the semiconductor device of claim 1, wherein a horizontal area of the upper buffer chip (50A of Chen) is greater than a horizontal area of the first lower buffer chip (50B of Chen).
Regarding claim 4, the aforementioned combination of Chen in view of Yu from claim 1 teaches the semiconductor device of claim 1, wherein the first lower buffer chip (50B) comprises a first through electrode (Fig.19 62; ¶0022 of Chen) extending in a first direction (vertical direction) perpendicular to the upper surface of the first lower buffer chip (50B).
The aforementioned combination does not teach the upper buffer chip comprising a second through electrode extending in the first direction.
Yu teaches the upper buffer chip (164 of Yu) comprising through electrodes (Fig.1E 116; ¶0032 of Yu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the upper buffer chip of Chen (50A of Chen) to include through electrodes (164 of Yu) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of enabling communication between the previously combined memory stack (MD of Yu) with the lower buffer chip of Chen (50B of Chen).
Regarding claim 5, the aforementioned combination of Chen in view of Yu from claim 4 teaches the semiconductor device of claim 4, wherein a width of the plurality of conductive posts (302 of Chen) is greater than a width of the first through electrode (62 of Chen) and a width of the second through electrode (164 of Yu).
Regarding claim 6, the aforementioned combination of Chen in view of Yu from claim 1 teaches the semiconductor device of claim 1, wherein at least one of the first lower buffer chip (50B of Chen) and the upper buffer chip (50B of Chen) comprises an arithmetic circuit configured to calculate data stored in the plurality of first memory chips (¶0022 of Chen).
Regarding claim 7, the aforementioned combination of Chen in view of Yu from claim 1 teaches the semiconductor device of claim 1, further comprising:
a first molding layer (Fig.19 304; ¶0067 of Chen) surrounding the first lower buffer chip (50B of Chen) and the conductive posts (302 of Chen); and
a second molding layer (Fig.20 96; ¶0041 of Chen) surrounding the first molding layer (304 of Chen), the upper buffer chip (50A of Chen), and the first memory chip stack structure (MD of Yu).
Regarding claim 8, the aforementioned combination of Chen in view of Yu from claim 1 teaches the semiconductor device of claim 1, wherein the first molding layer (304 of Chen) and the second molding layer (96 of Chen) comprise different materials (this is suggested by ¶0067 and ¶0041 of Chen).
Regarding claim 9, the aforementioned combination of Chen in view of Yu from claim 1 teaches the semiconductor device of claim 1, further comprising a first redistribution structure (Fig.19 54; ¶0018 of Chen) disposed between the first lower buffer chip (50B of Chen) and the upper buffer chip (50A of Chen).
Regarding claim 10, the aforementioned combination of Chen in view of Yu from claim 9 teaches the semiconductor device of claim 9, wherein the first redistribution structure (54 of Chen) is configured to be connected to the first lower buffer chip (50B of Chen), the upper buffer chip (50A of Chen), and the plurality of conductive posts (302 of Chen).
Regarding claim 11, the aforementioned combination of Chen in view of Yu from claim 1 teaches the semiconductor device of claim 1, wherein the first lower buffer chip (50B of Chen) overlaps a center of the upper buffer chip (50A of Chen) in a first direction (vertical direction) perpendicular to the upper surface of the first lower buffer chip (50B of Chen).
Regarding claim 12, the aforementioned combination of Chen in view of Yu from claim 1 teaches the semiconductor device of claim 1.
The aforementioned combination does not teach wherein the first lower buffer chip overlaps an edge portion of the upper buffer chip in a first direction perpendicular to the upper surface of the first lower buffer chip.
Fig.1E of Yu depicts the lower buffer chip (LD1 of Yu) being wider than the upper buffer chip (164 of Yu) and therefore overlapping an edge portion of the upper buffer chip (164 of Yu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the lower buffer chip (50B of Chen) to be wider than the upper buffer chip (50A of Chen) as taught by Yu (Fig.1E of Yu) as a matter of design choice.
Regarding claim 13, the aforementioned combination of Chen in view of Yu from claim 1 teaches the semiconductor device of claim 1, further comprising a second redistribution structure (150 of Yu) disposed between the upper buffer chip (50A of Chen) and the first memory chip stack structure (MD of Yu) and configured to connect the upper buffer chip (50A of Chen) to the first memory chip stack structure (MD of Yu).
Regarding claim 14, the aforementioned combination of Chen in view of Yu from claim 1 teaches the semiconductor device of claim 1.
The aforementioned combination does not teach the semiconductor device further comprising:
a second lower buffer chip disposed on a lower surface of the upper buffer chip and spaced apart from the first lower buffer chip; and
a second memory chip stack structure disposed on an upper surface of the upper buffer chip and including a plurality of second memory chips.
Yu teaches an alternative embodiment (Fig.3 of Yu) comprising a second lower buffer chip (Fig.3 LD2; ¶0044 of Yu) and multiple memory stacks (Fig.3 MD of Yu), with the second lower buffer chip (LD2 of Yu) spaced apart from the first lower buffer chip (LD1 of Yu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the configuration taught by Figure 3 of Yu including duplicates of previously taught components to arrive at the claimed invention. This modification is obvious because it is a matter of design choice.
Regarding claim 15, Chen teaches a semiconductor package (Fig.20; ¶0075) comprising:
a redistribution structure (Fig.20 74; ¶0028);
a semiconductor device (Fig.19 60A; ¶0085) disposed on the redistribution structure (74); and
a semiconductor chip (Fig.20 80; ¶0024) disposed on the redistribution structure (74) and spaced apart from the semiconductor device (60A) in a horizontal direction, wherein the semiconductor device (60A) comprises:
a lower buffer chip (Fig.18 50B; ¶0062) disposed on the redistribution structure (74);
an upper buffer chip (Fig.18 50A; ¶0062) disposed on an upper surface of the lower buffer chip (50B);
a plurality of conductive posts (Fig.19 302; ¶0066) spaced apart from the lower buffer chip (50B) and disposed on a lower surface of the upper buffer chip (50A); and
a first chip stack structure (Fig.23 94-A-C; ¶0059) disposed on the upper buffer chip (50A).
Chen does not teach wherein the first chip stack structure is a memory chip stack structure and including a plurality of first memory chips.
Yu teaches a memory chip stack (Fig.1E MD; ¶0038 of Yu) with a plurality of memory chips (Fig.1E 162; ¶0038 of Yu) disposed on top of an upper buffer chip (Fig.1E 164; ¶0038 of Yu) with a redistribution structure in between (Fig.1E 150; ¶0038 of Yu), the upper buffer chip disposed on top of a lower buffer chip (Fig.1E LD1; ¶0038).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the memory chip stack of Yu (MD of Yu) be the chip stack disposed on top of the upper buffer chip of Chen (50A of Chen) to arrive at the claimed invention. This modification is a matter of design choice to yield semiconductor packages for different applications and/or sizes and shapes.
Regarding claim 16, the aforementioned combination of Chen in view of Yu from claim 15 teaches the semiconductor package of claim 15, wherein at least one of the lower buffer chip (50B of Chen) and the upper buffer chip (50A of Chen) comprises arithmetic circuits (¶0022 of Chen) configured to operate on data stored in the plurality of memory chips (162 of Yu), wherein the plurality of memory chips (162 of Yu) comprise only memory cells.
Regarding claim 17, the aforementioned combination of Chen in view of Yu from claim 15 teaches the semiconductor package of claim 15, wherein the redistribution structure (74 of Chen) is configured to be connected to the lower buffer chip (50B of Chen) and the plurality of conductive posts (302 of Chen).
Regarding claim 18, the aforementioned combination of Chen in view of Yu from claim 15 teaches the semiconductor package of claim 15, wherein the plurality of conductive posts (302 of Chen) are configured to apply power to the upper buffer chip (50A of Chen) and the memory chip stack structure (MD of Yu).
Regarding claim 19, Chen teaches a semiconductor device (Fig.20; ¶0075) comprising:
a lower buffer chip (Fig.18 50B; ¶0062) including a first through electrode (Fig.19 62; ¶0022);
a plurality of conductive posts (Fig.19 302; ¶0066) spaced apart from the lower buffer chip (50B) and disposed along a periphery of the lower buffer chip (50B);
a first redistribution structure (Fig.19 54; ¶0018) disposed on the lower buffer chip (50B) and the plurality of conductive posts (302);
an upper buffer chip (Fig.18 50A; ¶0062) disposed on the first redistribution structure (54); and
a first chip stack structure (Fig.23 94-A-C; ¶0059) disposed on the upper buffer chip (50A), wherein a horizontal area of the upper buffer chip (50A) is greater than a horizontal area of the lower buffer chip (50B) and a vertical length of the upper buffer chip (50A) is greater than a vertical length of the lower buffer chip (50B), wherein a width of the plurality of conductive posts (302) is greater than a width of the first through electrode (62) and a width of the second through electrode (420).
Chen does not teach the upper buffer chip including a second through electrode; and
wherein the first chip stack structure is a memory chip stack structure and including a plurality of first memory chips; and
wherein a width of the plurality of conductive posts is greater than a width of the second through electrode.
Yu teaches a memory chip stack (Fig.1E MD; ¶0038 of Yu) with a plurality of memory chips (Fig.1E 162; ¶0038 of Yu) disposed on top of an upper buffer chip (Fig.1E 164; ¶0038 of Yu) with a redistribution structure in between (Fig.1E 150; ¶0038 of Yu), the upper buffer chip disposed on top of a lower buffer chip (Fig.1E LD1; ¶0038); and
wherein the upper buffer chip comprises through electrodes (Fig.1E 116; ¶0032 of Yu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the memory chip stack of Yu (MD of Yu) be the chip stack disposed on top of the upper buffer chip of Chen (50A of Chen) to arrive at the claimed invention. This modification is a matter of design choice to yield semiconductor packages for different applications and/or sizes and shapes.
It would further be obvious to one of ordinary skill in the art to include through electrodes (164 of Yu) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of enabling communication between the previously combined memory stack (MD of Yu) with the lower buffer chip of Chen (50B of Chen).
Regarding claim 20, the aforementioned combination of Chen in view of Yu from claim 19 teaches the semiconductor device of claim 19, further comprising:
a first molding layer (Fig.19 304; ¶0067 of Chen) surrounding the lower buffer chip (50B of Chen) and the conductive posts (302 of Chen); and
a second molding layer (Fig.20 96; ¶0041 of Chen) surrounding a portion of sidewalls of the first molding layer (304 of Chen), a portion of sidewalls of the upper buffer chip (50A of Chen), a portion of an upper surface of the upper buffer chip (50A of Chen), and the memory chip stack structure (MD of Yu), wherein the first molding layer (304 of Chen) and the second molding layer (96 of Chen) comprise different materials (this is suggested by ¶0067 and ¶0041 of Chen).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (US-20230389284-A1 and US-11282816-B2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817