DETAILED ACTION
This action is responsive to the following communication: the response filed 8/19/26. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-5, 7-13, 15-21 pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/19/26 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 7-8, 9-10, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 10,957,394 ‒hereinafter Chen) in view of Dong et al. (US 9,620,233 ‒hereinafter Dong).
Regarding claim 1, Chen discloses a method of pre-charging a plurality of channels in a memory device, comprising the steps of:
preparing a memory block (BLK0; fig. 6) that includes a plurality of memory cells that are arranged in a stack (“stack comprises alternating conductive and dielectric layers. The conductive layers act as word lines which are connected to the memory cells” column/line(s): 2/46-48) that includes a plurality of word lines (the memory cells are formed in a region in which the word lines intersect with the multiple thin layers; column/line(s): 14/11-13, 24/10-11, further WL0-WL19; fig. 16) and are arranged in a plurality of channels (channels extending vertically, i.e. “a channel which extends vertically in the stack. For example, see the channel 660 in the NAND string 700n” fig. 6 column/line(s): 2/54-55) and wherein a plurality of bit lines (bit lines BL, represented as bit lines BL0 and BL1; fig. 5, 6) are located on one side of the stack (i.e. drain side D; fig. 5) and a source line (source line SL of the block; fig. 10 column/line(s): 13/5-6) is located at an opposite side of the stack (i.e. source side S; fig. 5); and
in a hole pre-charge operation (hole-type pre-charging (C); fig. 10, 11), inducing by concurrently applying (i.e. during time t0-t1; fig. 14) a negative voltage (a voltage less than 0V; option C, fig. 10; further 1433 for Vsgs; fig. 14) to a source-side select gate transistor (SGS; fig. 6, 10) and a positive voltage (a voltage greater than 0V; option C, fig. 10; further 1451 for Vsl; fig. 14) to the source line (SL; fig. 5, 6, 10) to generate holes (column/line(s): 13/49-53) and inject the generated holes into the channels (1102; fig. 11, column/line(s): 18/11-20) prior to application of a programming pulse (time t1-t2 prior to application of programming pulse Vpgm during time t5-t6; fig. 14).
Chen does not expressly disclose gate-induced drain leakage (GIDL) and a voltage that is a weak erase voltage.
Dong discloses gate-induced drain leakage (GIDL) (“gate induced drain leakage (GIDL) current to charge up the NAND string channel” column/line(s): 26/17-18, i.e. for a hole pre-charge) and a voltage that is a weak erase voltage (“weak erase voltage is provided to the channel by way of the bit line and/or source line” column/line(s): 26/14-15)
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chen is modifiable as taught by Dong for the purpose of facilitating data accessing schemes by maintaining threshold voltage distributions (column/line(s): 2/40-55 of Dong), which is common and well known in the prior art to mitigate disturbances to threshold voltage windows.
Regarding claim 2, Chen discloses the method, wherein the memory cells of at least some of the plurality of word lines are programmed to retain at least three bits of data per memory cell (fig. 12).
Regarding claim 7, Chen discloses the method, wherein the plurality of word lines that are programmed include at least three bits of data per memory cell (fig. 12).
Regarding claim 8, Chen discloses the method, wherein at least some of the plurality of memory cells are in an erased data state that is associated with a range of threshold voltages (each data state, including erased data state Er, can be represented by a range of threshold voltages (Vth) in the memory cells; fig. 12, column/line(s): 19/12-26), and wherein a first voltage (0V; fig. 10) is applied to the plurality of word lines during the hole pre-charge operation (hole-type pre-charging (C); fig. 10, 11) and the first voltage is lower than the range of threshold voltages associated with the erased data state (i.e. 0V applied to word lines during hole-type pre-charging is considered lower than the range of Vth; fig. 10, 12).
Regarding claim 9, Chen discloses a memory device, comprising:
a memory block (BLK0; fig. 6) that includes a plurality of memory cells that are arranged in a plurality of word lines (memory cells are formed in a region in which the word lines intersect with the multiple thin layers; column/line(s): 14/11-13, 24/10-11, further WL0-WL19; fig. 16) of a stack (“stack comprises alternating conductive and dielectric layers. The conductive layers act as word lines which are connected to the memory cells” column/line(s): 2/46-48) and in a plurality of channels (channels extending vertically, i.e. channel 660; fig. 6), a plurality of bit lines (bit lines BL, represented as bit lines BL0 and BL1; fig. 5, 6) being located on one side of the stack (i.e. drain side D; fig. 5) and a source line (source line SL of the block; fig. 10 column/line(s): 13/5-6) being located at an opposite side of the stack (i.e. source side S; fig. 5);
circuitry (110; fig. 1A) that is configured to conduct a hole pre-charge operation (hole-type pre-charging (C); fig. 10, 11) to inject holes into the plurality of channels (1102; fig. 11, column/line(s): 18/11-20), the hole pre-charge operation including;
applying a first voltage (0V; fig. 10) to the plurality of word lines (biasing the plurality of word lines, i.e. WL0-WL19, with a respective voltage of no more than 0V; fig. 10, 16, column/line(s): 22/29-45) to make the plurality of memory cells conductive to holes (i.e. conduction of holes occurs in the channel of memory cells; column/line(s): 17/21-23) and applying a second voltage that is positive (a voltage greater than 0V; option C, fig. 10; further 1451 for Vsl; fig. 14) to the source line (SL; fig. 5, 6, 10) and applying a third voltage that is negative (a voltage less than 0V; option C, fig. 10; further 1433 for Vsgs; fig. 14) to a source-side select gate transistor (SGS; fig. 6, 10) to induce to generate holes (column/line(s): 13/49-53) and inject the holes into the channels (1102; fig. 11, column/line(s): 18/11-20).
Chen does not expressly disclose gate-induced drain leakage (GIDL) and a voltage that is a weak erase voltage.
Dong discloses gate-induced drain leakage (GIDL) (“gate induced drain leakage (GIDL) current to charge up the NAND string channel” column/line(s): 26/17-18, i.e. for a hole pre-charge) and a voltage that is a weak erase voltage (“weak erase voltage is provided to the channel by way of the bit line and/or source line” column/line(s): 26/14-15)
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chen is modifiable as taught by Dong for the purpose of facilitating data accessing schemes by maintaining threshold voltage distributions (column/line(s): 2/40-55 of Dong), which is common and well known in the prior art to mitigate disturbances to threshold voltage windows.
Regarding claim 10, Chen discloses the memory device, wherein the memory cells of at least some of the plurality of word lines are programmed to retain at least three bits of data per memory cell (fig. 12).
Regarding claim 16, Chen discloses the memory device, wherein at least some of the plurality of memory cells are in an erased data state that is associated with a range of threshold voltages (each data state, including erased data state Er, can be represented by a range of threshold voltages (Vth) in the memory cells; fig. 12, column/line(s): 19/12-26), and wherein the first voltage (0V; fig. 10) that is applied by the circuitry to the plurality of word lines during the hole pre-charge operation (hole-type pre-charging (C); fig. 10, 11) is lower than the range of threshold voltages associated with the erased data state (i.e. 0V applied to word lines during hole-type pre-charging is considered lower than the range of Vth; fig. 10, 12).
Claim(s) 3-5, 11-13, 15, 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 10,957,394 ‒hereinafter Chen) in view of Dong et al. (US 9,620,233 ‒hereinafter Dong), and further in view of Suzuki et al. (US. 2020/0075110 ‒hereinafter Suzuki).
Regarding claim 3, Chen as modified does not expressly disclose the method, further including the step of establishing one of the plurality of word lines that is programmed as a selected word line to be re-programmed.
Suzuki discloses the step of establishing one of the plurality of word lines that is programmed as a selected word line to be re-programmed (para 0122).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chen is further modifiable as taught by Suzuki for the purpose of facilitating data accessing schemes by achieving optimal threshold voltage distributions, which is common and well known in the art to reduce latencies due to faulty data access (para 0122 of Suzuki).
Regarding claim 4, Chen as modified does not expressly disclose the method, wherein the step of establishing one of the plurality of word lines that is programmed as the selected word line to be re-programmed includes determining that the selected word line has a failed bit count that is greater than a threshold.
Suzuki discloses the step of establishing one of the plurality of word lines that is programmed as the selected word line to be re-programmed includes determining that the selected word line has a failed bit count that is greater than a threshold (para 0153-0155).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chen is further modifiable as taught by Suzuki for the purpose of facilitating data accessing schemes by achieving optimal threshold voltage distributions, which is common and well known in the art to reduce latencies due to faulty data access (para 0122 of Suzuki).
Regarding claim 5, Chen as modified discloses the method, further including the step of applying a programming pulse (Vpgm; fig. 14) to the selected word line (WLn; fig. 14) of the plurality of word lines after the hole pre-charge operation (t0-t2; fig. 14).
Chen does not expressly disclose to re-program the memory cells of the selected word line.
Suzuki discloses to re-program the memory cells of the selected word line (para 0122).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chen is further modifiable as taught by Suzuki for the purpose of facilitating data accessing schemes by achieving optimal threshold voltage distributions, which is common and well known in the art to reduce latencies due to faulty data access (para 0122 of Suzuki).
Regarding claim 11, Chen as modified does not expressly disclose the memory device, wherein the circuitry is further configured to establish one of the plurality of word lines that is programmed as a selected word line to be re-programmed.
Suzuki discloses to establish one of the plurality of word lines that is programmed as a selected word line to be re-programmed (para 0122).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chen is further modifiable as taught by Suzuki for the purpose of facilitating data accessing schemes by achieving optimal threshold voltage distributions, which is common and well known in the art to reduce latencies due to faulty data access (para 0122 of Suzuki).
Regarding claim 12, Chen as modified does not expressly disclose the memory device, wherein the circuitry is further configured to establish the selected word line based on a determination that a failed bit count of the selected word line is greater than a threshold.
Suzuki discloses to establish the selected word line based on a determination that a failed bit count of the selected word line is greater than a threshold (para 0153-0155).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chen is further modifiable as taught by Suzuki for the purpose of facilitating data accessing schemes by achieving optimal threshold voltage distributions, which is common and well known in the art to reduce latencies due to faulty data access (para 0122 of Suzuki).
Regarding claim 13, Chen as modified discloses the memory device, wherein the circuitry is further configured to apply a programming pulse (Vpgm; fig. 14) to the selected word line (WLn; fig. 14) of the plurality of word lines after the hole pre-charge operation (t0-t2; fig. 14).
Chen does not expressly disclose to re-program at least some of the memory cells of the selected word line.
Suzuki discloses to re-program at least some of the memory cells of the selected word line (para 0122).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chen is further modifiable as taught by Suzuki for the purpose of facilitating data accessing schemes by achieving optimal threshold voltage distributions, which is common and well known in the art to reduce latencies due to faulty data access (para 0122 of Suzuki).
Regarding claim 15, Chen discloses the memory device, wherein the plurality of word lines that are programmed include at least three bits of data per memory cell (fig. 12).
Regarding claim 17, Chen discloses an apparatus, comprising:
a memory block (BLK0; fig. 6) that includes a plurality of memory cells that are arranged in a plurality of word lines (memory cells are formed in a region in which the word lines intersect with the multiple thin layers; column/line(s): 14/11-13, 24/10-11, further WL0-WL19; fig. 16) of a stack (“stack comprises alternating conductive and dielectric layers. The conductive layers act as word lines which are connected to the memory cells” column/line(s): 2/46-48) and in a plurality of channels (channels extending vertically, i.e. channel 660; fig. 6), a plurality of bit lines (bit lines BL, represented as bit lines BL0 and BL1; fig. 5, 6) being located on one side of the stack (i.e. drain side D; fig. 5) and a source line (source line SL of the block; fig. 10 column/line(s): 13/5-6) being located at an opposite side of the stack (i.e. source side S; fig. 5);
a re-programming means for data (column/line(s): 10/62-65) in a selected word line (WLn; fig. 14) that has been programmed (i.e. after time t6; fig. 14),
apply a first voltage (0V; fig. 10) to the plurality of word lines (biasing the plurality of word lines, i.e. WL0-WL19, with a respective voltage of no more than 0V; fig. 10, 16, column/line(s): 22/29-45) to make the plurality of memory cells conductive to holes (i.e. conduction of holes occurs in the channel of memory cells; column/line(s): 17/21-23) and applying a second voltage that is positive (a voltage greater than 0V; option C, fig. 10; further 1451 for Vsl; fig. 14) to the source line (SL; fig. 5, 6, 10) and applying a third voltage that is negative (a voltage less than 0V; option C, fig. 10; further 1433 for Vsgs; fig. 14) to a source-side select gate transistor (SGS; fig. 6, 10) to induce to generate holes (column/line(s): 13/49-53) and to inject holes into the channels (1102; fig. 11, column/line(s): 18/11-20).
Chen does not expressly disclose re-programming means for refreshing data in a selected word line that has been programmed, the re-programming means being configured to: determine that the selected word line has a failed bit count that is greater than a threshold, a voltage that is a weak erase voltage, gate-induced drain leakage (GIDL), and apply a programming pulse to the selected word line to re-program at least some of the memory cells of the selected word line.
Dong discloses a voltage that is a weak erase voltage (“weak erase voltage is provided to the channel by way of the bit line and/or source line” column/line(s): 26/14-15), gate-induced drain leakage (GIDL) (“gate induced drain leakage (GIDL) current to charge up the NAND string channel” column/line(s): 26/17-18, i.e. for a hole pre-charge).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chen is modifiable as taught by Dong for the purpose of facilitating data accessing schemes by maintaining threshold voltage distributions (column/line(s): 2/40-55 of Dong), which is common and well known in the prior art to mitigate disturbances to threshold voltage windows.
Suzuki discloses re-programming means for refreshing data in a selected word line that has been programmed (para 0122), the re-programming means being configured to:
determine that the selected word has a failed bit count that is greater than a threshold (para 0153-0155), and apply a programming pulse to the selected word line to re-program at least some of the memory cells of the selected word line (para 0255, 0274).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chen is further modifiable as taught by Suzuki for the purpose of facilitating data accessing schemes by achieving optimal threshold voltage distributions, which is common and well known in the art to reduce latencies due to faulty data access (para 0122 of Suzuki).
Regarding claim 18, Chen discloses the apparatus, wherein the memory cells of at least some of the plurality of word lines are programmed to retain at least three bits of data per memory cell (fig. 12).
Regarding claim 19, Chen does not expressly disclose the apparatus, wherein the weak erase voltage that is applied to the source line is approximately seven volts.
Dong discloses the weak erase voltage that is applied to the source line is approximately seven volts (column/line(s): 26/1-5).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chen is modifiable as taught by Dong for the purpose of facilitating data accessing schemes by maintaining threshold voltage distributions (column/line(s): 2/40-55 of Dong), which is common and well known in the prior art to mitigate disturbances to threshold voltage windows.
Regarding claim 20, Chen discloses the apparatus, wherein at least some of the plurality of memory cells are in an erased data state that is associated with a range of threshold voltages (each data state, including erased data state Er, can be represented by a range of threshold voltages (Vth) in the memory cells; fig. 12, column/line(s): 19/12-26), and wherein the first voltage (0V; fig. 10) that is applied by the circuitry to the plurality of word lines during the hole pre-charge operation (hole-type pre-charging (C); fig. 10, 11) is lower than the range of threshold voltages associated with the erased data state (i.e. 0V applied to word lines during hole-type pre-charging is considered lower than the range of Vth; fig. 10, 12).
Regarding claim 21, Chen does not expressly disclose the method, wherein the weak erase voltage is approximately seven volts.
Dong discloses the weak erase voltage that is applied to the source line is approximately seven volts (column/line(s): 26/1-5).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chen is modifiable as taught by Dong for the purpose of facilitating data accessing schemes by maintaining threshold voltage distributions (column/line(s): 2/40-55 of Dong), which is common and well known in the prior art to mitigate disturbances to threshold voltage windows.
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/UYEN SMET/
Primary Examiner, Art Unit 2824
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