Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/10/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-3, 7, 21, 24-25, 31-42 are rejected under 35 U.S.C. 103 as being unpatentable over Koo (US 20170222649 A1) in view of Lin (US 20200111734 A1).
Regarding claim 1, Koo discloses a multi-chip package (Fig. 3) comprising:
a first semiconductor integrated-circuit (IC) chip (160; [0046]: “one of external chips”) comprising a first input/output (I/O) circuit (a component of 160, See annotated figure);
a second semiconductor integrated-circuit (IC) chip (100, See annotated figure; [0046]: “the system-on-chip 100”) comprising:
a second input/output (I/O) circuit (Fig. 1: 130; selecting the embodiment of Fig. 11 for this circuit) coupling to the first input/output (I/O) circuit of the first semiconductor integrated-circuit (IC) chip (coupling through 150) for data transmission (Fig. 1: Data),
wherein the second input/output (I/O) circuit has a first power supply voltage (VddL) (Fig. 13: VDDL) with reference to a common ground voltage (Vss) (the schematic symbol for ground is illustrated),
a third input/output (I/O) circuit (Fig. 1: 120; selecting the embodiment of Fig. 10 for this circuit), configured for coupling to an external circuit of the multi-chip package (coupling through 150; [0025]: “interface with various external chips”; [0032]: “input/output pad 150 may be connected to an external channel”) for data transmission (Fig. 1: Data),
wherein the third input/output (I/O) circuit comprises a last output stage circuit (This circuit 520 ends at D_IO which corresponds to the same ending D_IO of Fig. 1. There are no other circuits after D_IO. Thus, this circuit is a “last output stage circuit”) having a second power supply voltage (VddH) (VDDH) with reference to the common ground voltage (Vss) (the schematic symbol for ground is illustrated),
wherein the second power supply voltage (VddH) with reference to the common ground voltage (Vss) is higher than the first power supply voltage (VddL) with reference to the common ground voltage (Vss) ([0033]: “higher than”), and
a first voltage-level shift circuit (Fig. 11: the circuitry of 130) having a first input node (D_IO) and a first output node (D_INa, D_INb),
wherein the first voltage-level shift circuit comprises a first input circuit element (132) coupling to the first input node (132 directly couples to D_IO) and a first output circuit element (131) coupling to the first output node (131 directly couples to D_INa),
wherein the first output node couples to the third input/output (I/O) circuit (Fig. 1: indirectly couples by routing through 110 and 120 before reaching D_IO),
wherein the first input circuit element has the first power supply voltage (VddL) (Fig. 13: VDDL) with reference to the common ground voltage (Vss) (the schematic symbol for ground is illustrated), and
the first output circuit element has the second power supply voltage (VddH) (Fig. 12: VDDL) with reference to the common ground voltage (Vss) (the schematic symbol for ground is illustrated); and
a first metal bump under the second semiconductor integrated-circuit (IC) chip and at a bottom of the multi-chip package.
Illustrated below are Fig. 1, marked and annotated figure of Fig. 3, and Figs. 10-13 of Koo.
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Koo teaches input/output circuits and an external circuit, but fails to teach structural configurations of the external connections. Thus, Koo fails to teach “a first metal bump under the second semiconductor integrated-circuit (IC) chip and at a bottom of the multi-chip package”.
Lin discloses a multi-chip package in the same field of endeavor (Fig. 25B) comprising: a finite selection of known suitable first metal bumps (563b; [0331]: “micro-bumps or micro-pillars”). This finite selection includes a first metal bump (563b; [0331]: “micro-bumps”) under the second semiconductor integrated-circuit (IC) chip and at a bottom of the multi-chip package. Modifying the multi-chip package of Koo by selecting these first metal bumps and using them in the same way would arrive at the claimed bump configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Lin teaches these bumps perform the function of data transmission ([0348]: “a signal bus for delivering signals”). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different external connection structure (i.e., the bumps). Therefore, the claim would have been obvious because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR). MPEP 2143 (1)(E).
Illustrated below is a marked and annotated figure of Fig. 25B of Lin.
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Regarding claim 2, Koo in view of Lin discloses the multi-chip package of claim 1 (Koo: Fig. 1), wherein the first power supply voltage (VddL) is lower than 0.7 volts ([0024]: “a logic voltage VDDL”; [0025]: “a power supply voltage of the logic circuit 110 in the system-on-chip 100 may be, for example, 1.0 V or lower”. Note: this range is overlapping the claimed range.).
Regarding claim 3, Koo in view of Lin discloses the multi-chip package of claim 1 (Koo: Fig. 1), wherein the second power supply voltage (VddH) is higher than 1 volt ([0024]: “a logic voltage VDDL”; [0025]: “a power supply voltage of the logic circuit 110 in the system-on-chip 100 may be, for example, 1.0 V or lower”; [0033]: “An interface voltage VDDH may be set to be higher than, equal to, or lower than the logic voltage VDDL” . Note: “higher” in reference to VDDL produces a range overlapping the claimed range.).
Regarding claim 7, Koo in view of Lin discloses the multi-chip package of claim 1 (Koo: Fig. 3), wherein the first semiconductor integrated- circuit (IC) chip is a logic chip ([0046]: “a chip including various functions such as an audio processor, an image processor, a controller, and application specific integrated circuits”).
Regarding claim 21, Koo in view of Lin discloses the multi-chip package of claim 1 (Koo: Fig. 11), wherein the first input node of the first voltage-level shift circuit couples to the second input/output (I/O) circuit (node D_IO couples to circuit 130).
Regarding claim 24, Koo in view of Lin discloses the multi-chip package of claim 1, wherein the second semiconductor integrated-circuit (IC) chip further comprises:
a fourth input/output (I/O) circuit (Koo: Fig. 4) configured for coupling to an external circuit of the multi-chip package (coupling through D_IO and 150; [0025]: “interface with various external chips”; [0032]: “input/output pad 150 may be connected to an external channel”) for data transmission (Fig. 1: Data),
wherein the fourth input/output (I/O) circuit comprises an inverter (INV) having the second power supply voltage (VddH) (Fig. 2: VDDH schematically connects in series from circuit 122 to D_PRE of circuit 123a. This configuration of VDDH to D_PRE is retained for D_PRE connection in the embodiment of Fig. 4.) with reference to the common ground voltage (Vss) (the schematic symbol for ground is illustrated);
a fifth input/output (I/O) circuit (Fig. 1: 120 corresponding to the first chip 160 of Fig. 3) coupling to a sixth input/output (I/O) circuit of the first semiconductor integrated-circuit (IC) chip (See annotated Fig. 3, a duplicate of “First I/O Circuit (of 160)” and corresponding to another of the multiple circuit blocks) for data transmission (because of the connection to the data channel),
wherein the fifth input/output (I/O) circuit has the first power supply voltage (VddL) (Fig. 10: VDDL) with reference to the common ground voltage (Vss) (the schematic symbol for ground is illustrated);
and a second voltage-level shift circuit (collection of 522 with 521) having a second input node (D_PRE) and a second output node (D_LS), wherein the second voltage-level shift circuit comprises a second input circuit element (522) coupling to the second input node (coupling at D_PRE) and a second output circuit element (521) coupling to the second output node (coupling at D_LS),
wherein the second input node couples to the fourth input/output (I/O) circuit (Fig. 1: indirectly couples by routing through 110 and 120 before reaching D_IO),
wherein the second input circuit element has the first power supply voltage (VddL) (VDDL) with reference to the common ground voltage (Vss) (the schematic symbol for ground is illustrated), and
the second output circuit element has the first power supply voltage (VddL) (VDDL is electrically connected to 522 in series through MP1) with reference to the common ground voltage (Vss) (the schematic symbol for ground is illustrated).
Regarding claim 25, Koo in view of Lin discloses the multi-chip package of claim 24 (Koo: Fig. 10), wherein the second output node of the second voltage-level shift circuit couples to the fifth input/output (I/O) circuit (“couples” by being inclusive within the circuit of Fig. 10).
Regarding claim 31, Koo in view of Lin discloses the multi-chip package of claim 1, wherein the second input/output (I/O) circuit (Koo: the circuit of 130 extends through 110 and reaches 120. The second input/output (I/O) circuit is designated here as including these portions of other sub-circuits) comprises an inverter (Fig. 6: INV) having an output node coupling (indirectly coupling) to the first input node of the first voltage-level shift circuit (backwards through the inverter and intervening circuits of the shift circuit) and having the first power supply voltage (VddL) (Fig. 10: VDDL is electrically in series to 521 which corresponds to the circuitry of Fig. 6) with reference to the common ground voltage (Vss) (the schematic symbol for ground is illustrated).
Regarding claim 32, Koo in view of Lin discloses the multi-chip package of claim 1 (Fig. 6), wherein the last output stage circuit of the third input/output (I/O) circuit comprises an inverter (INV) having the second power supply voltage (VddH) (VDDH) with reference to the common ground voltage (Vss) (the schematic symbol for ground is illustrated).
Regarding claim 33, Koo in view of Lin discloses the multi-chip package of claim 1 (Koo: Fig. 1), wherein the second semiconductor integrated-circuit (IC) chip is an input/output (I/O) integrated-circuit (IC) chip (chip 100 includes inputs and outputs at 150, thus it is “an input/output (I/O) integrated-circuit (IC) chip”).
Regarding claim 34, Koo in view of Lin discloses the multi-chip package of claim 1 (Koo: Fig. 1), wherein the second semiconductor integrated-circuit (IC) chip is a control chip ([0026]: “The system-on-chip 100 may adjust driving voltages of the logic circuit 110, the transmitter circuit 120, and the receiver circuit 130” requires controlling at least something, thus it is “a control chip”).
Regarding claim 35: Koo in view of Lin discloses the multi-chip package of claim 1 (Koo: Fig. 1), wherein the second semiconductor integrated-circuit (IC) chip is a power-management integrated-circuit (PMIC) chip ([0026]: “The system-on-chip 100 may adjust driving voltages of the logic circuit 110, the transmitter circuit 120, and the receiver circuit 130” is controlling power, thus it is “a power-management integrated-circuit (PMIC) chip”).
Regarding claim 36, Koo in view of Lin as applied above discloses the multi-chip package of claim 1, but fails to teach structural configurations of the chips. Thus, the combination as applied fails to teach “wherein the first semiconductor integrated- circuit (IC) chip has a bottom surface at a first horizontal level and comprises a second metal bump protruding from the bottom surface of the first semiconductor integrated-circuit (IC) chip, wherein the second semiconductor integrated-circuit (IC) chip has a top surface at a second horizontal level below the first horizontal level and couples to the second metal bump”.
Nevertheless, Lin discloses these structural configurations for a multi-chip package (Fig. 25B), wherein the first semiconductor integrated-circuit (IC) chip (See annotated figure for chip designation) has a bottom surface (See annotated figure for direction designation) at a first horizontal level (See dashed reference line) and comprises a second metal bump (563b) protruding (vertically protruding) from the bottom surface of the first semiconductor integrated-circuit (IC) chip, wherein the second semiconductor integrated-circuit (IC) chip (See annotated figure for chip designation) has a top surface (See annotated figure for direction designation) at a second horizontal level (See dashed reference line) below the first horizontal level (vertically below) and couples to the second metal bump (indirectly couples).
Combining these separately disclosed features of the prior art (i.e., the circuitry of Koo with the structures of Lin) would arrive at the claimed package configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Koo makes no particular requirements for structures and Lin makes no particular requirements for circuitry. A person of ordinary skill in the art before the effective filing date would have been motivated to combine these separately disclosed features because Koo teaches the circuitry offering efficient operation ([0026]: “efficiently manage power consumption”), while Lin teaches the structure offering compact package size ([0051]: “stacked format” which offers a smaller package footprint). Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because it would enable a package with reduced power consumption and compact size. MPEP 2143 (I)(G).
Regarding claim 37, Koo in view of Lin discloses the multi-chip package of claim 36 (Lin: Fig. 25B), wherein the second semiconductor integrated-circuit (IC) chip (159) comprises a silicon substrate (Fig. 22: 688; [0344]: “through silicon vias” requires the substrate to be silicon) and a through silicon via (TSV) ([0344]: “through silicon vias”) vertically in the silicon substrate and coupling to the first metal bump (indirectly coupling).
Regarding claim 38, Koo in view of Lin discloses the multi-chip package of claim 36 (Lin: Fig. 22), wherein the second semiconductor integrated-circuit (IC) chip further comprises a transistor (See Fig. 16: transistor 4) at a top of the silicon substrate (designating the entire silicon substrate as the top, corresponding to Fig. 16: substrate 2), an interconnection scheme (697, corresponding to Fig. 16: schemes 20 and 29) over the silicon substrate and a metal contact (Fig. 22, the exposed surface of TSV 689) on a top surface of the interconnection scheme (indirectly on), at a top of the second semiconductor integrated-circuit (IC) chip (directly at the top) and coupling to the second metal bump (indirectly coupling).
Regarding claim 39, Koo in view of Lin discloses the multi-chip package of claim 36 (Lin: Fig. 25B) further comprising a polymer layer (See annotated figure, 565: [0345]: “polymer layer”) having a first and a second portion (left and right portions, See annotated figure for direction designation), wherein the second semiconductor integrated-circuit (IC) chip is horizontally between the first and second portions of the polymer layer (sandwiched between, See annotated figure for direction designation).
Regarding claim 40, Koo in view of Lin discloses the multi-chip package of claim 39 (Fig. 25B), wherein the polymer layer comprises a molding compound ([0335]: “molding”).
Regarding claim 41, Koo in view of Lin discloses the multi-chip package of claim 36, wherein the second metal bump comprises tin ([0332]: “solder caps”; [0270]: “tin-containing solder cap”).
Regarding claim 42, Koo in view of Lin discloses the multi-chip package of claim 36 (Lin: Fig. 25B) further comprising an underfill (564) at a bottom of the first semiconductor integrated-circuit (IC) chip and in contact (direct contact) with a sidewall of the second metal bump.
Allowable Subject Matter
Claims 5, 10-12, 22-23, and 26-30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claim 5 is the inclusion of the limitation “wherein each of the first and second input/output (I/O) circuits has an output capacitance smaller than that of the third input/output (I/O) circuit” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “output capacitance”, “smaller than”, and “third input/output (I/O) circuit” in combination with all other limitations in claims 5 and 1. More specifically: although output capacitances are generally known in the prior art; the claim goes beyond a mere recitation of this measurable property by requiring a specific relation among these capacitances/properties and this specific relation was not rendered obvious by the prior art. MPEP 2144.04 (IV)(A).
The primary reason for the allowable subject matter of claims 10-12, 30 is the inclusion of the limitation “a third semiconductor integrated-circuit (IC) chip comprising a fourth input/output (I/O) circuit, wherein the first semiconductor integrated-circuit (IC) chip comprises a fifth input/output (I/O) circuit coupling to the fourth input/output (I/O) circuit, wherein each of the fourth and fifth input/output (I/O) circuits has a driving capability smaller than that of the third input/output (I/O) circuit” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “fourth input/output (I/O) circuit”, “fifth input/output (I/O) circuit”, “driving capability”, “smaller than”, and “third input/output (I/O) circuit” in combination with all other limitations in claims 10 and 1. More specifically: although driving capabilities are generally known in the prior art; the claim goes beyond a mere recitation of this measurable property by requiring a specific relation among these capacitances/properties and this specific relation was not rendered obvious by the prior art. MPEP 2144.04 (IV)(A).
The primary reason for the allowable subject matter of claim 22 is the inclusion of the limitation “wherein each of the first and second input/output (I/O) circuits has a driving capability smaller than that of the third input/output (I/O) circuit” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first and second input/output (I/O) circuits”, “driving capability”, “smaller than”, and “third input/output (I/O) circuit” in combination with all other limitations in claims 22 and 1. More specifically: although driving capabilities are generally known in the prior art; the claim goes beyond a mere recitation of this measurable property by requiring a specific relation among these capacitances/properties and this specific relation was not rendered obvious by the prior art. MPEP 2144.04 (IV)(A).
The primary reason for the allowable subject matter of claim 23 is the inclusion of the limitation “wherein each of the first and second input/output (I/O) circuits has an input/output (I/O) power efficiency smaller than that of the third input/output (I/O) circuit” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first and second input/output (I/O) circuits”, “input/output (I/O) power efficiency”, “smaller than”, and “third input/output (I/O) circuit” in combination with all other limitations in claims 23 and 1. More specifically: although power efficiencies are generally known in the prior art; the claim goes beyond a mere recitation of this measurable property by requiring a specific relation among these capacitances/properties and this specific relation was not rendered obvious by the prior art. MPEP 2144.04 (IV)(A).
The primary reason for the allowable subject matter of claim 26 is the inclusion of the limitation “wherein each of the fourth and fifth input/output (I/O) circuits has an output capacitance smaller than that of the third input/output (I/O) circuit” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “output capacitance”, “smaller than”, and “third input/output (I/O) circuit” in combination with all other limitations in claims 26 and 1. More specifically: although output capacitances are generally known in the prior art; the claim goes beyond a mere recitation of this measurable property by requiring a specific relation among these capacitances/properties and this specific relation was not rendered obvious by the prior art. MPEP 2144.04 (IV)(A).
The primary reason for the allowable subject matter of claims 27-29 is the inclusion of the limitation “a third semiconductor integrated-circuit (IC) chip comprising a fourth input/output (I/O) circuit, wherein the second semiconductor integrated-circuit (IC) chip comprises a fifth input/output (I/O) circuit coupling to the fourth input/output (11O) circuit, wherein each of the fourth and fifth input/output (I/O) circuits has a driving capability smaller than that of the third input/output (I/O) circuit” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “fourth input/output (I/O) circuit”, “fifth input/output (I/O) circuit”, “driving capability”, “smaller than”, and “third input/output (I/O) circuit” in combination with all other limitations in claims 27 and 1. More specifically: although driving capabilities are generally known in the prior art; the claim goes beyond a mere recitation of this measurable property by requiring a specific relation among these capacitances/properties and this specific relation was not rendered obvious by the prior art. MPEP 2144.04 (IV)(A).
Response to Arguments
Applicant's arguments filed 2/10/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 1 that “the above subject matter are not obvious under Lin’s teaching in view of Tuan’s teaching”. Remarks at pg. 20.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner agrees with Applicant’s remarks for reasons consistent with Applicant’s arguments, however, the amendments to claim 1 change the scope of the claim which has necessitated the use of a new reference (Koo) in the instant Office action.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
/Kretelia Graham/ Supervisory Patent Examiner, Art Unit 2817 March 9, 2026