Attorney Docket Number: Q287523
Filing Date: 08/08/2023
Claimed Priority Date: 01/04/2023 (KR 10-2023-0001400)
Inventors: Ryu et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the election filed on 01/21/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Elections/Restrictions
Applicant’s election with traverse of Species 5, reading on figure 12, in view of figures 4 and 5A as per par.010//ll.6-7 of US 2024/0222401, in the reply filed on 01/21/2026, is acknowledged. The applicant indicated that claims 1-20 read on the elected species. The examiner agrees. Accordingly, pending in this Office action are claims 1-20.
The traversal is on the grounds that there is no serious burden in examining all species on the merits because the species disclose overlapping subject matter. This is not found persuasive. It is not that the species might overlap in subject matter, it is that because of their mutually exclusive characteristics, searching all species would require different fields of search, and the prior art applicable to one species would not likely be applicable to the other species. On pages 2-3 of the previous restriction requirement mailed on 12/18/2025, the examiner set forth that the application contained several species, each including mutually exclusive characteristics. These exclusive characteristics make the species patentably distinct from each other. That is, the unpatentability of one of the species would not necessarily imply the unpatentability of the other species. Accordingly, the prior art applicable to one of the species would not likely be applicable to the other species as the species are likely to raise different prior art issue. This creates a serious burden in examining all species on the merits. The applicants, however, other than broadly arguing that the species are related in concept, have failed to advance any reasons leading to the conclusion that the species claimed are considered clearly unpatentable over each other. Accordingly, the requirement is still deemed proper and is, therefore, made final.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8-20 are rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 8 recites the limitation “a substrate including a plurality of pixels” before reciting the limitation “a first impurity region in the substrate in each of the pixels”. The language of claims does not distinctly clarify whether the limitation “in the substrate in each of the pixels” is intended to mean that a first impurity region is located in a substrate included in each of the pixels or is intended to mean that a first impurity region is in the previously-recited substrate and in each of the previously-recited pixels. In the event that the limitation is intended to mean that a first impurity region is located in a substrate included in each of the pixels, there is insufficient antecedent basis for this limitation in the claim. Accordingly, this limitation in the claim is indefinite, as it is unclear how the limitation “in the substrate in each of the pixels” is meant to be structurally interpreted. For the express purposes of examination, the limitation “a first impurity region in the substrate in each of the pixels” is construed as “a first impurity region in the substrate and in each of the pixels”.
Claim 16 recites the limitation “a substrate comprising a plurality of pixels” before reciting the limitation “a floating diffusion region in the substrate in each of the pixels”. The language of claims does not distinctly clarify whether the limitation “in the substrate in each of the pixels” is intended to mean that a floating diffusion region is located in a substrate included in each of the pixels or is intended to mean that a floating diffusion region is in the previously-recited substrate and in each of the previously-recited pixels. In the event that the limitation is intended to mean that a floating diffusion region is located in a substrate included in each of the pixels, there is insufficient antecedent basis for this limitation in the claim. Accordingly, this limitation in the claim is indefinite, as it is unclear how the limitation “in the substrate in each of the pixels” is meant to be structurally interpreted. For the express purposes of examination, the limitation “a floating diffusion region in the substrate in each of the pixels” is construed as “a floating diffusion region in the substrate and in each of the pixels”.
Claims 9-15 depend from claim 8 and thus inherit the deficiencies identified supra.
Claims 17-20 depend from claim 16 and thus inherit the deficiencies identified supra.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu (US 9,985,023).
Regarding claim 1, Liu (see, e.g., fig. 3J) shows all aspects of the instant invention, including a semiconductor device comprising:
a gate pattern 200 disposed on a substrate 100/110;
a first interlayer insulating layer 170 on a sidewall of the gate pattern;
a second interlayer insulating layer 260 on the gate pattern and the first interlayer insulating layer;
a first contact plug 290 passing through the second interlayer insulating layer and the first interlayer insulating layer and being in contact with the substrate;
wherein:
the first contact plug 290 comprises a first contact part 294 in the first interlayer insulating layer 170 and a second contact part 292 in the second interlayer insulating layer 260;
the first contact part of the first contact plug has a first width C; and
the second contact part of the first contact plug has a second width A smaller than the first width (see, e.g., col.14/ll.14)
Regarding claim 1, Liu (see, e.g., fig. 3J) shows all aspects of the instant invention, including a semiconductor device comprising:
a gate pattern 200 disposed on a substrate 100/110;
a first interlayer insulating layer 260 on a sidewall of the gate pattern;
a second interlayer insulating layer 190 on the gate pattern and the first interlayer insulating layer;
a first contact plug 290 passing through the second interlayer insulating layer and the first interlayer insulating layer and being in contact with the substrate
wherein:
the first contact plug 290 comprises a first contact part in the first interlayer insulating layer 260 and a second contact part in the second interlayer insulating layer 190;
the first contact part of the first contact plug has a first width A; and
the second contact part of the first contact plug has a second width B smaller than the first width (see, e.g., col.11/ll.21-22)
Claims 1 and 4-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee I (US 2020/0119150).
Regarding claim 1, Lee I (see, e.g., figs. 2D and 4) shows all aspects of the instant invention, including a semiconductor device comprising:
a gate pattern 115/110/125/120 disposed on a substrate 100/AF/SDP;
a first interlayer insulating layer 130 disposed on a sidewall of the gate pattern;
a second interlayer insulating layer 150 on the gate pattern and the first interlayer insulating layer; and
a first contact plug SCP passing through the second interlayer insulating layer and the first interlayer insulating layer and being in contact with the substrate;
wherein:
the first contact plug SCP comprises a first contact part (SC1 in 130 and above and not in SDP) in the first interlayer insulating layer 130 and a second contact part SC2 in the second interlayer insulating layer;
the first contact part of the first contact plug has a first width (e.g., WD3’); and
the second contact part of the first contact plug has a second width WD4’ smaller than the first width (see, e.g., pars.0033/ll.15-17 and 0034/ll.6-9)
Regarding claim 4, Lee I (see, e.g., figs. 2D and 4) shows that the gate pattern 115/110/125/120 comprises a gate insulating layer 115, a gate electrode 110, and a gate capping pattern 120, wherein:
the semiconductor device further comprises a second contact plug GCP passing through the second interlayer insulating layer 150 and the gate capping pattern 120;
the second contact plug is in contact with the gate electrode 110;
the second contact plug comprises a third contact part GC1 in the gate capping pattern and a fourth contact part GC2 in the second interlayer insulating layer;
the third contact part of the second contact plug has a third width WD1’; and
the fourth contact part of the second contact plug has a fourth width WD2’ smaller than the third width (see, e.g., par.0030/ll.15-17)
Regarding claim 5, Lee I (see, e.g., figs. 2D and 4 and par.0034/ll.6-9) shows that the first contact plug SCP further comprises a third contact part (SC1 in SDP) in the substrate, and wherein the third contact part of the first contact plug has a third width smaller than the first width (e.g., WD3’ in 130) (see, e.g., pars.0033/ll.10-17 and 0034/ll.6-9).
Regarding claim 6, Lee I (see, e.g., fig. 4 and par.0037) shows that the first contact plug SCP comprises a metal pattern 310 and a diffusion barrier pattern 320 on a sidewall of the metal pattern.
Regarding claim 7, Lee I (see, e.g., fig. 4) shows that an upper surface of the first interlayer insulating layer 130 is coplanar with an upper surface of the gate pattern 115/110/125/120.
Claims 8 and 14 are rejected under 35 U.S.C. 103 under 35 U.S.C. 102(a)(1) as being anticipated by Lee II (US 2021/0335862).
Regarding claim 8, Lee II (see, e.g., figs. 2B, 3C, 4A, 5C, and 8) shows all aspects of the instant invention, including an image sensor comprising:
a substrate (all features including and between 100a and 100b – henceforth referred to as 100) including a plurality of pixels PX;
a first impurity region 111 in the substrate and in each of the pixels (see, e.g., par.0060/ll.1-3 and 11-15);
a first interlayer insulating layer 420 on the substrate;
a second interlayer insulating layer 410 on the first interlayer insulating layer; and
a first contact plug CT passing through the second interlayer insulating layer and the first interlayer insulating layer and being in contact with the substrate;
wherein:
the first contact plug CT comprises a first contact part (CT in 420) in the first interlayer insulating layer 410 and a second contact part (CT in 410) in the second interlayer insulating layer;
the first contact part of the first contact plug has a first width W11; and
the second contact part of the first contact plug has a second width W1 smaller than the first width (see, e.g., par.0059/ll.1-3)
Regarding claim 14, Lee II (see, e.g., fig. 4A and pars.0058/ll.1-6, 0059/ll.1-3, and 0092/ll.1) shows that the first contact plug CT further comprises a third contact part (CT below 100a and 410) in the substrate 100, wherein the third contact part of the first contact plug has a third width (W1 or less) smaller than the first width W11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Lee I.
Regarding claim 1, Liu (see, e.g., fig. 3J) shows most aspects of the instant invention, including a semiconductor device comprising:
a gate pattern 200 disposed on a substrate 100/110;
a first interlayer insulating layer 190 on a sidewall of the gate pattern;
a second interlayer insulating layer 260 on the gate pattern and the first interlayer insulating layer;
a first contact plug 290 passing through the second interlayer insulating layer and the first interlayer insulating layer and being in contact with the substrate
wherein:
the first contact plug 290 comprises a first contact part (292 in 190) in the first interlayer insulating layer 190 and a second contact part (292 in 260) in the second interlayer insulating layer;
the first contact part of the first contact plug has a first width (smallest horizontal width of 292 in 190, corresponding to B); and
the second contact part of the first contact plug has a second width A have a relation to the first width (see, e.g., col.14/ll.14)
Although Liu teaches most aspects of the instant invention, Liu fails to explicitly illustrate that the second width is smaller than the first width. However, Liu does teach that the first width and second width are not limited and may have a relationship not explicitly illustrated in Liu’s disclosure, wherein Liu further teaches that the widths of contact plugs may be desirably adjusted so as to prevent short circuiting, avoid defects, and modulate contact resistance (see, e.g., Liu: cols.11/ll.31-32 and 14/ll.15-33). Liu (see, e.g., fig. 3J) also shows that Liu’s device includes adjacent contact plugs. Lee I, in the same field of endeavor and in a similar structure to Liu, teaches a first contact plug SCP having a first contact part SC1 in a first interlayer insulating layer 130 or 130/140 and a second contact part SC2 in a second interlayer insulating layer 150, wherein the second contact part has a second width WD4’ smaller than a first width WD3’ of the first contact part (see, e.g., Lee I: figs. 2D and 4 and par.0033/ll.15-17). Lee I teaches that such a structure allows the first contact part to act as and include a barrier for the conductive contact plug while simultaneously permitting increased spacing between the second contact parts of adjacent contact plugs, thereby mitigating electrical shorting in the semiconductor device (see, e.g., Lee I: pars.0034-0036, 0039, and 0065).
Here, Liu’s express teaching that Liu’s first and second widths may take on relationships not explicitly illustrated taken together with its disclosure that the widths of contact plugs may be desirably adjusted so as to prevent short circuiting, avoid defects, and modulate contact resistance, would have suggested to one of ordinary skill in the art that the contact plug widths may be adjusted as a matter of routine optimization of a result-effective variable. Adjusting width to achieve predictable results, such as improved scaling, reduced material usage, or modified electrical/mechanical performance, as well as Liu’s express teachings of preventing short circuiting, avoiding defects, and modulating contact resistance, would have been well within the ordinary skill in the art. No evidence of criticality or unexpected results for the claimed dimensional relationship is apparent. Accordingly, the claimed limitation represents an obvious optimization of a result-effective variable.
Moreover, Lee I is evidence that it would have been obvious at the time of filing the invention that one of ordinary skill in the art would find particular incentive to have a second width smaller than a first width, as taught by Lee I, so as to include an advantageous barrier-acting portion in Liu’s first contact plug while simultaneously permitting increased spacing between adjacent contact plugs, thereby mitigating electrical shorting.
Regarding claim 3, Liu (see, e.g., fig. 3J) shows that Liu’s semiconductor device further comprises an etch stop layer 180 between a sidewall of the gate pattern 200 and the first interlayer insulating layer 190 and between the substrate 100/110 and the first interlayer insulating layer, wherein the first contact plug 290 further comprises a third contact part 294 penetrating the etch stop layer, and wherein the third contact part of the first contact plug has a third width C greater than the second width A (see, e.g., cols.12/ll.26 and 14/ll.14).
Claims 8, 10, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee II in view of Lee I and Liu.
Regarding claim 8, Lee II (see, e.g., figs. 2B, 3C, 5C, and 8) shows most aspects of the instant invention, including an image sensor comprising:
a substrate (all features including and between 100a and 100b – henceforth referred to as 100) including a plurality of pixels PX;
a first impurity region 111 in the substrate and in each of the pixels (see, e.g., par.0060/ll.1-3 and 11-15);
a first interlayer insulating layer 410 on the substrate;
a second interlayer insulating layer 420 on the first interlayer insulating layer; and
a first contact plug 370 passing through the second interlayer insulating layer and the first interlayer insulating layer and being in contact with the substrate;
wherein:
the first contact plug 370 comprises a first contact part (370 in 410) in the first interlayer insulating layer 410 and a second contact part (370 in 420) in the second interlayer insulating layer 420;
the first contact part of the first contact plug has a first width; and
the second contact part of the first contact plug has a second width
Lee II teaches most aspects of the instant invention. Lee II further teaches that contact plug widths may be non-uniform and may additionally be adjusted and structured so as to improve contact properties and accomplish improved image characteristics, demonstrating that Lee II recognizes the importance and structural value of controlling and modulating contact plug widths in semiconductor devices (see, e.g., fig. 3C and par.0059). Lee II further shows that Lee II’s first contact plug is adjacent other conductive contact plug structures (see, e.g., fig. 3C). Lee II, however, fails to explicitly specify a relationship between the first and second width, including if the second width is smaller than the first width.
Lee I, in the same field of endeavor and in a similar structure to Lee II, teaches a first contact plug SCP having a first contact part SC1 in a first interlayer insulating layer 130 or 130/140 and a second contact part SC2 in a second interlayer insulating layer 150, wherein the second contact part has a second width WD4’ smaller than a first width WD3’ of the first contact part (see, e.g., Lee I: figs. 2D and 4 and par.0033/ll.15-17). Lee I further teaches that such a structure allows the first contact part to act as and include a barrier for the conductive contact plug while simultaneously permitting increased spacing between the second contact parts of adjacent contact plugs, thereby mitigating electrical shorting in the semiconductor device (see, e.g., Lee I: pars.0034-0036, 0039, and 0065). Liu, also in the same field of endeavor and in a similar structure to Lee II, additionally teaches a first contact plug 290 having a first contact part (294 in 170) in a first interlayer insulating layer 170 and a second contact part 292 in a second interlayer insulating layer 190, wherein the second contact part has a second width B smaller than a first width C of the first contact part (see, e.g., Liu: fig. 3J and col.12/ll.22-23). Liu teaches that such a width difference between first and second contact parts reduces contact resistance, enhances operation speed, promotes device miniaturization/scalability, ensures sufficient electrical connection, and improves device performance and reliability (see, e.g., Liu: col.14/ll.15-65).
Lee I is evidence that it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a second width smaller than a first width, as taught by Lee I, so as to include an advantageous barrier-acting portion in Lee II’s first contact plug while simultaneously permitting increased spacing between adjacent contact plugs, thereby mitigating electrical shorting. Furthermore, Liu is additional evidence that it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have in the first contact plug a second width smaller than a first width, as taught by Liu, so as to reduce contact resistance, enhance operation speed, ensure sufficient electrical connection, and improve device performance and reliability while promoting scalability and miniaturization in Lee II’s device.
Moreover, Lee II’s express teaching that the widths of contact plugs may be non-uniform taken together with its disclosure that the widths of contact plugs may be desirably adjusted so as to improve contact properties and image characteristics would have suggested to one of ordinary skill in the art that the first and second contact part and plug widths may be adjusted as a matter of routine optimization of a result-effective variable. Adjusting width to achieve predictable results, such as improved scaling, reduced material usage, or modified electrical/mechanical performance, as well as Lee II’s express teachings of improved contact properties and image characteristics, would have been well within the ordinary skill in the art. No evidence of criticality or unexpected results for the claimed dimensional relationship is apparent. Accordingly, the claimed limitation represents an obvious optimization of a result-effective variable.
With regards to other language recited in claim 8, see the comments stated above in paragraph 6.
Regarding claim 10, Lee II/Liu/Lee I shows most aspects of the instant invention (see paragraphs 31-36 above). Furthermore, Lee II teaches that trenches may be employed to create space for vertical contact structures in Lee II’s device (see, e.g., pars.0045 and 0092/ll.1-3). Lee II, however, fails to specify that Lee II’s overall device comprises an etch stop layer between the substrate and the first interlayer insulating layer, wherein the first contact plug further includes a third contact part penetrating the etch stop layer, and wherein the third contact part of the first contact plug has a third width greater than the second width. Liu (see, e.g., Liu: fig. 3J and col.12/ll.22-23) shows an etch stop layer 180 between the substrate 100/110 and the first interlayer insulating layer 190, wherein the first contact plug 290 includes a third contact part (294 in 180) penetrating the etch stop layer, and wherein the third contact part of the first contact plug has a third width C greater than a second width B of a second contact part 292. Liu teaches that the inclusion of such an etch stop layer and penetration structure beneficially aids in forming trenches for forming the first contact plug while promoting miniaturization and permitting manufacturing variability by allowing sufficient contact space and electrical connection with underlying structures (see, e.g., Liu: fig. 3J and cols.11/ll.1-5 and 14/ll.48-55). Furthermore, Liu teaches that having a third contact part having a third width greater than the second width reduces contact resistance, enhances operation speed, promotes device miniaturization/scalability, ensures sufficient electrical connection, and improves device performance and reliability (see, e.g., Liu: col.14/ll.15-65).
Therefore, Liu is evidence that it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include an etch stop layer between the substrate and the first interlayer insulating layer, wherein the first contact plug further includes a third contact part penetrating the etch stop layer, as taught by Liu, so as to beneficially aid in forming trenches for forming the first contact plug while promoting miniaturization and permitting manufacturing variability by allowing sufficient contact space and electrical connection with underlying structures. Furthermore, Liu is additional evidence that it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have in the first contact plug a third width greater than the second width, as taught by Liu, so as to reduce contact resistance, enhance operation speed, ensure sufficient electrical connection, and improve device performance and reliability while promoting scalability and miniaturization in Lee II’s device.
Regarding claim 10, Liu (see, e.g., Liu: fig. 3J and col.12/ll.22-23) shows an etch stop layer 180 between the substrate 100/110 and the first interlayer insulating layer 190, wherein the first contact plug 290 includes a third contact part (294 in 180) penetrating the etch stop layer, and wherein the third contact part of the first contact plug has a third width C greater than the second width B.
Regarding claim 15, Lee I (see, e.g., fig. 4 and par.0037) shows that the first contact plug SCP comprises a metal pattern 310 and a diffusion barrier pattern 320 on a sidewall of the metal pattern.
Claims 16-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee II in view of Lee I, Liu, and Mouli (US 2007/0012970).
Regarding claim 16, Lee II (see, e.g., figs. 2B, 3C, 5C, and 8) shows most aspects of the instant invention, including an image sensor comprising:
a substrate (all features including and between 100a and 100b – henceforth referred to as 100) comprising a plurality of pixels PX;
a floating diffusion region 111 in the substrate and in each of the pixels (see, e.g., par.0060/ll.1-3 and 11-15);
a first interlayer insulating layer 410 on the substrate;
a second interlayer insulating layer 420 on the first interlayer insulating layer; and
a first contact plug 370 passing through the second interlayer insulating layer and the first interlayer insulating layer and being in contact with the substrate;
a transfer gate pattern 300/315 disposed on the substrate next to the floating diffusion region in each of the pixels and covered with the second interlayer insulating layer, the transfer gate pattern comprising a gate insulating layer 315 and a gate electrode 300; and
a second contact plug 360 passing through the second interlayer insulating layer and being in contact with the gate electrode;
wherein:
a first distance between an upper portion of the first contact plug 370 and an upper portion of the second contact plug 360 appears to be greater than a second distance between a lower portion of the first contact plug and a lower portion of the second contact plug
Lee II teaches most aspects of the instant invention. Lee II further teaches that the second contact plug contacts the gate electrode through an insulating layer located over the gate pattern. Lee II, however, fails to specify that the gate pattern comprises a gate capping pattern and that the second contact plug passes through the gate capping pattern. Liu, in the same field of endeavor and in a similar device to Lee II, teaches a second contact plug 310 passing through a gate capping pattern 250 included in a gate pattern 200, wherein the gate pattern further comprises a gate insulating layer 210 and a gate electrode 240 (see, e.g., Liu: fig. 3J). Liu teaches that both gate patterns formed with a gate capping pattern such that a second contact plug passes through the gate capping pattern and gate patterns formed without a gate capping pattern such that a second contact plug may not pass through the gate capping pattern are both viable embodiments for second contact plug structures, wherein Liu additionally teaches that openings penetrating through the gate capping pattern facilitate contact between the second conductive plug and the gate electrode (see, e.g., Liu: fig. 3J and col.20-27 and 15/ll.3-5). Additionally, Mouli, in the same field of endeavor and in a similar device to Lee II, teaches that gate capping patterns may be included in gate patterns, wherein such gate capping patterns serve to insulate and protect underlying conductive gate electrodes (see, e.g., Mouli: par.0042/ll.7-9).
Liu is evidence showing that one of ordinary skill in the art would appreciate that a gate pattern comprising a gate capping pattern such that a second contact plug passes through the gate capping pattern would be equivalent to another gate pattern and a second contact plug passing through another insulative feature, and that such differences would result in no unexpected changes in the performance of the device of Lee II. That is, the gate patterns and second contact plug dispositions of both Lee II and Liu would yield the predictable result of providing suitable and functional gate patterns underlying an insulative feature facilitating appropriate contact between a second contact plug and a gate electrode.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a gate contact pattern comprising a gate capping pattern such that a second contact plug passes through a gate capping pattern, as taught by Liu, or another gate pattern and a second contact plug passing through another insulative feature, as taught by Liu and/or Lee II, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable and functional gate patterns underlying an insulative feature facilitating appropriate contact between a second contact plug and a gate electrode. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Moreover, Mouli and Liu are evidence that it would have been obvious that at the time of filing the invention one of ordinary skill in the art would find particular incentive to include in Lee II’s gate pattern a gate capping pattern such that the second contact plug passes through the gate capping pattern, as taught by Mouli and Liu, so as to include an insulative and protective gate feature in Lee II’s device while simultaneously facilitating contact between Lee II’s second contact plug and gate electrode, as already taught to be desired by Lee II.
Lee II further teaches that contact plug widths may be non-uniform and may additionally be adjusted and structured so as to improve contact properties and accomplish improved image characteristics, demonstrating that Lee II recognizes the importance and structural value of controlling and modulating contact plug widths in semiconductor devices (see, e.g., fig. 3C and par.0059). Lee II further shows that Lee II’s first contact plug is adjacent other conductive contact plug structures, including the second contact plug (see, e.g., fig. 3C). Lee II, however, fails to explicitly specify that a first distance between an upper portion of the first contact plug and an upper portion of the second contact plug is greater than a second distance between a lower portion of the first contact plug and a lower portion of the second contact plug.
Lee I, in the same field of endeavor and in a similar structure to Lee II, teaches a first contact plug SCP having a horizontally wider lower portion SC1 in a first interlayer insulating layer 130 or 130/140 and a horizontally thinner upper portion SC2 in a second interlayer insulating layer 150. Lee I also teaches a second contact plug GCP adjacent the first contact plug having a horizontally wider lower portion GC1 in a gate capping pattern 120 and a horizontally thinner upper portion GC2 in the second interlayer insulating layer. Lee I (see, e.g., fig. 4 and pars.0030/ll.10-16 and 0033/ll.10-17) further shows that a first distance between the upper portion of the first contact plug and the upper portion of the second contact plug is greater than a second distance between the lower portion of the first contact plug and the lower portion of the second contact plug. Lee I teaches that such contact plug structures and dispositions increases spacing between the upper portions of the first and second contact plugs, thereby mitigating electrical shorting in the overall device, while simultaneously allowing the lower portions of the contact plugs to act as and include advantageous barrier portions (see, e.g., Lee I: pars.0034-0036, 0039, and 0065).
Lee I is evidence that it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a first distance between an upper portion of the first contact plug and an upper portion of the second contact plug be greater than a second distance between a lower portion of the first contact plug and a lower portion of the second contact plug, as taught by Lee I, so as to increase spacing between the upper portions of the adjacent contact plugs, thereby mitigating electrical shorting in the semiconductor device, while simultaneously allowing the lower portions of the contact plugs to act as and include advantageous barrier portions.
Moreover, Lee II’s express teaching that the widths of contact plugs may be non-uniform taken together with its disclosure that the widths of contact plugs may be desirably adjusted so as to improve contact properties and image characteristics, along with Lee I’s disclosure that adjusting spacing between contact plug portions may beneficially mitigate electrical shorting, would have suggested to one of ordinary skill in the art that the first and second distances may be adjusted as a matter of routine optimization of a result-effective variable. Adjusting distance to achieve predictable results, such as improved scaling, reduced material usage, or modified electrical/mechanical performance, as well as Lee II’s express teachings of improved contact properties and image characteristics and Lee I’s express teachings of electrical shorting mitigation, would have been well within the ordinary skill in the art. No evidence of criticality or unexpected results for the claimed dimensional relationship is apparent. Accordingly, the claimed limitation represents an obvious optimization of a result-effective variable.
With regards to other language recited in claim 16, see the comments stated above in paragraph 7.
Regarding claim 17, Lee II teaches most aspects of the instant invention, including that the first contact plug has a first contact part with a first with and a second contact part with a second width (see, e.g., figs. 2B, 3C, 5C, and 8). Lee II further teaches that contact plug widths may be non-uniform and may additionally be adjusted and structured so as to improve contact properties and accomplish improved image characteristics, demonstrating that Lee II recognizes the importance and structural value of controlling and modulating contact plug widths in semiconductor devices (see, e.g., fig. 3C and par.0059). Lee II further shows that Lee II’s first contact plug is adjacent other conductive contact plug structures and appears to show that Lee II’s second width is smaller than Lee II’s first width (see, e.g., fig. 3C). Lee II, however, fails to explicitly specify a relationship between the first and second width, including if the second width is smaller than the first width.
Lee I, in the same field of endeavor and in a similar structure to Lee II, teaches a first contact plug SCP having a first contact part SC1 in a first interlayer insulating layer 130 or 130/140 and a second contact part SC2 in a second interlayer insulating layer 150, wherein the second contact part has a second width WD4’ smaller than a first width WD3’ of the first contact part (see, e.g., Lee I: figs. 2D and 4 and par.0033/ll.15-17). Lee I further teaches that such a structure allows the first contact part to act as and include a barrier for the conductive contact plug while simultaneously permitting increased spacing between adjacent contact plugs, thereby mitigating electrical shorting in the semiconductor device (see, e.g., Lee I: pars.0034-0036, 0039, and 0065). Liu, also in the same field of endeavor and in a similar structure to Lee II, additionally teaches a first contact plug 290 having a first contact part (294 in 170) in a first interlayer insulating layer 170 and a second contact part 292 in a second interlayer insulating layer 190, wherein the second contact part has a second width B smaller than a first width C of the first contact part (see, e.g., Liu: fig. 3J and col.12/ll.22-23). Liu teaches that such a width difference between first and second contact parts reduces contact resistance, enhances operation speed, promotes device miniaturization/scalability, ensures sufficient electrical connection, and improves device performance and reliability (see, e.g., Liu: col.14/ll.15-65).
Lee I is evidence that it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a second width smaller than a first width, as taught by Lee I, so as to include an advantageous barrier-acting portion in Lee II’s first contact plug while simultaneously permitting increased spacing between adjacent contact plugs, thereby mitigating electrical shorting. Furthermore, Liu is additional evidence that it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have in the first contact plug a second width smaller than a first width, as taught by Liu, so as to reduce contact resistance, enhance operation speed, ensure sufficient electrical connection, and improve device performance and reliability while promoting scalability and miniaturization in Lee II’s device.
Moreover, Lee II’s express teaching that the widths of contact plugs may be non-uniform taken together with its disclosure that the widths of contact plugs may be desirably adjusted so as to improve contact properties and image characteristics would have suggested to one of ordinary skill in the art that the first and second contact part widths may be adjusted as a matter of routine optimization of a result-effective variable. Adjusting width to achieve predictable results, such as improved scaling, reduced material usage, or modified electrical/mechanical performance, as well as Lee II’s express teachings of improved contact properties and image characteristics, would have been well within the ordinary skill in the art. No evidence of criticality or unexpected results for the claimed dimensional relationship is apparent. Accordingly, the claimed limitation represents an obvious optimization of a result-effective variable.
Regarding claim 17, Lee I (see, e.g., figs. 2D and 4 and pars.0033/ll.15-17 and 0034/ll.6-9), shows that the first contact part SC1 of the first contact plug has a first width (e.g., WD3’) and the second contact part SC2 of the first contact plug has a second width WD4’ smaller than the first width.
Regarding claim 19, Lee II/Liu/Lee I shows most aspects of the instant invention (see paragraphs 42-56 above). Furthermore, Lee II teaches that trenches may be employed to create space for vertical contact structures in Lee II’s device (see, e.g., pars.0045 and 0092/ll.1-3). Lee II, however, fails to specify that Lee II’s overall device comprises an etch stop layer interposed between the substrate and the first interlayer insulating layer, wherein the first contact plug further includes a third contact part penetrating the etch stop layer, and wherein the third contact part of the first contact plug has a third width greater than the second width. Liu (see, e.g., Liu: fig. 3J and col.12/ll.22-23) shows an etch stop layer 180 interposed between the substrate 100/110 and the first interlayer insulating layer 190, wherein the first contact plug 290 includes a third contact part (294 in 180) penetrating the etch stop layer, and wherein the third contact part of the first contact plug has a third width C greater than a second width B of a second contact part 292. Liu teaches that the inclusion of such an etch stop layer and penetration structure beneficially aids in forming trenches for forming the first contact plug while promoting miniaturization and permitting manufacturing variability by allowing sufficient contact space and electrical connection with underlying structures (see, e.g., Liu: fig. 3J and cols.11/ll.1-5 and 14/ll.48-55). Furthermore, Liu teaches that having a third contact part having a third width greater than the second width reduces contact resistance, enhances operation speed, promotes device miniaturization/scalability, ensures sufficient electrical connection, and improves device performance and reliability (see, e.g., Liu: col.14/ll.15-65).
Therefore, Liu is evidence that it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include an etch stop layer interposed between the substrate and the first interlayer insulating layer, wherein the first contact plug further includes a third contact part penetrating the etch stop layer, as taught by Liu, so as to beneficially aid in forming trenches for forming the first contact plug while promoting miniaturization and permitting manufacturing variability by allowing sufficient contact space and electrical connection with underlying structures. Furthermore, Liu is additional evidence that it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have in the first contact plug a third width greater than the second width, as taught by Liu, so as to reduce contact resistance, enhance operation speed, ensure sufficient electrical connection, and improve device performance and reliability while promoting scalability and miniaturization in Lee II’s device.
Regarding claim 19, Liu (see, e.g., Liu: fig. 3J and col.12/ll.22-23) shows an etch stop layer 180 interposed between the substrate 100/110 and the first interlayer insulating layer 190, wherein the first contact plug 290 includes a third contact part (294 in 180) penetrating the etch stop layer and a second contact part (294 in 190), and wherein the third contact part of the first contact plug has a third width C greater than a second width B of the second contact part.
Regarding claim 20, Lee I (see, e.g., figs. 2D and 4 and par.0030/ll.15-17) shows that the second contact plug GCP comprises a third contact part GC1 in the gate capping pattern 120 and a fourth contact part GC2 in the second interlayer insulating layer 150, wherein the third contact part of the second contact plug has a third width WD1’, and wherein the fourth contact part of the second contact plug has a fourth width WD2’ smaller than the third width.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee II/Lee I/Liu in view of Mouli.
Regarding claim 11, Lee II/Lee I/Liu shows most aspects of the instant invention (see paragraphs 31-35). Lee II (see, e.g., figs. 2B, 3C, 5C, and 8) further shows:
a gate pattern 300 on the substrate 100 next to the first impurity region 111 in each of the pixels PX (see the comments stated above in paragraph 6) and covered with the second interlayer insulating layer 420, the gate pattern comprising a gate insulating layer 302 and a gate electrode 301; and
a second contact plug 360 passing through the second interlayer insulating layer and an insulating layer 420 or 430 over the gate pattern, the second contact plug being in contact with the gate electrode;
wherein:
the second contact plug 360 comprises a third contact part in the insulating layer 420 or 430 over the gate pattern and a fourth contact part in the second interlayer insulating layer 420;
wherein the third contact part of the second contact plug has a third width; and
wherein the fourth contact part of the second contact plug has a fourth width having a relationship to the third width
Lee II shows most aspects of the instant invention. Lee II further teaches that the second contact plug contacts the gate electrode through an insulating layer located over the gate pattern. Lee II, however, fails to specify that the gate pattern comprises a gate capping pattern and that the second contact plug passes through the gate capping pattern. Liu, in the same field of endeavor and in a similar device to Lee II, teaches a second contact plug 310 passing through a gate capping pattern 250 included in a gate pattern 200, wherein the gate pattern further comprises a gate insulating layer 210 and a gate electrode 240 (see, e.g., Liu: fig. 3J). Liu teaches that both gate patterns formed with a gate capping pattern such that a second contact plug passes through the gate capping pattern and gate patterns formed without a gate capping pattern such that a second contact plug may not pass through the gate capping pattern are both viable embodiments for second contact plug structures, wherein Liu additionally teaches that openings penetrating through the gate capping pattern facilitate contact between the second conductive plug and the gate electrode (see, e.g., Liu: fig. 3J and col.20-27 and 15/ll.3-5). Additionally, Mouli, in the same field of endeavor and in a similar device to Lee II, teaches that gate capping patterns may be included in gate patterns, wherein such gate capping patterns serve to insulate and protect underlying conductive gate electrodes (see, e.g., Mouli: par.0042/ll.7-9).
Liu is evidence showing that one of ordinary skill in the art would appreciate that a gate pattern comprising a gate capping pattern such that a second contact plug passes through the gate capping pattern would be equivalent to another gate pattern and a second contact plug passing through another insulative feature, and that such differences would result in no unexpected changes in the performance of the device of Lee II. That is, the gate patterns and second contact plug dispositions of both Lee II and Liu would yield the predictable result of providing suitable and functional gate patterns underlying an insulative feature facilitating appropriate contact between a second contact plug and a gate electrode.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a gate contact pattern comprising a gate capping pattern such that a second contact plug passes through a gate capping pattern, as taught by Liu, or another gate pattern and a second contact plug passing through another insulative feature, as taught by Liu and/or Lee II, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable and functional gate patterns underlying an insulative feature facilitating appropriate contact between a second contact plug and a gate electrode. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Moreover, Mouli and Liu are evidence that it would have been obvious at the time of filing the invention that one of ordinary skill in the art would find particular incentive to include in Lee II’s gate pattern a gate capping pattern such that the second contact plug passes through the gate capping pattern, as taught by Mouli and Liu, so as to include an insulative and protective gate feature in Lee II’s device while simultaneously facilitating contact between Lee II’s second contact plug and gate electrode.
Additionally, Lee II teaches that contact plug widths may be non-uniform and may additionally be adjusted and structured so as to improve contact properties and accomplish improved image characteristics, demonstrating that Lee II recognizes the importance and structural value of controlling and modulating contact plug widths in semiconductor devices (see, e.g., fig. 3C and par.0059). Lee II further shows that Lee II’s second contact plug is adjacent other conductive contact plug structures (see, e.g., fig. 3C). Lee II, however, fails to explicitly specify a relationship between the third and fourth width, including if the fourth width is smaller than the third width.
Lee I, in the same field of endeavor and in a similar structure to Lee II, teaches a contact plug GCP having a third contact part GC1 in a gate capping pattern 120 and a fourth contact part GC2 in a second interlayer insulating layer 150, wherein the fourth contact part has a fourth width WD2’ smaller than a third width WD1’ of the third contact part (see, e.g., Lee I: figs. 2D and 4 and par.0030/ll.15-17). Lee I further teaches that such a structure allows the third contact part to act as and include a barrier for the conductive contact plug while simultaneously permitting increased spacing between adjacent contact plugs, thereby mitigating electrical shorting in the semiconductor device (see, e.g., Lee I: pars.0034-0036, 0039, and 0065). Liu, also in the same field of endeavor and in a similar structure to Lee II, additionally teaches a contact plug 290 having a third contact part (294 in 170) in a gate capping pattern and a fourth contact part 292 in a second interlayer insulating layer 190, wherein the fourth contact part has a fourth width smaller than a third width of the third contact part (see, e.g., Liu: fig. 3J and col.15/ll.55-67). Liu teaches that such a width difference between third and fourth contact parts enlarges the area for forming the second contact plug and reduces contact resistance between the second contact plug and the gate pattern (see, e.g., Liu: col.15/ll.55-67).
Lee I is evidence that it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a fourth width smaller than a third width, as taught by Lee I, so as to include an advantageous barrier-acting portion in Lee II’s third contact plug while simultaneously permitting increased spacing between adjacent contact plugs, thereby mitigating electrical shorting. Furthermore, Liu is additional evidence that it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a fourth width smaller than a third width, as taught by Liu, so as to enlarge the area for forming Lee II’s second contact plug while simultaneously reducing contact resistance between Lee II’s second contact plug and gate pattern.
Moreover, Lee II’s express teaching that the widths of contact plugs may be non-uniform taken together with its disclosure that the widths of contact plugs may be desirably adjusted so as to improve contact properties and image characteristics would have suggested to one of ordinary skill in the art that the third and fourth contact plug widths may be adjusted as a matter of routine optimization of a result-effective variable. Adjusting width to achieve predictable results, such as improved scaling, reduced material usage, or modified electrical/mechanical performance, as well as Lee II’s express teachings of increased manufacturing area and improved contact resistance, would have been well within the ordinary skill in the art. No evidence of criticality or unexpected results for the claimed dimensional relationship is apparent. Accordingly, the claimed limitation represents an obvious optimization of a result-effective variable.
Regarding claim 12, Lee I (see, e.g., fig. 4) shows that an upper surface of the first interlayer insulating layer 130 is coplanar with an upper surface of the gate pattern 115/110/125/120.
Regarding claim 13, Lee I (see, e.g., fig. 4 and pars.0030/ll.10-16 and 0033/ll.10-17) shows that a first distance between an upper portion of the first contact plug SCP and an upper portion of the second contact plug GCP is greater than a second distance between a lower portion of the first contact plug and a lower portion of the second contact plug. Furthermore, Liu (see, e.g., fig. 3J and cols.11/ll.27-31, 12/ll.24-28, and 16/ll.62-63) shows that a first distance between an upper portion of the first contact plug 290 and an upper portion of the second contact plug 310 is greater than a second distance between a lower portion of the first contact plug and a lower portion of the second contact plug. Additionally, Lee II (see, e.g., fig. 4A) appears to show that a first distance between an upper portion (portion of 370 in 420 and farthest from 100a) of the first contact plug 370 and an upper portion (portion of 360 in 420 closest to 100a) of the second contact plug 360 is greater than a second distance between a lower portion (portion of 370 in 410 and closest to 100a) of the first contact plug and a lower portion (portion of 360 in 420 farthest from 100a).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Jang (US 2021/0351220).
Regarding claim 2, Liu shows most aspects of the instant invention (see paragraph 12 above). Furthermore, Liu teaches that the dielectric materials selected for Liu’s interlayer insulating layers may be porous, wherein Liu further teaches that the material of such dielectric layers may be selected to minimize propagation delays and crosstalk between nearby conductive features (see, e.g., col.10/ll.34-37). Liu, however, fails to explicitly specify that a porosity of the first interlayer insulating layer 170 is greater than a porosity of the second interlayer insulating layer 260. Jang, in the same field of endeavor, teaches a device comprising interlayer insulating layers formed from materials similar to Liu’s interlayer insulating layers, wherein Jang further teaches that selection of certain materials for first and second interlayer insulating layers may result in a first interlayer insulating layer having a porosity greater than a porosity of a second interlayer insulating layer, wherein Jang additionally teaches that such a porosity difference is viable and functional in semiconductor devices (see, e.g., Jang: par.0039/ll.10-19).
Here, Liu’s express teaching that the material of dielectric layers may be selected to minimize propagation delays and crosstalk between nearby conductive structures taken together with its disclosure that porous materials are appropriate for use in Liu’s interlayer insulating layers and Jang’s disclosure that having a first interlayer insolating layer with a porosity greater than a porosity of a second interlayer insulating layer is viable for semiconductor devices, would have suggested to one of ordinary skill in the art that the materials and subsequent porosity of Liu’s first and second interlayer insulating layers may be adjusted as a matter of routine optimization of a result-effective variable. Adjusting material and subsequent porosity to achieve predictable results, such as Liu’s express teachings of propagation delay and crosstalk minimization, would have been well within the ordinary skill in the art. No evidence of criticality or unexpected results for the claimed porosity relationship is apparent. Accordingly, the claimed limitation represents an obvious optimization of a result-effective variable.
Furthermore, Jang is evidence showing that one of ordinary skill in the art would appreciate that a porosity of a first interlayer insulating layer being greater than a porosity of a second interlayer insulating layer would be equivalent to an unexplicit, undisclosed porosity relationship between first and second insulating layers, and that such differences would result in no unexpected changes in the performance of the device of Liu. That is, the interlayer insulating layers of both Liu and Jang would yield the predictable result of providing suitable isolating layers capable of insulating conductive features from one another and supporting various electrical and non-electrical structures in a semiconductor device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a first interlayer insolating layer having a porosity greater than a porosity of a second interlayer insulating layer, as taught by Jang, an unexplicit, undisclosed porosity relationship between first and second insulating layers, as taught by Liu, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable isolating layers capable of insulating conductive features from one another and supporting various electrical and non-electrical structures in a semiconductor device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lee I in view of Jang.
Regarding claim 2, Lee I shows most aspects of the instant invention (see paragraph 15 above). Furthermore, Lee I teaches that the dielectric materials selected for Liu’s interlayer insulating layers may either be porous or another appropriate material (see, e.g., pars.0028-0029). Accordingly, by selection of a porous dielectric material for Lee I’s first interlayer insulating layer and another insulating material for Lee I’s second interlayer insulating layer, Lee I implicitly teaches that a porosity of Lee I’s first interlayer insulating layer 130 may be greater than a porosity of Lee I’s second interlayer insulating layer 150.
Lee I, however, fails to explicitly specify that a porosity of the first interlayer insulating layer is greater than a porosity of the second interlayer insulating layer. Jang, in the same field of endeavor, teaches a device comprising interlayer insulating layers formed from materials similar to Lee I’s interlayer insulating layers, wherein Jang further teaches that selection of certain materials for first and second interlayer insulating layers may result in a first interlayer insulating layer having a porosity greater than a porosity of a second interlayer insulating layer, wherein Jang additionally teaches that such a porosity difference is viable and functional in semiconductor devices (see, e.g., Jang: par.0039/ll.10-19).
Jang is evidence showing that one of ordinary skill in the art would appreciate that a porosity of a first interlayer insulating layer being greater than a porosity of a second interlayer insulating layer would be equivalent to an unexplicit, undisclosed porosity relationship between first and second insulating layers, and that such differences would result in no unexpected changes in the performance of the device of Lee I. That is, the interlayer insulating layers of both Lee I and Jang would yield the predictable result of providing suitable isolating layers capable of insulating conductive features from one another and supporting various electrical and non-electrical structures in a semiconductor device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a first interlayer insolating layer having a porosity greater than a porosity of a second interlayer insulating layer, as taught by Jang, an unexplicit, undisclosed porosity relationship between first and second insulating layers, as taught by Lee I, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable isolating layers capable of insulating conductive features from one another and supporting various electrical and non-electrical structures in a semiconductor device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Liu/Lee I in view of Jang.
Regarding claim 2, Liu/Lee I shows most aspects of the instant invention (see paragraphs 25-28 above). Furthermore, Liu teaches that the dielectric materials selected for Liu’s interlayer insulating layers may either be porous or another appropriate material, wherein Liu further teaches that the material of such dielectric layers may be selected to minimize propagation delays and crosstalk between nearby conductive features (see, e.g., cols.7/ll.13-16 and 10/ll.34-37). Accordingly, by selection of a porous dielectric material for Liu’s first interlayer insulating layer and another insulating material for Liu’s second interlayer insulating layer, Liu implicitly teaches that a porosity of Liu’s first interlayer insulating layer 190 may be greater than a porosity of Liu’s second interlayer insulating layer 260.
Liu, however, fails to explicitly specify that a porosity of the first interlayer insulating layer 190 is greater than a porosity of the second interlayer insulating layer 260. Jang, in the same field of endeavor, teaches a device comprising interlayer insulating layers formed from materials similar to Liu’s interlayer insulating layers, wherein Jang further teaches that selection of certain materials for first and second interlayer insulating layers may result in a first interlayer insulating layer having a porosity greater than a porosity of a second interlayer insulating layer, wherein Jang additionally teaches that such a porosity difference is viable and functional in semiconductor devices (see, e.g., Jang: par.0039/ll.10-19).
Here, Liu’s express teaching that the material of dielectric layers may be selected to minimize propagation delays and crosstalk between nearby conductive structures taken together with its disclosure that porous materials are appropriate for use in Liu’s interlayer insulating layers and Jang’s disclosure that having a first interlayer insolating layer with a porosity greater than a porosity of a second interlayer insulating layer is viable for semiconductor devices, would have suggested to one of ordinary skill in the art that the materials and subsequent porosity of Liu’s first and second interlayer insulating layers may be adjusted as a matter of routine optimization of a result-effective variable. Adjusting material and subsequent porosity to achieve predictable results, such as Liu’s express teachings of propagation delay and crosstalk minimization, would have been well within the ordinary skill in the art. No evidence of criticality or unexpected results for the claimed porosity relationship is apparent. Accordingly, the claimed limitation represents an obvious optimization of a result-effective variable.
Furthermore, Jang is evidence showing that one of ordinary skill in the art would appreciate that a porosity of a first interlayer insulating layer being greater than a porosity of a second interlayer insulating layer would be equivalent to an unexplicit, undisclosed porosity relationship between first and second insulating layers, and that such differences would result in no unexpected changes in the performance of the device of Liu. That is, the interlayer insulating layers of both Liu and Jang would yield the predictable result of providing suitable isolating layers capable of insulating conductive features from one another and supporting various electrical and non-electrical structures in a semiconductor device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a first interlayer insolating layer having a porosity greater than a porosity of a second interlayer insulating layer, as taught by Jang, an unexplicit, undisclosed porosity relationship between first and second insulating layers, as taught by Liu, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable isolating layers capable of insulating conductive features from one another and supporting various electrical and non-electrical structures in a semiconductor device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee II in view of Jang.
Regarding claim 9, Lee II shows most aspects of the instant invention (see paragraph 21 above). Lee II, however, fails to explicitly specify any porosity of Lee II’s interlayer insulating layers, including if a porosity of the first interlayer insulating layer 420 is greater than a porosity of the second interlayer insulating layer 410. Jang, in the same field of endeavor, teaches a device comprising interlayer insulating layers formed from materials similar to Lee II’s interlayer insulating layers (see, e.g., Lee II: par.0049). Jang teaches that selection of certain materials for first and second interlayer insulating layers may result in a first interlayer insulating layer having a porosity greater than a porosity of a second interlayer insulating layer, wherein Jang additionally teaches that such a porosity difference is viable and functional in semiconductor devices (see, e.g., Jang: par.0039/ll.10-19).
Jang is evidence showing that one of ordinary skill in the art would appreciate that a porosity of a first interlayer insulating layer being greater than a porosity of a second interlayer insulating layer would be equivalent to an unexplicit, undisclosed porosity relationship between first and second insulating layers, and that such differences would result in no unexpected changes in the performance of the device of Lee II. That is, the interlayer insulating layers of both Lee II and Jang would yield the predictable result of providing suitable isolating layers capable of insulating conductive features from one another and supporting various electrical and non-electrical structures in a semiconductor device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a first interlayer insolating layer having a porosity greater than a porosity of a second interlayer insulating layer, as taught by Jang, an unexplicit, undisclosed porosity relationship between first and second insulating layers, as taught by Lee II, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable isolating layers capable of insulating conductive features from one another and supporting various electrical and non-electrical structures in a semiconductor device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee II/Liu/Lee I in view of Jang.
Regarding claim 9, Lee II/Liu/Lee I shows most aspects of the instant invention (see paragraphs 31-36 above). Furthermore, Liu teaches that the dielectric materials selected for interlayer insulating layers may either be porous or another appropriate material, wherein Liu further teaches that the material of such dielectric layers may be selected to minimize propagation delays and crosstalk between nearby conductive features (see, e.g., cols.7/ll.13-16 and 10/ll.34-37). Accordingly, by selection of a porous dielectric material for a first interlayer insulating layer and another insulating material for a second interlayer insulating layer, Liu implicitly teaches that a porosity of a first interlayer insulating layer may be greater than a porosity of a second interlayer insulating layer.
Lee II/Liu/Lee I, however, fails to explicitly specify that a porosity of the first interlayer insulating layer is greater than a porosity of the second interlayer insulating layer. Jang, in the same field of endeavor, teaches a device comprising interlayer insulating layers formed from materials similar to Lee II’s interlayer insulating layers (see, e.g., Lee II: par.0049). Jang further teaches that selection of certain materials for first and second interlayer insulating layers may result in a first interlayer insulating layer having a porosity greater than a porosity of a second interlayer insulating layer, wherein Jang additionally teaches that such a porosity difference is viable and functional in semiconductor devices (see, e.g., Jang: par.0039/ll.10-19).
Here, Liu’s express teaching that the material of dielectric layers may be selected to minimize propagation delays and crosstalk between nearby conductive structures taken together with its disclosure that porous materials are appropriate for use in interlayer insulating layers and Jang’s disclosure that having a first interlayer insolating layer with a porosity greater than a porosity of a second interlayer insulating layer is viable for semiconductor devices, would have suggested to one of ordinary skill in the art that the materials and subsequent porosity of Lee II/Liu/Lee I’s first and second interlayer insulating layers may be adjusted as a matter of routine optimization of a result-effective variable. Adjusting material and subsequent porosity to achieve predictable results, such as Liu’s express teachings of propagation delay and crosstalk minimization, would have been well within the ordinary skill in the art. No evidence of criticality or unexpected results for the claimed porosity relationship is apparent. Accordingly, the claimed limitation represents an obvious optimization of a result-effective variable.
Furthermore, Jang is evidence showing that one of ordinary skill in the art would appreciate that a porosity of a first interlayer insulating layer being greater than a porosity of a second interlayer insulating layer would be equivalent to an unexplicit, undisclosed porosity relationship between first and second insulating layers, and that such differences would result in no unexpected changes in the performance of the device of Lee II/Liu/Lee I. That is, the interlayer insulating layers of both Lee II/Liu/Lee I and Jang would yield the predictable result of providing suitable isolating layers capable of insulating conductive features from one another and supporting various electrical and non-electrical structures in a semiconductor device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a first interlayer insolating layer having a porosity greater than a porosity of a second interlayer insulating layer, as taught by Jang, an unexplicit, undisclosed porosity relationship between first and second insulating layers, as taught by Lee II/Liu/Lee I, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable isolating layers capable of insulating conductive features from one another and supporting various electrical and non-electrical structures in a semiconductor device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lee II/Liu/Lee I/Mouli in view of Jang.
Regarding claim 18, Lee II/Liu/Lee I/Mouli shows most aspects of the instant invention (see paragraphs 42-51 above). Furthermore, Liu teaches that the dielectric materials selected for interlayer insulating layers may either be porous or another appropriate material, wherein Liu further teaches that the material of such dielectric layers may be selected to minimize propagation delays and crosstalk between nearby conductive features (see, e.g., cols.7/ll.13-16 and 10/ll.34-37). Accordingly, by selection of a porous dielectric material for a first interlayer insulating layer and another insulating material for a second interlayer insulating layer, Liu implicitly teaches that a porosity of a first interlayer insulating layer may be greater than a porosity of a second interlayer insulating layer.
Lee II/Liu/Lee I/Mouli, however, fails to explicitly specify that a porosity of the first interlayer insulating layer is greater than a porosity of the second interlayer insulating layer. Jang, in the same field of endeavor, teaches a device comprising interlayer insulating layers formed from materials similar to Lee II’s interlayer insulating layers (see, e.g., Lee II: par.0049). Jang further teaches that selection of certain materials for first and second interlayer insulating layers may result in a first interlayer insulating layer having a porosity greater than a porosity of a second interlayer insulating layer, wherein Jang additionally teaches that such a porosity difference is viable and functional in semiconductor devices (see, e.g., Jang: par.0039/ll.10-19).
Here, Liu’s express teaching that the material of dielectric layers may be selected to minimize propagation delays and crosstalk between nearby conductive structures taken together with its disclosure that porous materials are appropriate for use in interlayer insulating layers and Jang’s disclosure that having a first interlayer insolating layer with a porosity greater than a porosity of a second interlayer insulating layer is viable for semiconductor devices, would have suggested to one of ordinary skill in the art that the materials and subsequent porosity of Lee II/Liu/Lee I/Mouli’s first and second interlayer insulating layers may be adjusted as a matter of routine optimization of a result-effective variable. Adjusting material and subsequent porosity to achieve predictable results, such as Liu’s express teachings of propagation delay and crosstalk minimization, would have been well within the ordinary skill in the art. No evidence of criticality or unexpected results for the claimed porosity relationship is apparent. Accordingly, the claimed limitation represents an obvious optimization of a result-effective variable.
Furthermore, Jang is evidence showing that one of ordinary skill in the art would appreciate that a porosity of a first interlayer insulating layer being greater than a porosity of a second interlayer insulating layer would be equivalent to an unexplicit, undisclosed porosity relationship between first and second insulating layers, and that such differences would result in no unexpected changes in the performance of the device of Lee II/Liu/Lee I/Mouli. That is, the interlayer insulating layers of both Lee II/Liu/Lee I/Mouli and Jang would yield the predictable result of providing suitable isolating layers capable of insulating conductive features from one another and supporting various electrical and non-electrical structures in a semiconductor device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a first interlayer insolating layer having a porosity greater than a porosity of a second interlayer insulating layer, as taught by Jang, an unexplicit, undisclosed porosity relationship between first and second insulating layers, as taught by Lee II/Liu/Lee I/Mouli, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable isolating layers capable of insulating conductive features from one another and supporting various electrical and non-electrical structures in a semiconductor device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Conclusion
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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