DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 3, 5, 6, and 8 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US Patent Application Publication No. 2009/0085172 to Horigome et al.
Regarding claim 1, Horigome et al. teach a semiconductor device (Fig. 3B, for example), comprising:
a first dielectric (10) comprising a first side and a second side;
a first conductive tier in the first dielectric and comprising a first conductive path integral with a first conductive via (11), wherein the first conductive path and the first conductive via extend between the first side and the second side of the first dielectric;
a second dielectric (20) comprising a first side and a second side; and
a first barrier (13) covering the first conductive tier and covering the first dielectric, wherein the first barrier is between the second side of the first dielectric and the first side of the second dielectric; wherein:
the first conductive tier comprises a trench barrier (12) coupled with the first dielectric.
Regarding claim 2, Horigome et al. teach a semiconductor device, wherein: the first dielectric and the second dielectric comprise an organic dielectric material (¶¶[0050], [0056]); and the first barrier comprises an inorganic dielectric material (¶ [0051]).
Regarding claim 3, Horigome et al. teach a semiconductor device, wherein: the first barrier is configured to restrict migration of ions of the first conductive tier into the second dielectric since that is an inherent property of a barrier film, such as SiCN.
Regarding claim 5, Horigome et al. teach a semiconductor device, wherein: the first dielectric comprises a single layer of dielectric material; and the first conductive path and the first conductive via are in the single layer of dielectric material (See Fig. 3B).
Regarding claim 6, Horigome et al. teach a semiconductor device, comprising: a second conductive tier in the second dielectric and comprising a second conductive path integral with a second conductive via, wherein the second conductive path and the second conductive via extend between the first side and the second side of the second dielectric; wherein the second conductive tier is coupled with the first conductive tier through an opening in the first barrier. See Fig. 3B.
Regarding claim 8, Horigome et al. teach a semiconductor device, wherein: the first barrier fully covers the first dielectric and partially covers the first conductive tier. See Fig. 3B
Claims 13, 14, and 17 – 20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US Patent No. 6,713,381 to Barr et al .
Regarding claim 13, Barr et al. teach a semiconductor device, comprising:
a first dielectric (110) comprising a first side and a second side;
a first conductive tier comprising a first conductive path integral with a first conductive via (114), wherein the first conductive path and the first conductive via extend between the first side and the second side of the first dielectric;
a second dielectric (124) comprising a first side and a second side;
a second conductive tier comprising a second conductive path integral with a second conductive via (128), wherein the second conductive path and the second conductive via extend between the first side and the second side of the second dielectric;
a first barrier (122) between the second side of the first conductive tier and the first side of the second dielectric;
a first electronic component (1230) coupled with the second conductive tier; and
a first encapsulant (92, 1001) coupled with the second dielectric and covering a lateral side of the first electronic component; wherein
the second conductive tier is coupled with the first conductive tier through an opening in the first barrier.
Regarding claim 14, Barr et al. teach a semiconductor device comprising: a base substrate (100) comprising a base dielectric structure (102) and a base conductive structure (104, 108); wherein the base conductive structure is coupled with the first conductive tier through a substrate inward terminal.
Regarding claim 17, Barr et al. teach a method to manufacture a semiconductor device, comprising:
providing a substrate (100) comprising a first side and a second side;
providing a first dielectric (110) comprising a first side and a second side, wherein the first side of the first dielectric is coupled with the second side of the substrate;
providing a first conductive tier in the first dielectric and comprising a first conductive path integral with a first conductive via (114), wherein the first conductive path and the first conductive via extend between the first side of the first dielectric and the second side of the first dielectric;
providing a first barrier (122) covering the first conductive tier and covering the second side of the first dielectric; and providing a second dielectric comprising a first side and a second side, wherein the first side of the second dielectric is coupled with the second side of the first dielectric;
wherein the first barrier is between the second side of the first dielectric and the first side of the second dielectric.
Regarding claim 18, Barr et al. teach a method, comprising providing the first conductive tier comprises:
providing a trench barrier (112) into the first dielectric; and
providing the first conductive via and the first conductive path over the trench barrier;
wherein the trench barrier is between the first dielectric and each of the first conductive path and the first conductive via.
Regarding claim 19, Barr et al. teach a method, comprising: providing a second conductive tier in the second dielectric and comprising a second conductive path (128) integral with a second conductive via wherein the second conductive path and the second conductive via extend between the first side of the second dielectric and the second side of the second dielectric; wherein the second conductive via is coupled with the first conductive tier through an opening in the first barrier.
Regarding claim 20, Barr et al. teach a method, wherein: the first dielectric comprises a single layer of dielectric material; and
the first conductive path and the first conductive via are in the single layer of dielectric material. See Fig. 12.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Horigome et al.
Regarding claim 4, Horigome et al. teach a trench barrier that comprises tantalum, tantalum nitride, and the like. (¶ [0050]). Horigome et al. do not explicitly teach a trench barrier comprising titanium. Tantalum and titanium are both refractory metals, so one of ordinary skill would consider titanium to be a like material. Accordingly, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to select titanium since it is a metal suggested by Horigome et al. Moreover, it is a known barrier metal that is well suited for the intended use.
Allowable Subject Matter
Claims 7, 9 – 12, 15, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication No. 2023/0307294 to Ma teaches a first and second dielectric layer, a conductive tier in the first dielectric layer, with a barrier layer between the first and second dielectric layers. Ma does not teach a trench barrier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS W OWENS whose telephone number is (571)272-1662. The examiner can normally be reached M-F 5:30-1:30.
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DOUGLAS W. OWENS, Esq.
Primary Patent Examiner
Art Unit 2897
/DOUGLAS W OWENS/Primary Patent Examiner, Art Unit 2897