DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I, Species 1 (claims 1-8 and 11-17) in the reply filed on January 5, 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The references cited within the IDS document (dated August 8, 2023) have been considered.
Specification (Title)
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 8, 11-13, 16, and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu et al. (US 2023/0108041 A1, hereinafter referred to as ‘Yu’).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
As to claim 1, Yu teaches a semiconductor device (see figures 1-3 and 7) comprising:
an active pattern comprising:
a lower pattern (BP) extending in a first direction; and
a plurality of sheet patterns (NS) spaced apart from the lower pattern in a second direction perpendicular to an upper surface of the lower pattern, each of the plurality of sheet patterns comprising an upper surface and a lower surface opposite to each other in the second direction;
a gate structure (GS) provided on the lower pattern, and comprising a gate electrode (120) and a gate insulating film (130), wherein the gate electrode and the gate insulating film are around the plurality of sheet patterns; and
a source/drain pattern (150) provided on at least one side of the gate structure,
wherein the gate structure comprises a plurality of inter gate structures provided between the lower pattern and the plurality of sheet patterns and between adjacent sheet patterns of the plurality of sheet patterns,
wherein the plurality of inter gate structures contact the source/drain pattern,
wherein the gate insulating film comprises an interfacial insulating film (131),
wherein the interfacial insulating film comprises:
a first vertical portion (131_V1) extending along the source/drain pattern; and
a horizontal portion (131_H) extending along the upper surface of each of the plurality of sheet patterns, and along the lower surface of each of the plurality of sheet patterns,
wherein a first dimension in a third direction of the first vertical portion of the interfacial insulating film is greater than a second dimension in the second direction of the horizontal portion of the interfacial insulating film (shown in fig. 7),
wherein the first vertical portion comprises:
a first area (131_V11) in contact with the source/drain pattern; and
a second area (131_V12) provided between the first area and the gate electrode,
wherein the interfacial insulating film comprises a first element other than silicon (see para. 0125-0126), and
wherein a first concentration of the first element in the first area is greater than a second concentration of the first element in the second area (see para. 0125-0126).
As to claim 5, Yu teaches the first element comprises one of carbon (C), boron (B), phosphorus (P) or nitrogen (N). See para. 0112.
As to claim 8, Yu teaches each of the plurality of inter gate structures further comprises a high dielectric constant insulating film (132) provided between the gate electrode and the interfacial insulating film. See also para. 0057.
As to claim 11, Yu teaches a semiconductor device (see figures 1-3 and 7) comprising:
an active pattern comprising:
a lower pattern (BP) extending in a first direction; and
a plurality of sheet patterns (NS) spaced apart from the lower pattern in a second direction perpendicular to an upper surface of the lower pattern;
a gate structure (GS) provided on the lower pattern and extending in a third direction perpendicular to the first direction, the gate structure comprising:
a gate electrode (120) around the plurality of sheet patterns; and
a gate insulating film (130) provided on the gate electrode,
a plurality of gate spacers (140) provided on the gate insulating film and spaced apart from each other in the third direction; and
a source/drain pattern (150) provided between the plurality of gate spacers and contacting each of the plurality of sheet patterns and the gate insulating film,
wherein the gate insulating film comprises an interfacial insulating film (131),
wherein the interfacial insulating film comprises:
a first area (131_V11) contacting the source/drain pattern; and
a second area (131_V12) provided between the first area and the gate electrode,
wherein the interfacial insulating film comprises a first element other than silicon (see para. 0125-0126), and
wherein a first concentration of the first element in the first area is different from a second concentration of the first element in the second area (see para. 0125-0126).
As to claim 12, Yu teaches the first concentration of the first element in the first area is greater than the second concentration of the first element in the second area. See para. 0125-0126.
As to claim 13, Yu teaches the interfacial insulating film overlaps the plurality of gate spacers (140) in the third direction. See fig. 10
As to claim 16, Yu teaches the first element comprises one of carbon (C), boron (B), phosphorus (P), or nitrogen (N). See para. 0125-0126.
As to claim 17, Yu teaches the gate insulating film further comprises a high dielectric constant insulating film (132) provided between the gate electrode and the interfacial insulating film. See also para. 0070.
Allowable Subject Matter
Claims 2-4, 6, 7, 14, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record does not teach or suggest wherein the source/drain pattern comprises a third area contacting the interfacial insulating film,
wherein the third area comprises the first element, and
wherein a third concentration of the first element in the third area is different from the first concentration of the first element in the first area, as recited in claim 2.
The prior art of record does not teach or suggest wherein the second concentration of the first element in the second area is equal to a fourth concentration of the first element in the horizontal portion, as recited in claim 4.
The prior art of record does not teach or suggest wherein each of the plurality of sheet patterns comprises a sidewall connecting the upper surface of each of the plurality of sheet patterns to the lower surface of each of the plurality of sheet patterns,
wherein the interfacial insulating film comprises a second vertical portion extending along the sidewall of the respective one of the plurality of sheet patterns, and
wherein a third concentration of the first element in the first vertical portion is greater than a fourth concentration of the first element in the second vertical portion, as recited in claim 6.
The prior art of record does not teach or suggest wherein each sheet pattern of the plurality of sheet patterns comprises a sidewall connecting the upper surface of the sheet pattern to the lower surface of the sheet pattern,
wherein the interfacial insulating film comprises a second vertical portion extending along the sidewall of the sheet pattern, and
wherein the second dimension in the second direction of the horizontal portion is equal to a third dimension in the first direction of the second vertical portion, as recited in claim 7.
The prior art of record does not teach or suggest wherein the source/drain pattern comprises:
a first liner film contacting the interfacial insulating film and the plurality of sheet patterns;
a second liner film provided on the first liner film; and
a filling film provided on the second liner film, as recited in claim 14.
Claims 3 and 15 are also objected to as being dependent upon objected claims.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim (telephone: 571-272-8458). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only.
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/SCOTT B GEYER/ Primary Examiner, Art Unit 2812
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