Prosecution Insights
Last updated: October 02, 2026

Examiner: GEYER, SCOTT B

Tech Center 2800 • Art Units: 2800 2812

This examiner grants 94% of resolved cases

Analysis

Scott B. Geyer, working in Tech Center 2800 and Art Unit 2800, demonstrates an allowance rate of 94.2% over 727 resolved cases. The median days to allowance is 693, which represents the typical timeline for successful applications. This 693-day figure and the 94.2% allowance rate indicate a very efficient path to patent issuance. Practitioners should use these metrics to plan their prosecution strategy in this art unit.

The interview lift is 4.2%, a figure that is small relative to the 94.2% allowance rate. With such a high baseline for success, interviews may only be necessary for the most complex cases among the 727 resolved cases. The 4.2% lift suggests that written prosecution is often sufficient to reach an allowance. The 693-day median pendency confirms that this examiner provides a streamlined route to grant, and the 94.2% rate reflects a high probability of success.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

94.2%
Allow Rate
+26.2% vs TC avg
736
Total Applications
+4.2%
Interview Lift
693
Avg Prosecution Days
Based on 727 resolved cases, 2023–2026

Rejection Statute Breakdown

1.6%
§101 Eligibility
41.5%
§102 Novelty
21.0%
§103 Obviousness
24.2%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18811512 PASSIVE COMPONENT EMBEDDED SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME Non-Final OA SAMSUNG ELECTRONICS CO., LTD.
18662107 CAPACITOR, SEMICONDUCTOR DEVICE COMPRISING THE CAPACITOR, AND METHOD OF FABRICATING THE CAPACITOR Non-Final OA Samsung Electronics Co., Ltd.
18422471 SEMICONDUCTOR DEVICE Non-Final OA Samsung Electronics Co., Ltd.
18762478 PACKAGE FORMATION METHODS INCLUDING COUPLING A MOLDED ROUTING LAYER TO AN INTEGRATED ROUTING LAYER Non-Final OA Intel Corporation
18061181 INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG) Final Rejection Intel Corporation
18566939 SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC EQUIPMENT Non-Final OA SONY SEMICONDUCTOR SOLUTIONS CORPORATION
18409105 SELF ASSEMBLED MONOLAYER FORMED ON A QUANTUM DEVICE Non-Final OA International Business Machines Corporation
18788031 MULTI-GATE SEMICONDUCTOR DEVICE WITH INNER SPACER AND FABRICATION METHOD THEREOF Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18784645 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18644209 CHIP PACKAGE STRUCTURE WITH LID AND METHOD FOR FORMING THE SAME Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18783807 3DIC WITH GAP-FILL STRUCTURES AND THE METHOD OF MANUFACTURING THE SAME Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18594540 Solid Electrolytic Capacitor with Improved ESR and Leakage Non-Final OA KEMET Electronics Corporation
18747476 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Non-Final OA UNITED MICROELECTRONICS CORP.

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