DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on January 6, 2026 has been considered by the examiner.
Response to Amendment
The amendment filed December 18, 2025 has been entered. Claims 1-23 remain pending in this application. Claims 1, 9, and 17 have been amended, adding no new matter. Claims 21-23 have been added. No new matter has been added with new claims.
Applicant’s amendments to the Specification, Drawings, and Claims have overcome each and every objection and 112(b) rejection previously set forth in the Final Office Action mailed September 30, 2025.
Double Patenting
The terminal disclaimer filed on December 18, 2025 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of applications 18/232117, 18/230972, and 18/234094 has been reviewed and is accepted. The terminal disclaimer has been recorded.
In view of the accepted terminal disclaimer, the non-statutory double patenting rejection of Claims 1 and 9 is withdrawn.
Claim Objections
New Claims 22-23 objected to because of the following informalities:
New Claim 22: “Wherein the analog bitscan operation comprises further includes the control circuitry…” Additional words. In the interest of compact prosecution, the word ‘comprises’ will be ignored in this claim.
New Claim 23: “Wherein the analog bitscan operation comprises further includes the control circuitry…” Additional words. In the interest of compact prosecution, the word ‘comprises’ will be ignored in this claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 6-7, 9-11, and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. 11,475,959 to Yu-Chung Lien, et al. (hereafter Lien) in view of U.S. 11,568,943 to Xue Bai Pitner, et al. (hereafter Pitner).
Regarding Amended Independent Claim 1, Lien discloses a method of performing an erasing operation in a memory device, comprising the steps of:
preparing a memory block (Disclosing a memory block: Lien, col.3:23-25)
that includes a plurality of memory cells (Disclosing a number of memory cells: Lien, col.3:25-28)
that are arranged in a plurality of word lines (Disclosing memory cells arranged in word lines: Lien, col.3:33-35),
the plurality of word lines including a selected group of word lines to be erased (Disclosing block enable line 317 connected to wordlines, enabling an erase operation within that block: Lien, col.13:21-34; See Also Lien Figure 7);
erasing the memory cells (Disclosing an erase operation: Lien, col.13:32-34)
in at least one erase loop (Suggesting performing an erase operation in iterative processes: Lien, col.18:21-23),
the at least one erase loop includes
an analog bitscan operation (Disclosing a verify operation producing a specified number rather than a simple pass/fail: Lien, col.21:26-29);
determining an output of the analog bitscan operation (Disclosing comparing the output of the verification operation: Lien, col.21:37-38),
the output being one of at least three options (Disclosing the verification operation falling into three categories, for example the count compared to a BSPF <= 24, count between BSPF 24 and 72, and BSPF greater than 72: Lien, col.21:37-54).
Lien does not disclose erasing the memory cells of the selected group of word lines where the at least one erase loop includes an erase pulse and an erase-verify operation and subsequently setting at least one erase parameter based on the output of the analog bitscan operation.
Pitner, however, discloses a method of programming a memory device wherein
erasing the memory cells
of the selected group of word lines (Disclosing performing an erase operation on a block: Pitner, col.8:32-33; Wherein the block includes a set of NAND strings in communication with a common set of word lines: Pitner, col.8:19-20)
the at least one erase loop (Disclosing a trial erase loop: Pitner, col.14:40-41) including
an erase pulse (Disclosing an erase operation starting with an initial erase pulse: Pitner, col.14:22), and an erase-verify operation (Erase operation including an erase verification step: Pitner, col.15:57-58),
the erase-verify operation (Disclosing a single erase-verify operation: Pitner, Figure 8, Step 804) including the application of only a single erase-verify reference voltage to the word lines of the selected group of word lines (Teaching the second erase operation does not include an erase verification step, therefore limiting the erase loop to a single erase verification step and, by definition, only a single erase verification voltage: Pitner, col.16:65-66), and
an analog bitscan operation that follows the single erase-verify operation (Performing a determination step following the first erase-verify operation: Pitner, Figure 8, Steps 806 and 808);
setting at least one erase parameter (Disclosing adjusting the erase voltage for a second erase loop: Pitner, col.16:6-7)
based on the output of the analog bitscan operation (Disclosing the change in erase voltage is based on the relative success of a trial erase loop: Pitner, col.16:6-7).
Pitner discloses estimating the optimal erase value allows the erase operation to succeed reliably despite variations in erase pulse characteristics (Teaching applying a trial pulse to memory cells during an erase operation to identify ideal erase pulse characteristics: Pitner, col.14:40-53; Further teaching the natural variation of required erase pulse characteristics over time: Pitner, col.14:53-56).
Therefore, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the invention to combine the optimal erase pulse determination method of Pitner with the analog verification method of Lien. The inventions are known variants of program/erase cycle verification operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2, Pitner discloses the method as set forth in claim 1, wherein the step of setting the at least one erase parameter based on the output of the analog bitscan operation includes:
in response to the output of the analog bitscan operation (Disclosing using the bit scan to estimate the upper tail Vt: Pitner Figure 9B) being a first output option ,
increasing a voltage of the erase pulse by a first step size (Disclosing deriving a second erase voltage based on the identified upper tail Vt: Pitner, col.16:6-17); and
in response to the output of the analog bitscan operation being a second output option (The upper tail Vt, determined from the results of the bit scan, may be any voltage between the erase Vt and the upper programmed Vt. If the output of a second bit scan operation differs from the first output, that will necessarily result in a different upper tail Vt determination),
increasing the voltage of the erase pulse by a second step size that is different than the first step size (The voltage between the trial erase and second erase pulse is derived from the output of the bit scan and upper tail Vt. Where the bit scan results differ, the voltage step will therefore necessarily differ.; See Also Disclosing the determination of the second erase voltage comes from a table based on the upper tail Vt: Pitner, col.16:55-59).
Regarding Claim 3, Lien discloses the method as set forth in claim 2, wherein the step of setting the at least one erase parameter based on the output of the analog bitscan operation further includes:
in response to the output of the analog bitscan operation being a third output option (Disclosing the count of cells failing a BSPF step being below a set threshold: Lien, col.21:50),
ending the erasing operation (Disclosing the operation being complete under this final verification output and setting an inhibit voltage to prevent further modification: Lien, col.51-54).
Regarding Claim 6, Pitner discloses the method as set forth in claim 1, wherein the step of setting the at least one erase parameter based on the output of the analog bitscan operation includes:
in response to the output of the analog bitscan operation (Disclosing using the bit scan to estimate the upper tail Vt: Pitner Figure 9B) being a first output option,
increasing a voltage of the erase pulse by a first step size (Disclosing deriving a second erase voltage based on the identified upper tail Vt: Pitner, col.16:6-17); and
in response to the output of the analog bitscan operation being a second output option,
increasing the voltage of the erase pulse by a second step size that is different than the first step size (The voltage between the trial erase and second erase pulse is derived from the output of the bit scan and upper tail Vt. Where the bit scan results differ, the voltage step will therefore necessarily differ.; See Also Disclosing the determination of the second erase voltage comes from a table based on the upper tail Vt: Pitner, col.16:55-59) and
applying an additional erase pulse to the selected group of word lines (Disclosing applying an additional erase pulse at the second derived erase voltage: Pitner, col.16:60-61).
Regarding Claim 7, Lien discloses the method as set forth in claim 6, wherein the step of setting the at least one erase parameter based on the output of the analog bitscan operation further includes:
in response to the output of the analog bitscan operation being a third output option (Disclosing the count of cells failing a BSPF step being below a set threshold: Lien, col.21:50),
ending the erasing operation (Disclosing the operation being complete under this final verification output and setting an inhibit voltage to prevent further modification: Lien, col.51-54).
Regarding Amended Independent Claim 9, Lien discloses a memory device, comprising:
a memory block (Disclosing a memory block: Lien, col.3:23-25)
that includes a plurality of memory cells (Disclosing a number of memory cells: Lien, col.3:25-28)
that are arranged in a plurality of word lines (Disclosing memory cells arranged in word lines: Lien, col.3:33-35),
the plurality of word lines including a selected group of word lines to be erased in an erasing operation (Disclosing block enable line 317 connected to wordlines, enabling an erase operation within that block: Lien, col.13:21-34; See Also Lien Figure 7);
circuitry (Disclosing circuitry: Lien Figure 1A) that is configured to
erase the memory cells (Disclosing an erase operation: Lien, col.13:32-34)
in at least one erase loop (Suggesting performing an erase operation in iterative processes: Lien, col.18:21-23),
the at least one erase loop includes
an analog bitscan operation (Disclosing a verify operation producing a specified number rather than a simple pass/fail: Lien, col.21:26-29);
the circuitry being configured to:
determine an output of the analog bitscan operation (Disclosing comparing the output of the verification operation: Lien, col.21:37-38),
the output being one of at least three options (Disclosing the verification operation falling into three categories, for example the count compared to a BSPF <= 24, count between BSPF 24 and 72, and BSPF greater than 72: Lien, col.21:37-54).
Lien does not disclose the circuitry being configured to erase the memory cells of the selected word line where the at least one erase loop includes an erase pulse and with an erase-verify operation and subsequently setting at least one erase parameter based on the output of the analog bitscan operation.
Pitner, however, discloses a memory device with circuitry configured to:
erase the memory cells
of the selected group of word lines (Disclosing performing an erase operation on a block: Pitner, col.8:32-33; Wherein the block includes a set of NAND strings in communication with a common set of word lines: Pitner, col.8:19-20)
the at least one erase loop (Disclosing a trial erase loop: Pitner, col.14:40-41) including
an erase pulse (Disclosing an erase operation starting with an initial erase pulse: Pitner, col.14:22), and an erase-verify operation (Erase operation including an erase verification step: Pitner, col.15:57-58),
the erase-verify operation (Disclosing a single erase-verify operation: Pitner, Figure 8, Step 804) including the application of only a single erase-verify reference voltage to the word lines of the selected group of word lines (Teaching the second erase operation does not include an erase verification step, therefore limiting the erase loop to a single erase verification step and, by definition, only a single erase verification voltage: Pitner, col.16:65-66), and
an analog bitscan operation that follows the single erase-verify operation (Performing a determination step following the first erase-verify operation: Pitner, Figure 8, Steps 806 and 808); and
set at least one erase parameter (Disclosing adjusting the erase voltage for a second erase loop: Pitner, col.16:6-7)
based on the output of the analog bitscan operation (Disclosing the change in erase voltage is based on the relative success of a trial erase loop: Pitner, col.16:6-7).
Pitner discloses estimating the optimal erase value allows the erase operation to succeed reliably despite variations in erase pulse characteristics (Teaching applying a trial pulse to memory cells during an erase operation to identify ideal erase pulse characteristics: Pitner, col.14:40-53; Further teaching the natural variation of required erase pulse characteristics over time: Pitner, col.14:53-56).
Therefore, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the invention to combine the optimal erase pulse determination method of Pitner with the analog verification method of Lien. The inventions are known variants of program/erase cycle verification operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 10, Pitner discloses the memory device as set forth in claim 9, wherein the circuitry is further configured to:
in response to the output of the analog bitscan operation (Disclosing using the bit scan to estimate the upper tail Vt: Pitner Figure 9B) being a first output option,
increase a voltage of the erase pulse by a first step size (Disclosing deriving a second erase voltage based on the identified upper tail Vt: Pitner, col.16:6-17); and
in response to the output of the analog bitscan operation being a second output option (The upper tail Vt, determined from the results of the bit scan, may be any voltage between the erase Vt and the upper programmed Vt. If the output of a second bit scan operation differs from the first output, that will necessarily result in a different upper tail Vt determination),
increase the voltage of the erase pulse by a second step size that is different than the first step size (The voltage between the trial erase and second erase pulse is derived from the output of the bit scan and upper tail Vt. Where the bit scan results differ, the voltage step will therefore necessarily differ.; See Also Disclosing the determination of the second erase voltage comes from a table based on the upper tail Vt: Pitner, col.16:55-59).
Regarding Claim 11, Lien discloses the memory device as set forth in claim 10, wherein the circuitry is further configured to:
in response to the output of the analog bitscan operation being a third output option (Disclosing the count of cells failing a BSPF step being below a set threshold: Lien, col.21:50),
end the erasing operation (Disclosing the operation being complete under this final verification output and setting an inhibit voltage to prevent further modification: Lien, col.51-54).
Regarding Claim 14, Pitner discloses the memory device as set forth in claim 9, wherein the circuitry is further configured to:
in response to the output of the analog bitscan operation (Disclosing using the bit scan to estimate the upper tail Vt: Pitner Figure 9B) being a first output option,
increase a voltage of the erase pulse by a first step size (Disclosing deriving a second erase voltage based on the identified upper tail Vt: Pitner, col.16:6-17); and
in response to the output of the analog bitscan operation being a second output option,
increase the voltage of the erase pulse by a second step size that is different than the first step size (The voltage between the trial erase and second erase pulse is derived from the output of the bit scan and upper tail Vt. Where the bit scan results differ, the voltage step will therefore necessarily differ.; See Also Disclosing the determination of the second erase voltage comes from a table based on the upper tail Vt: Pitner, col.16:55-59) and
apply an additional erase pulse to the selected group of word lines (Disclosing applying an additional erase pulse at the second derived erase voltage: Pitner, col.16:60-61).
Regarding Claim 15, Lien discloses the memory device as set forth in claim 14, wherein the circuitry is further configured to:
in response to the output of the analog bitscan operation being a third output option (Disclosing the count of cells failing a BSPF step being below a set threshold: Lien, col.21:50),
end the erasing operation (Disclosing the operation being complete under this final verification output and setting an inhibit voltage to prevent further modification: Lien, col.51-54).
Claim(s) 4, 8, 12, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. 11,475,959 to Yu-Chung Lien, et al. (hereafter Lien) in view of U.S. 11,568,943 to Xue Bai Pitner, et al. (hereafter Pitner) and further in view of U.S. 10,366,770 to Yasuhiko Kurosawa, et al. (hereafter Kurosawa).
Regarding Claim 4, Lien and Pitner disclose the method as set forth in claim 3 but do not explicitly teach the remaining limitations of Claim 4. Kurosawa, however, discloses an analog bitscan method for use during programming and erase cycles (Disclosing estimating the Bit Error Rate (BER) during a program erase cycle: Kurosawa, col.2:58-60) wherein:
the first output option is a strong fail;
the second output option is a weak fail or a weak pass; and
the third output option is a strong pass (Disclosing four tiers of errors, numbered 0-3. Does not apply the specific titles as above, but the tiers map to the same concepts, with 3 being a strong fail though 0 being a strong pass: Kurosawa, col.4:31-40; See Also, Kurosawa, Table 1 and Figure 4).
Kurosawa discloses estimating the BER during program/erase operations and beyond a simple indicator of success or not is less time consuming than the conventional approach and allows block optimization (Kurosawa, col.2:52-63).
Therefore, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the invention to combine the four-plus BER tiers of Kurosawa with the analog verification method of Lien. The inventions are known variants of program/erase cycle verification operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 8, Lien and Pitner disclose the method as set forth in Claim 6, but do not explicitly disclose the additional limitations of Claim 8. Kurosawa, however, discloses an analog bitscan method for use during programming and erase cycles (Disclosing estimating the Bit Error Rate (BER) during a program erase cycle: Kurosawa, col.2:58-60) wherein:
the first output option is strong fail,
the second output option is weak fail, and
the third output option is pass (Disclosing four tiers of errors, numbered 0-3. Does not apply the specific titles as above, but the tiers map to the same concepts, with 3 being a strong fail though 0 being a strong pass: Kurosawa, col.4:31-40; See Also, Kurosawa, Table 1 and Figure 4).
Kurosawa discloses estimating the BER during program/erase operations and beyond a simple indicator of success or not is less time consuming than the conventional approach and allows block optimization (Kurosawa, col.2:52-63).
Therefore, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the invention to combine the four-plus BER tiers of Kurosawa with the analog verification method of Lien. The inventions are known variants of program/erase cycle verification operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 12, Lien and Pitner disclose the memory device as set forth in claim 11, but do not explicitly teach the remaining limitations of Claim 12. Kurosawa, however, discloses a memory device using an analog bitscan method for use during programming and erase cycles (Disclosing estimating the Bit Error Rate (BER) during a program erase cycle: Kurosawa, col.2:58-60) wherein
the first output option is a strong fail;
the second output option is a weak fail or a weak pass; and
the third output option is a strong pass (Disclosing four tiers of errors, numbered 0-3. Does not apply the specific titles as above, but the tiers map to the same concepts, with 3 being a strong fail though 0 being a strong pass: Kurosawa, col.4:31-40; See Also, Kurosawa, Table 1 and Figure 4).
Kurosawa discloses estimating the BER during program/erase operations and beyond a simple indicator of success or not is less time consuming than the conventional approach and allows block optimization (Kurosawa, col.2:52-63).
Therefore, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the invention to combine the four-plus BER tiers of Kurosawa with the analog verification method of Lien. The inventions are known variants of program/erase cycle verification operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 16, Lien and Pitner disclose the memory device as set forth in claim 14, but do not explicitly teach disclose the additional limitations of Claim 14. Kurosawa, however, discloses a memory device using an analog bitscan as in Claim 14 wherein
the first output option is strong fail,
the second output option is weak fail, and
the third output option is pass (Disclosing four tiers of errors, numbered 0-3. Does not apply the specific titles as above, but the tiers map to the same concepts, with 3 being a strong fail though 0 being a strong pass: Kurosawa, col.4:31-40; See Also, Kurosawa, Table 1 and Figure 4).
Kurosawa discloses estimating the BER during program/erase operations and beyond a simple indicator of success or not is less time consuming than the conventional approach and allows block optimization (Kurosawa, col.2:52-63).
Therefore, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the invention to combine the four-plus BER tiers of Kurosawa with the analog verification method of Lien. The inventions are known variants of program/erase cycle verification operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Independent Claim 17, Lien discloses an apparatus, comprising:
a memory block (Disclosing a memory block: Lien, col.3:23-25)
that includes a plurality of memory cells (Disclosing a number of memory cells: Lien, col.3:25-28)
that are arranged in a plurality of word lines (Disclosing memory cells arranged in word lines: Lien, col.3:33-35),
the plurality of word lines including
a selected group of word lines to be erased in an erasing operation (Disclosing block enable line 317 connected to wordlines, enabling an erase operation within that block: Lien, col.13:21-34; See Also Lien Figure 7);
a control circuitry (Control Circuit 130: Lien, Figure 1A) for erasing the memory cells (Disclosing an erase operation: Lien, col.13:32-34)
in at least one erase loop (Suggesting performing an erase operation in iterative processes: Lien, col.18:21-23)
the at least one erase loop includes
an analog bitscan operation (Disclosing a verify operation producing a specified number rather than a simple pass/fail: Lien, col.21:26-29);
the control circuitry (Control Circuit 130: Lien, Figure 1A) being configured to:
determine an output of the analog bitscan operation (Disclosing comparing the output of the verification operation: Lien, col.21:37-38),
the output being one of at least three options (Disclosing the verification operation falling into three categories, for example the count compared to a BSPF <= 24, count between BSPF 24 and 72, and BSPF greater than 72: Lien, col.21:37-54).
Lien does not explicitly teach an erasing means for erasing the memory cells of the selected group of word lines in the at least one erase loop including an erase pulse with an erase-verify operation, with an analog bitscan operation outputting a strong fail, a weak fail, and a pass, and wherein the erasing means for erasing further increase the voltage of the erase pulse by a first step size in response to the output of the analog bitscan operation being strong fail, and increases the voltage of the erase pulse by as second step size in response to the output of the analog bitscan operation being weak fail, the second step size being different from the first step size.
Pitner, however, teaches an apparatus including an erasing means for erasing, wherein:
an erasing means for erasing the memory cells (Disclosing an erase operation: Lien, col.13:32-34)
of the selected group of word lines (Disclosing performing an erase operation on a block: Pitner, col.8:32-33; Wherein the block includes a set of NAND strings in communication with a common set of word lines: Pitner, col.8:19-20)
the at least one erase loop (Disclosing a trial erase loop: Pitner, col.14:40-41) including
an erase pulse (Disclosing an erase operation starting with an initial erase pulse: Pitner, col.14:22),
the erase-verify operation (Disclosing a single erase-verify operation: Pitner, Figure 8, Step 804) including the application of only a single erase-verify reference voltage to the word lines of the selected group of word lines (Teaching the second erase operation does not include an erase verification step, therefore limiting the erase loop to a single erase verification step and, by definition, only a single erase verification voltage: Pitner, col.16:65-66), and
an analog bitscan operation that follows the single erase-verify operation (Performing a determination step following the first erase-verify operation: Pitner, Figure 8, Steps 806 and 808);
increase a voltage of the erase pulse by a first step size (Disclosing deriving a second erase voltage based on the identified upper tail Vt: Pitner, col.16:6-17)
in response to the output of the analog bitscan operation being strong fail (Pitner does not use terms such as ‘strong fail’ or ‘weak fail.’ The step size increase between pulses is instead determined based on the overall failure rate. Therefore, more cells failing verification [a strong fail] will inherently result in a larger step size increase), and
increase the voltage of the erase pulse by a second step size in response to the output of the analog bitscan operation being weak fail (The voltage between the trial erase and second erase pulse is derived from the output of the bit scan and upper tail Vt. Where the bit scan results differ, the voltage step will therefore necessarily differ.; See Also Disclosing the determination of the second erase voltage comes from a table based on the upper tail Vt: Pitner, col.16:55-59), the second step size being different than the first step size (A second step size is different from a first step size, by definition).
Pitner discloses estimating the optimal erase value allows the erase operation to succeed reliably despite variations in erase pulse characteristics (Teaching applying a trial pulse to memory cells during an erase operation to identify ideal erase pulse characteristics: Pitner, col.14:40-53; Further teaching the natural variation of required erase pulse characteristics over time: Pitner, col.14:53-56).
Therefore, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the invention to combine the optimal erase pulse determination method of Pitner with the analog verification method of Lien. The inventions are known variants of program/erase cycle verification operations and the combination of known inventions with predictable results is obvious and not patentable.
Neither Lien nor Pitner expressly teaches an erasing means for erasing including an analog bitscan operation wherein the output comprises a strong fail, a weak fail, and a pass.
Kurosawa, however, teaches an erasing means for erasing including an analog bitscan operation wherein the output comprises:
a strong fail, a weak fail, and a pass (Disclosing four tiers of errors, numbered 0-3. Does not apply the specific titles as above, but the tiers map to the same concepts, with 3 being a strong fail though 0 being a strong pass: Kurosawa, col.4:31-40; See Also, Kurosawa, Table 1 and Figure 4),
Kurosawa discloses estimating the BER during program/erase operations and beyond a simple indicator of success or not is less time consuming than the conventional approach and allows block optimization (Kurosawa, col.2:52-63).
Therefore, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the invention to combine the four-plus BER tiers of Kurosawa with the analog verification method of Lien. The inventions are known variants of program/erase cycle verification operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 18, Kurosawa discloses the apparatus as set forth in claim 17, wherein the at least three options for the output of the analog bitscan operation further comprises
a weak pass and a strong pass (Disclosing the four tiers of BER given in Table 1 a based on a two-bit binary value and using additional bits allows additional conditions: Kurosawa, col. 4:26-30).
Regarding Claim 19, Lien and Pitner disclose the apparatus as set forth in claim 18, wherein the control circuitry is further configured
to increase the voltage of the erase pulse
by the second step size in response to the output of the analog bitscan operation being weak pass (The voltage between the trial erase and second erase pulse is derived from the output of the bit scan and upper tail Vt. Where the bit scan results differ, the voltage step will therefore necessarily differ.; See Also Disclosing the determination of the second erase voltage comes from a table based on the upper tail Vt: Pitner, col.16:55-59) and
to end the erasing operation (Disclosing the operation being complete under this final verification output and setting an inhibit voltage to prevent further modification: Lien, col.51-54)
in response to the output of the analog bitscan operation being strong pass (Disclosing the count of cells failing a BSPF step being below a set threshold: Lien, col.21:50).
Regarding Claim 20, Pitner discloses the apparatus as set forth in claim 17, wherein the control circuitry is further configured
to apply an additional erase pulse (Disclosing applying an additional erase pulse at the second derived erase voltage: Pitner, col.16:60-61)
to the selected group of word lines in response to the output of the analog bitscan operation being weak fail (The voltage between the trial erase and second erase pulse is derived from the output of the bit scan and upper tail Vt. Where the bit scan results differ, the voltage step will therefore necessarily differ.; See Also Disclosing the determination of the second erase voltage comes from a table based on the upper tail Vt: Pitner, col.16:55-59).
Claim(s) 5 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. 11,475,959 to Yu-Chung Lien, et al. (hereafter Lien) in view of U.S. 11,568,943 to Xue Bai Pitner, et al. (hereafter Pitner), U.S. 10,366,770 to Yasuhiko Kurosawa, et al. (hereafter Kurosawa), and further in view of U.S. 12,142,328 to Kaijin Huang (hereafter Huang).
Regarding Claim 5, Lien discloses the method as set forth in claim 4, but fails to disclose the further limitations of Claim 5. Huang, however, discloses a method as in claim 4, but wherein
the second step size is approximately half of the first step size (Teaching an erase voltage step increase
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where M = 1, the second step size will be one half the prior step increase: Huang col.19:14-23).
Huang discloses this reduced step erase voltage helps avoid either an overly deep or shallow erase, resolving problems of reduced read margin or deteriorated endurance (Huang col.19:23-25).
Therefore, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the invention to combine the halving step-wise erase voltage decrease of Huang with the analog verification system of Lien. The inventions are known variants of program/erase cycle operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 13, Lien discloses the memory device as set forth in claim 12, but fails to disclose the further limitations of Claim 12. Huang, however, discloses a memory device as in Claim 12 wherein
the second step size is approximately half of the first step size (Teaching an erase voltage step increase
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Greyscale
where M = 1, the second step size will be one half the prior step increase: Huang col.19:14-23).
Huang discloses this reduced step erase voltage helps avoid either an overly deep or shallow erase, resolving problems of reduced read margin or deteriorated endurance (Huang col.19:23-25).
Therefore, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the invention to combine the halving step-wise erase voltage decrease of Huang with the analog verification system of Lien. The inventions are known variants of program/erase cycle operations and the combination of known inventions with predictable results is obvious and not patentable.
Allowable Subject Matter
Claims 21-23 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The following is an examiner’s statement of reasons for allowance:
Regarding New Claim 21 and the substantially similar limitations of New Claims 22-23, Pitner discloses the method as set forth in claim 1, wherein the step of setting the at least one erase parameter based on the output of the analog bitscan operation comprises;
in response to the output being strong fail (Disclosing using the bit scan to estimate the upper tail Vt: Pitner Figure 9B),
increasing a voltage of the erase pulse by a first step size (Disclosing deriving a second erase voltage based on the identified upper tail Vt: Pitner, col.16:6-17),
in response to the output being weak fail,
increasing the voltage of the erase pulse by a second step size
that is less than the first step size (The voltage between the trial erase and second erase pulse is derived from the output of the bit scan and upper tail Vt. Where the bit scan results differ, the voltage step will therefore necessarily differ.; See Also Disclosing the determination of the second erase voltage comes from a table based on the upper tail Vt: Pitner, col.16:55-59) and
applying an additional erase pulse to the selected group of word lines, and
in response to the output being pass (On a success: Pitner, col.12:34-36),
ending the erasing operation (Concluding the operation on a success: Pitner, col.12:37-40).
The prior art of record and considered pertinent to the applicant’s disclosure, include prior art Pitner and Lien, individually or in combination, does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
A method as in Claim 1, wherein the analog bitscan operation comprises
calculating a busy time of the bitscan operation and
comparing the busy time to a busy time threshold;
wherein, the output of the analog bitscan operation
is based on the comparison of the busy time to the busy time threshold and
is one of strong fail, weak fail, or pass.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. 11,342,035 B2 to Xue Bai Pitner, et al.: Disclosing a programming operation controlled by BSPF criteria or FSENSE time.
U.S. 2018/0286485 A1 by Kazutaka Takizawa, et al.: Disclosing an erase operation with multiple levels of Fail Bit Count verification.
U.S. 2017/0206124 A1 by Bong-Soon Lim, et al.: Disclosing counting and storing counts of failed bits in a register.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824