DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 19 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20220122651 A1, hereinafter Kim’651) of record.
Regarding independent claim 19, Kim‘651 teaches, “An electronic system (2000, fig. 26, fig. 1-26; ¶ [0029] - ¶ [0148]) comprising:
a main substrate (substrate of storage device 2200, fig. 26);
a semiconductor device (2220) disposed on the main substrate; and
a controller (2210) electrically connected to the semiconductor device (2220) on the main substrate,
wherein the semiconductor device (2220) comprises:
a first structure (PERI, fig. 25) comprising a first substrate (1101), a peripheral circuit (1120 etc) disposed on the first substrate (1101), a first insulating structure (1190) disposed on the peripheral circuit (1120) and the first substrate (1101), and a first bonding pad (1195) disposed on the first insulating structure (1190);
a second structure (CELL) comprising a common source plate (1002), a cell stack (1020, 1030, CH), a second insulating structure (1090), a second bonding pad (1065), and an interconnect structure (1060, 1055, 1050) electrically connecting the cell stack to the second bonding pad (1065),
wherein the cell stack (1020, 1030, CH) is disposed on the common source plate (1002) and comprises a plurality of gate electrodes (1030) and a plurality of channel structures (CH) connected to the common source plate (1002) by passing through the plurality of gate electrodes (1030),
wherein the second insulating structure (1090) is disposed on the cell stack and is in contact with the first insulating structure (1190), wherein the second bonding pad (1065) is disposed on the second insulating structure (1190) and is in contact with the first bonding pad (1195), wherein the cell stack comprises a plurality of cell blocks (CBK, DBKSC) defined between a plurality of stack insulating layers (1005) extending in a first horizontal direction (X) by passing through the cell stack, and the plurality of cell blocks comprises a plurality of main blocks (CBK) and at least one dummy block (DBKSC) disposed at one side of the plurality of main blocks (CBK); and
a connection structure (190, 153, 155 etc, fig. 7) comprising an outer insulating layer (190) and an input-output pad (153, 155), wherein the connection structure covers the common source plate (102) and is disposed on the second structure (CELL), and wherein the input-output pad (153, 155) is disposed on the outer insulating layer (190) and is electrically connected to the interconnect structure, wherein at least a portion of the input-output pad (153, 155) vertically overlaps at least a portion of the at least one dummy block (DBKSC),
wherein the common source plate (1002) comprises a main common source line region (part of element 1002 overlapping CBK) and a dummy common source line region (part of element 1002 overlapping DBKSC), wherein the main common source line region vertically overlaps the plurality of main blocks (CBK), wherein the dummy common source line region is separated and electrically isolated from the main common source line region (separated by element 106) and vertically overlaps the at least one dummy block (DBKSC) .
Allowable Subject Matter
Claims 1-9 and 13-18 are allowed. The restriction requirement, as set forth in the Office action mailed on 09/29/2025, has been reconsidered in view of the allowability of claim 1 to the elected invention pursuant to MPEP § 821.04(a). The restriction requirement is hereby withdrawn as to any claim that requires all the limitations of an allowable claim. Claims 9-12 directed to a non-elected invention are no longer withdrawn from consideration because the claim(s) requires all the limitations of an allowable claim. In view of the above noted withdrawal of the restriction requirement, applicant is advised that if any claim presented in a continuation or divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Once a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding independent claim 1 and 13, the applicant has sufficiently claimed and defined a semiconductor device, whereby the prior arts of record and to the examiner's knowledge do not teach or render obvious, at least to the skilled artisan, the instant invention regarding the semiconductor device comprising: wherein each of the plurality of channel structures included in both of the main block and the dummy block is electrically connected to the common source plate. The closest prior art of record, Kim et al. (US 20220122651 A1, fig. 23-25) teaches, a memory device (1000) comprising a main block (CBK) and a dummy block (DBKsc), wherein the main block (CBK) comprising a plurality of channel structures (CH), and the plurality of channel structures (CH) are connected to a common source plate (1002), but fails to teach, wherein dummy block (DBKsc) also comprises channel structures. None of the prior arts of record, either singularly or in combination, can be used to modify the device of Kim et al. to teach the above missing feature with obvious motivation or without breaking the device of Kim et al.
Claims 2-12 and 14-18 are also rejected as they depend on the independent claims 1 and 13.
Again, claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claim 20, the prior arts of record do not anticipate or make obvious, inter alia, the feature of: a bit line electrically connected to a first channel structure included in a main block, of the plurality of main blocks, among the plurality of channel structures and electrically isolated from a second channel structure included in the at least one dummy block among the plurality of channel structures; and
Response to Arguments
Applicant’s arguments with respect to the newly amended claims 1 and 13 have been considered and the claims are allowed. The applicant did not place any arguments on the rejection of amended claim 19.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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