DETAILED ACTION
Election/Restrictions
Applicant’s election species A-B, reflected in claims 1-8, 13-20 in the reply filed on 08/09/2023 is acknowledged. Claims 9-12 are withdrawn from further consideration pursuant to 37 CFR 1.142 (b), as being drawn to the nonelected group.
Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 13-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20220122651 A1, hereinafter Kim‘651).
Regarding independent claim 1, Kim‘651 teaches, “A semiconductor device (fig. 1-26; ¶ [0029] - ¶ [0148]) comprising:
a first structure (PERI, fig. 25) comprising a first substrate (1101), a peripheral circuit (1120 etc) disposed on the first substrate (1101), a first insulating structure (1190) disposed on the peripheral circuit (1120) and the first substrate (1101), and a first bonding pad (1195) disposed on the first insulating structure (1190); and
a second structure (CELL) comprising a common source plate (1002), a cell stack (1020, 1030, CH), a second insulating structure (1090), a second bonding pad (1065), and an interconnect structure (1060, 1055, 1050) electrically connecting the cell stack to the second bonding pad (1065),
wherein the cell stack (1020, 1030, CH) is disposed on the common source plate (1002) and comprises a plurality of gate electrodes (1030) and a plurality of channel structures (CH) connected to the common source plate (1002) by passing through the plurality of gate electrodes (1030),
wherein the second insulating structure (1090) is disposed on the cell stack and being in contact with the first insulating structure (1190),
wherein the second bonding pad (1065) is disposed on the second insulating structure (1190) and is in contact with the first bonding pad (1195),
wherein the cell stack comprises a plurality of cell blocks (CBK, DBKSC) defined between a plurality of stack insulating layers (1005) extending in a first horizontal direction (X) by passing through the cell stack, and
wherein the plurality of cell blocks comprises a plurality of main blocks (CBK) and at least one dummy block (DBKSC) disposed at one side of the plurality of main blocks (CBK),
wherein the common source plate (1002) comprises a main common source line region (part of element 1002 overlapping CBK) and a dummy common source line region (part of element 1002 overlapping DBKSC), wherein the main common source line region vertically overlaps the plurality of main blocks (CBK),
wherein the dummy common source line region is separated from the main common source line region (separated by element 1060) and vertically overlaps the at least one dummy block (DBKSC) by being electrically isolated (by insulating layer 1003/103, ¶ [0072]) from the at least one dummy block (DBKSC)”.
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Regarding claim 2, Kim‘651 further teaches, “The semiconductor device of claim 1, wherein the dummy common source line region is configured to float (as the dummy common source line is isolated from main common source line region, fig. 18 and fig. 25) when a common source voltage is applied to the main common source line region.
Regarding claim 3, Kim‘651 further teaches, “The semiconductor device of claim 1, wherein the second structure (CELL, fig. 25) further comprises a bit line (1053, 1055) electrically connected to a first channel structure (CH) included in the plurality of main blocks (CBK) among the plurality of channel structures and electrically isolated from a second channel structure (DCH, fig. 18) included in the at least one dummy block (DBKBC) among the plurality of channel structures”.
Regarding claim 4, Kim‘651 further teaches, “The semiconductor device of claim 3, wherein the bit line (1035, 1055, fig. 25) extends in a second horizontal direction (Y), which is substantially perpendicular to the first horizontal direction (X), to vertically overlap both the first channel structure and the second channel structure (CH), wherein a first bit line contact (BCNT, fig. 8) is disposed between the bit line and the first channel structure to electrically connect the bit line to the first channel structure (¶ [0075]), and no bit line contact is disposed between the bit line and the second channel structure (fig. 8)”.
Regarding claim 5, Kim‘651 further teaches, “The semiconductor device of claim 3, wherein the bit line (1035, 1055, fig. 25) extends in a second horizontal direction (Y), which is substantially perpendicular to the first horizontal direction (X), to vertically overlap the first channel structure and not to vertically overlap the second channel structure (CH), and wherein a first bit line contact (BCNT, fig. 8) is disposed between the bit line and the first channel structure to electrically connect the bit line to the first channel structure (CH)”.
Regarding claim 6, Kim‘651 further teaches, “The semiconductor device of claim 1, wherein the second structure (CELL) further comprises a common source isolation insulating layer (1005) disposed between the main common source line region and the dummy common source line region of the common source plate (1002)”.
Regarding claim 7, Kim‘651 further teaches, “The semiconductor device of claim 6, wherein the common source isolation insulating layer (1005) extends in the first horizontal direction (X or Y), and the dummy common source line region (1002) has a rectangular shape”.
Regarding claim 8, Kim‘651 further teaches, “The semiconductor device of claim 1, further comprising a connection structure (190, 153, 155 etc, fig. 7) comprising an outer insulating layer (190) and an input-output pad (153, 155), wherein the connection structure covers the common source plate (102) and is disposed on the second structure (CELL), and wherein the input-output pad (153, 155) is disposed on the outer insulating layer (190) and is electrically connected to the interconnect structure, wherein at least a portion of the input-output pad (153, 155) vertically overlaps at least a portion of the at least one dummy block (DBKSC)”.
Regarding independent claim 13, Kim‘651 teaches, “A semiconductor device (fig. 1-26; ¶ [0029] - ¶ [0148]) comprising:
a first structure (PERI, fig. 25) comprising a first substrate (1101), a peripheral circuit (1120 etc) disposed on the first substrate (1101), a first insulating structure (1190) disposed on the peripheral circuit (1120) and the first substrate (1101), and a first bonding pad (1195) disposed on the first insulating structure (1190); and
a second structure (CELL) comprising a common source plate (1002), a cell stack (1020, 1030, CH), a second insulating structure (1090), and a second bonding pad (1065) disposed on the second insulating structure (1090) and being in contact with the first bonding pad (1195),
wherein the cell stack (1020, 1030, CH) is disposed on the common source plate (1002) and comprises a plurality of gate electrodes (1030) and a plurality of channel structures (CH) passing through the plurality of gate electrodes (1030), wherein the second insulating structure (1090) is disposed on the cell stack and is in contact with the first insulating structure (1190), wherein the cell stack comprises a main block (CBK) and a dummy block (DBKSC, DBKBC) disposed at one side of the main block (CBK),
wherein the common source plate (1002) comprises:
a main common source line region (part of element 1002 overlapping CBK) connected to a first channel structure (CH, ¶ [0080]) in the main block among the plurality of channel structures; and
a dummy common source line region (part of element 502 overlapping DBKBC, fig. 18) connected to a second channel structure (DCH) in the dummy block among the plurality of channel structures and separated from the main common source line region (separated by element 106),
wherein the dummy common source line region is configured to float (as the dummy common source line is isolated from main common source line region, fig. 18 and fig. 25) when a common source voltage is applied to the main common source line region”.
Regarding claim 14, Kim‘651 further teaches, “The semiconductor device of claim 13, wherein the cell stack further comprises a stack insulating layer (1005) extending in a first horizontal direction (X) between the main block (CBK) and the dummy block (DBKSC) by passing through the cell stack, and the second structure (CELL) further comprises a bit line (1053, 1055) extending in a second horizontal direction (Y), which is substantially perpendicular to the first horizontal direction (X), and electrically connected to the first channel structure (CH), wherein the bit line (1053, 1055) is electrically isolated from the second channel structure (CH)”.
Regarding claim 15, Kim‘651 further teaches, “The semiconductor device of claim 14, wherein the bit line (1035, 1055, fig. 25) extends in the second horizontal direction (Y) to vertically overlap both the first channel structure and the second channel structure (CH), wherein a first bit line contact (BCNT, fig. 8) is disposed between the bit line and the first channel structure to electrically connect the bit line to the first channel structure (¶ [0075]), and no bit line contact is disposed between the bit line and the second channel structure (fig. 8)”.
Regarding claim 16, Kim‘651 further teaches, “The semiconductor device of claim 14, wherein the bit line (1035, 1055, fig. 25) extends in the second horizontal direction (Y) to vertically overlap the first channel structure (CH) and not to vertically overlap the second channel structure, and wherein a first bit line contact (BCNT, fig. 8) is disposed between the bit line and the first channel structure”.
Regarding claim 17, Kim‘651 further teaches, “The semiconductor device of claim 13, further comprising: an outer insulating layer (190, fig. 7) covering the common source plate (102) and disposed on the second structure (CELL); and an input-output pad (153, 155) disposed on the outer insulating layer (102), wherein at least a portion of the input-output pad (153, 155) vertically overlaps at least a portion of the dummy block (DBKSC)”.
Regarding claim 18, Kim‘651 further teaches, “The semiconductor device of claim 17, wherein the second structure (CELL) further comprises a common source isolation insulating layer (1005) disposed between the main common source line region and the dummy common source line region, and wherein the common source isolation insulating layer (1005) is connected to the outer insulating layer (190)”.
Regarding independent claim 19, Kim‘651 teaches, “An electronic system (2000, fig. 26, fig. 1-26; ¶ [0029] - ¶ [0148]) comprising:
a main substrate (substrate of storage device 2200, fig. 26);
a semiconductor device (2220) disposed on the main substrate; and
a controller (2210) electrically connected to the semiconductor device (2220) on the main substrate,
wherein the semiconductor device (2220) comprises:
a first structure (PERI, fig. 25) comprising a first substrate (1101), a peripheral circuit (1120 etc) disposed on the first substrate (1101), a first insulating structure (1190) disposed on the peripheral circuit (1120) and the first substrate (1101), and a first bonding pad (1195) disposed on the first insulating structure (1190);
a second structure (CELL) comprising a common source plate (1002), a cell stack (1020, 1030, CH), a second insulating structure (1090), a second bonding pad (1065), and an interconnect structure (1060, 1055, 1050) electrically connecting the cell stack to the second bonding pad (1065),
wherein the cell stack (1020, 1030, CH) is disposed on the common source plate (1002) and comprises a plurality of gate electrodes (1030) and a plurality of channel structures (CH) connected to the common source plate (1002) by passing through the plurality of gate electrodes (1030),
wherein the second insulating structure (1090) is disposed on the cell stack and is in contact with the first insulating structure (1190), wherein the second bonding pad (1065) is disposed on the second insulating structure (1190) and is in contact with the first bonding pad (1195), wherein the cell stack comprises a plurality of cell blocks (CBK, DBKSC) defined between a plurality of stack insulating layers (1005) extending in a first horizontal direction (X) by passing through the cell stack, and the plurality of cell blocks comprises a plurality of main blocks (CBK) and at least one dummy block (DBKSC) disposed at one side of the plurality of main blocks (CBK); and
a connection structure (190, 153, 155 etc, fig. 7) comprising an outer insulating layer (190) and an input-output pad (153, 155), wherein the connection structure covers the common source plate (102) and is disposed on the second structure (CELL), and wherein the input-output pad (153, 155) is disposed on the outer insulating layer (190) and is electrically connected to the interconnect structure, wherein at least a portion of the input-output pad (153, 155) vertically overlaps at least a portion of the at least one dummy block (DBKSC),
wherein the common source plate (1002) comprises a main common source line region (part of element 1002 overlapping CBK) and a dummy common source line region (part of element 1002 overlapping DBKSC), wherein the main common source line region vertically overlaps the plurality of main blocks (CBK), wherein the dummy common source line region is separated from the main common source line region (separated by element 106) and vertically overlaps the at least one dummy block (DBKSC) by being electrically isolated (by insulating layer 1003/103, ¶ [0072]) from the at least one dummy block (DBKSC)”.
Regarding claim 20, Kim‘651 further teaches, “The electronic system of claim 19, wherein the second structure further comprises:
a bit line (1053, 1055, fig. 25) electrically connected to a first channel structure (CH) included in a main block of the plurality of main blocks (CBK), among the plurality of channel structures and electrically isolated from a second channel structure (DCH, fig. 18) included in the at least one dummy block (DBKBC) among the plurality of channel structures; and
a common source isolation insulating layer (1005) disposed between the main common source line region and the dummy common source line region of the common source plate (1002), and
wherein the dummy common source line region is configured to float (as the dummy common source line is isolated from main common source line region, fig. 18 and fig. 25) when a common source voltage is applied to the main common source line region”.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817