DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group VII, Species J (Figure 20) in the reply filed on 02/12/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 26 and 39 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 26 and 39 state “wherein a roughness of an upper surface of an insulating layer disposed lowermost, among the plurality of second insulating layers, is greater than a roughness of an upper surface of a remaining insulating layer except for an insulating layer disposed lowermost, among the plurality of second insulating layers”, however there is no support in the Specification for a “wherein a roughness of an upper surface of an insulating layer disposed lowermost, among the plurality of second insulating layers, is greater than a roughness of an upper surface of a remaining insulating layer except for an insulating layer disposed lowermost, among the plurality of second insulating layers” motor wire winding. This language is without support from the Specification.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18 – 20, 22 – 27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation "the" in “is disposed on the first via”. There is insufficient antecedent basis for this limitation in the claim.
Claims 19 – 20 and 22 – 27 are rejected due to dependency from claim 18.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 18 – 20 and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimizu (US 2015/0062851 A1).
Regarding Claim 18, Shimizu (US 2015/0062851 A1) discloses a printed circuit board (Fig 1) comprising: a first substrate portion (annotated FIRST SUBSTRTATE PORTION; a portion or region comprising 20,23,22,51,53; note that the claim has not structurally defined nor limited this claimed portion) including a plurality of first insulating layers (51,20,52,53), a plurality of first wiring layers (22,23) respectively disposed on or in the plurality of first insulating layers, and a plurality of first via layers (layers with V4,V5,64) penetrating through at least a portion of one or more of the plurality of first insulating layers; a second substrate portion (annotated SECOND SUBSTRTATE PORTION; portion or region comprising 32,33,V2) disposed on the first substrate portion; and an intermediate insulating layer (31) disposed between the first and second substrate portions, wherein at least one first wiring (71) of a first wiring layer (layer with 71) disposed lowermost, among the plurality of first wiring layers, is disposed on (the) first via (64), and the first substrate portion includes a gap region (see Fig 1B; S1) for separating at least a portion of at least one first via (64) of a first via layer (layer with 64) disposed lowermost, among the plurality of first via layers (layers with V4,V5,64), from a first insulating layer (53) disposed lowermost, among the plurality of first insulating layers.
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Annotated Fig 1A from Shimizu (US 2015/0062851 A1)
Regarding Claim 19, Shimizu further discloses the printed circuit board (Fig 1) according to claim 18, wherein the first wiring (layer with 71) includes a first metal layer (77,78) disposed on the first via and a second metal layer (76) disposed on the first metal layer.
Regarding Claim 20, Shimizu further discloses the printed circuit board (Fig 1) according to claim 19, wherein the first metal layer (77,78) extends to a first insulating layer (53) disposed lowermost, among the plurality of first insulating layers and is disposed in the gap region (S1).
Regarding Claim 27, The printed circuit board according to claim 18, further comprising: a third substrate portion (a portion or region about 70; note that the claim has not structurally defined nor limited this claimed portion) disposed on a surface opposite to a surface on which the second substrate portion (annotated SECOND SUBSTRTATE PORTION; portion or region comprising 32,33,V2) of the first substrate portion (annotated FIRST SUBSTRTATE PORTION; a portion or region comprising 20,23,22,51,53; note that the claim has not structurally defined nor limited this claimed portion) is disposed, wherein the third substrate portion includes a third insulating layer (82,83), a third wiring layer (72,73) formed on the third insulating layer, and a third via layer (layer with V8) penetrating through at least a portion of the third insulating layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 22 – 24 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 2015/0062851 A1) as applied to claim 18 above, and further in view of Shuto (US 2022/0394844 A1).
Regarding Claim 22, Shimizu discloses the limitations of the preceding claim.
Shimizu does not disclose the printed circuit board according to claim 18, wherein a thickness, along a first side surface of the first substrate portion, of the first substrate portion is thicker than a thickness, along a second side surface facing the first side surface of the first substrate portion, of the first substrate portion.
Shuto (US 2022/0394844 A1; [0044]) teaches of a printed circuit board (Fig 3), wherein a thickness (T2), along a first side surface (side surface of 902) of a first substrate portion (9; portion about 901,902), of the first substrate portion is thicker than a thickness (T1), along a second side surface (side surface of 901) facing the first side surface of the first substrate portion, of the first substrate portion.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Shimizu, wherein a thickness, along a first side surface of the first substrate portion, of the first substrate portion is thicker than a thickness, along a second side surface facing the first side surface of the first substrate portion, of the first substrate portion as taught by Shuto, in order to provide a desired profile when mounting different sized components (Shuto, [0076]). Note also a thicker portion would provide more structural support for any mounted components and thus could better support a heavier component. Furthermore it can be seen by Fig 3, the increased thickness region comprises an increased amount of electrically conductive layers allowing for an increased electrical activity in the thicker region.
Regarding Claim 23, Shimizu in view of Shuto teaches the limitations of the preceding claim and Shuto further teaches the printed circuit board (Fig 3) according to claim 22, wherein the first substrate portion (9) is inclined (see centrally located portion between 901 and 902 having a slant or incline) so that a thickness (T2) along the first side surface (side surface of 902) thereof is the thickest and a thickness (T1) along the second side surface (side surface of 901) thereof is the thinnest.
Regarding Claim 24, Shimizu in view of Shuto teaches the limitations of the preceding claim.
Shuto further teaches of a printed circuit board (Fig 3) according to claim 23 wherein a thickness, along a first side surface (a side surface of 17) of a second substrate portion (at 17), of a second substrate portion (17) is substantially identical to a thickness, along a second side surface (other side surface of 17) facing the first side surface of the second substrate portion, of the second substrate portion (17).
Claim(s) 25 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 2015/0062851 A1) as applied to claim 18 above.
Regarding Claim 25, Shimizu further discloses the printed circuit board (Fig 1) according to claim 18, wherein the second substrate portion includes a plurality of second insulating layers (32,33), a plurality of second wiring layers (41,42,V3) respectively disposed on or in the plurality of second insulating layers, and a plurality of second via layers (V2,V3) penetrating through at least a portion of one or more of the plurality of second insulating layers.
Shimizu does not explicitly disclose the second substrate portion includes a wiring finer than a wiring of the first substrate portion.
However Shimizu already teaches of a portion (portion about 70) comprising fine wiring, such that the wiring is finer than ([0058-0060]) a wiring of the first substrate portion (a portion or region comprising 20,23,22,51,53).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Shimizu, wherein the second substrate portion includes a wiring finer than a wiring of the first substrate portion as taught by Shimizu, as both limitations are present in the same publication and since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art, in order to provide a minimization and enhancement in performance (Shimizu, [0004,0058-0060,0115]). Such a combination would allow for finer wiring and enhanced performance by allowing the mounting of finer components on both upper and lower sides of the printed circuit board. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Claim(s) 26 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 2015/0062851 A1) as applied to claim 25 above, and further in view of Tsukamoto (US 2017/0372991 A1).
Regarding Claim 26, Shimizu discloses the limitations of the preceding claim.
Shimizu does not explicitly disclose the printed circuit board according to claim 25, wherein a roughness of an upper surface of an insulating layer disposed lowermost, among the plurality of second insulating layers, is greater than a roughness of an upper surface of a remaining insulating layer except for an insulating layer disposed lowermost, among the plurality of second insulating layers.
Tsukamoto (US 2017/0372991 A1) teaches of a printed circuit board (Fig 1) wherein a roughness ([0078] e.g. 15 to 40 nm) of an upper surface of an insulating layer (33B) disposed lowermost, among a plurality of second insulating layers (33,51,52), is greater than a roughness ([0087] e.g. 2 to 10 nm) of an upper surface of a remaining insulating layer (51) except for an insulating layer (33) disposed lowermost, among the plurality of second insulating layers.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Shimizu, wherein a roughness of an upper surface of an insulating layer disposed lowermost, among the plurality of second insulating layers, is greater than a roughness of an upper surface of a remaining insulating layer except for an insulating layer disposed lowermost, among the plurality of second insulating layers as taught by Tsukamoto, in order to allow formation of finer wiring on upper regions of the second insulating layer while also increasing adhesiveness between the second insulating layer and the rest of the printed circuit board as well as increase adhesiveness between the metal wiring and the lowermost second insulating layer (Tsukamoto, [0026,0048,0065,0073-0078,0087,0113]). Note that the Applicant has not provided any criticality for this claimed aspect in the Applicant’s Specification.
Claim(s) 36 – 38 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 2015/0062851 A1) in view of Shuto (US 2022/0394844 A1).
Regarding Claim 36, Shimizu discloses a printed circuit board (Fig 1) comprising: a first substrate portion (a portion or region comprising 20,23,22,51; note that the claim has not structurally defined nor limited this claimed portion) including a plurality of first insulating layers (20,51,52), a plurality of first wiring layers (22,61,62) respectively disposed on or in the plurality of first insulating layers, and a plurality of first via layers (layers with V4,V5) penetrating through at least a portion of one or more of the plurality of first insulating layers; a second substrate portion (portion or region about 70) disposed on the first substrate portion, and including a plurality of second insulating layers (81,82), a plurality of second wiring layers (71,72) respectively disposed on or in the plurality of second insulating layers, and a plurality of second via layers (layers with V7,V8) penetrating through at least a portion of one or more of the plurality of second insulating layers; and an intermediate insulating layer (layer at 53) disposed between the first and second substrate portions, wherein a thickness (as seen in Fig 1, right side of portion about 70 has a thickness), along a first side surface (right side of portion about 70) of the second substrate portion, of the second substrate portion is substantially identical to a thickness (as seen in Fig 1, left side of portion about 70 has a thickness), along a second side surface (left side of Fig 1) facing the first side surface of the second substrate portion, of the second substrate portion.
Shimizu does not disclose a thickness, along a first side surface of the first substrate portion, of the first substrate portion is thicker than a thickness, along a second side surface facing the first side surface of the first substrate portion, of the first substrate portion.
Shuto (US 2022/0394844 A1) teaches of a printed circuit board (Fig 3), wherein a thickness (T2), along a first side surface (side surface of 902) of a first substrate portion (9; portion about 901,902), of the first substrate portion is thicker than a thickness (T1), along a second side surface (side surface of 901) facing the first side surface of the first substrate portion, of the first substrate portion.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Shimizu, wherein a thickness, along a first side surface of the first substrate portion, of the first substrate portion is thicker than a thickness, along a second side surface facing the first side surface of the first substrate portion, of the first substrate portion as taught by Shuto, in order to provide a desired profile when mounting different sized components (Shuto, [0076]). Note also a thicker portion would provide more structural support for any mounted components and thus could better support a heavier component. Furthermore it can be seen by Fig 3, the increased thickness region comprises an increased amount of electrically conductive layers allowing for an increased electrical activity in the thicker region.
Regarding Claim 37, Shimizu in view of Shuto teaches the limitations of the preceding claim and Shuto further teaches the printed circuit board (Fig 3) according to claim 36, wherein the first substrate portion (9) is inclined (see centrally located portion between 901 and 902 having a slant or incline) so that a thickness (T2) along the first side surface (side surface of 902) thereof is the thickest and a thickness (T1) along the second side surface (side surface of 901) thereof is the thinnest.
Regarding Claim 38, Shimizu in view of Shuto teaches the limitations of the preceding claim.
Shimizu further discloses the printed circuit board according to claim 36 (Fig 1), the second substrate portion (portion about 70) includes a wiring finer ([0058-0060]) than a wiring of the first substrate portion (a portion or region comprising 20,23,22,51).
Claim(s) 39 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 2015/0062851 A1) in view of Shuto (US 2022/0394844 A1)as applied to claim 36 above, and further in view of Tsukamoto (US 2017/0372991 A1).
Regarding Claim 39, Shimizu in view of Shuto teaches the limitations of the preceding claim.
Shimizu does not explicitly disclose the printed circuit board according to claim 36, wherein a roughness of an upper surface of an insulating layer disposed lowermost, among the plurality of second insulating layers, is greater than a roughness of an upper surface of a remaining insulating layer except for an insulating layer disposed lowermost, among the plurality of second insulating layers.
Tsukamoto (US 2017/0372991 A1) teaches of a printed circuit board (Fig 1) wherein a roughness ([0078] e.g. 15 to 40 nm) of an upper surface of an insulating layer (33B) disposed lowermost, among a plurality of second insulating layers (33,51,52), is greater than a roughness ([0087] e.g. 2 to 10 nm) of an upper surface of a remaining insulating layer (51) except for an insulating layer (33) disposed lowermost, among the plurality of second insulating layers.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as taught by Shimizu in view of Shuto, wherein a roughness of an upper surface of an insulating layer disposed lowermost, among the plurality of second insulating layers, is greater than a roughness of an upper surface of a remaining insulating layer except for an insulating layer disposed lowermost, among the plurality of second insulating layers as taught by Tsukamoto, in order to allow formation of finer wiring on upper regions of the second insulating layer while also increasing adhesiveness between the second insulating layer and the rest of the printed circuit board as well as increase adhesiveness between the metal wiring and the lowermost second insulating layer (Tsukamoto, [0026,0048,0065,0073-0078,0087,0113]). Note that the Applicant has not provided any criticality for this claimed aspect in the Applicant’s Specification.
Claim(s) 40 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 2015/0062851 A1) in view of Shuto (US 2022/0394844 A1)as applied to claim 36 above, and further in view of En (US 2004/0226745 A1).
Regarding Claim 40, Shimizu in view of Shuto teaches the limitations of the preceding claim.
Shimizu does not explicitly disclose the printed circuit board according to claim 36, further comprising: a solder resist layer disposed on the second substrate portion and including an opening exposing patterns of an uppermost one of the plurality of second wiring layers.
En (US 2004/0226745 A1) teaches of a printed circuit board (Fig 1) comprising: a solder resist layer (14) disposed on a second substrate portion (upper layers with 2) and including an opening (at 17) exposing patterns (15,7) of an uppermost one of a plurality of second wiring layers (7).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as taught by Shimizu in view of Shuto, further comprising: a solder resist layer disposed on the second substrate portion and including an opening exposing patterns of an uppermost one of the plurality of second wiring layers as taught by En, in order to provide protection for conductor circuitry (En, [0006]). Such a combination would also provide environmental protection by coating the upper circuit layer of the printed circuit board as well as provide insulation ([0259]) between conductive solder portions.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Yosui (US 2019/0090362 A1) teaches of a printed circuit board (Fig 1) comprising a first substrate portion (B1) wherein one side surface is thicker than the other side surface of the same substrate portion, wherein a second substrate portion (B3) atop comprising a same thickness on both side surfaces. This could be used in a 103 Rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2896