DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments to claims 1 and 12 has been fully considered. Based on the cited prior arts Koch and Yonehara and new grounds of rejection from Cheng the claims 1-8 and 12-19 are rejected.
Response to Amendment
Applicant’s amendments with respect to the claim objections has been fully considered and resolve the objections. The objections to the claims has been withdrawn. However, the amendment has introduced new claim objections and U.S.C. 112 rejections. Applicant’s cancellation of claims 9 and 10 has been acknowledged.
Claim Objections
Claim 12 is objected to because of the following informalities:
Claim 12 recites “separation of the compound semiconductor stack from the substrate”; this should be written as “separation of the CS stack from the substrate.” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 - 8 and 12 - 19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 on page 2, recites “removing the first handle substrate without utilizing a release layer configured to enable separation of the compound semiconductor stack from the substrate.“ A review of the specification finds no support for this limitation. The closest support is found in paragraph [0012], which recites “the entire handle substrate can be removed via a simple, highly selective wet etch that does not affect the optical-device material”; and paragraph [0091] which recites “since a CS chip handle substrate in accordance with the present disclosure is made of germanium, it can be removed via any of a variety of well-known wet or dry etches that highly selectively etch germanium, while not significantly attacking gallium arsenide or its compounds” but it does not disclose the negative limitation of “without utilizing…”
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "compound semiconductor stack" in line 9. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 8 and 12 - 19 are rejected under 35 U.S.C. 103 as being unpatentable over Koch et al. (US20210215874A1; hereinafter Koch) in view of Yonehara et al. (US20060166468A1; hereinafter Yonehara), further in view of Cheng et al. (US20170301611A1; hereinafter Cheng).
Regarding Claim 1 (Amended), Koch discloses a method (method of forming an integrated-optics system, [0029]) including:
providing a compound-semiconductor (CS) chip (photonic substrate 400) that includes a first CS layer (208) disposed on a first handle substrate (sacrificial substrate 402) comprising a conventional gallium arsenide wafer in the depicted example, FIG. 4A reproduced below, [0058], [0059];
providing a host substrate (substrate 108) including a first layer (silicon device layer 206) that comprises a first material that is selected from the group consisting of a dielectric layer (buried oxide layer (BOX) 204) and an indirect-bandgap semiconductor (206 is a layer of single-crystal silicon an indirect-bandgap semiconductor), FIG. 2A, [0053];
joining the CS chip and the host substrate (CS chip 400 is flipped over and bonded to host substrate 108) such that the first CS layer (208) is between the host substrate (108) and the first handle substrate (402), FIG. 4B reproduced below, [0067];
and removing the first handle substrate (402), FIG. 4B, [0068].
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Koch: FIGS. 4A, 4B
Koch discloses the first CS layer 208 disposed on a first handle substrate 402 comprising a conventional gallium arsenide wafer (FIG. 4A, [0058], [0059]) but does not disclose “a first handle substrate comprising germanium; removing the first handle substrate without utilizing a release layer configured to enable separation of the compound semiconductor stack from the substrate.”
In a similar art, Yonehara discloses a semiconductor structure including semiconductor substrate constituting germanium, [0013].
Yonehara discloses: providing a compound-semiconductor (CS) chip (layered CS structure) that includes a first CS layer (layer 105) disposed on a first handle substrate (germanium substrate 101) comprising germanium, FIG. 11 reproduced below, [0050], [0051].
Yonehara [0013], [0050] discloses germanium substrate 101 on which the compound semiconductor stack is grown and later separated, indicating 101 functions as a handle substrate.
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Yonehara: FIG. 11
Yonehara discloses that a method as taught reduces production cost since germanium substrates can be produced in large size [0063]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Koch’s method in order to reduce the production cost as disclosed by Yonehara [0063].
In a similar art, Cheng discloses a method of manufacturing a semiconductor structure [0001].
Cheng discloses removal of the primary substrate 10 and the epitaxial buffer layer 20 by grinding approximately 90 percent of the primary substrate 10 and thereafter selectively etching a remaining portion of the primary substrate 10 and the epitaxial buffer layer 20 with etching stopping at the etch selectivity layer 22, FIG. 9A, [0022].
The combination of Koch and Cheng discloses: removing the first handle substrate (Cheng: 10), without utilizing a release layer configured to enable separation of the compound semiconductor stack (Koch: stack 210 and 208) from the substrate (Cheng: 10, FIG. 9A, [0022]).
Cheng discloses that a method as taught for removal of the handle substrate without utilizing a release layer simplifies the manufacturing process [0022]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Koch and Yonehara’s method in order to simplify the manufacturing process as disclosed by Cheng [0022].
Regarding Claim 2, The combination of Koch, Yonehara, and Cheng discloses the method of claim 1.
Koch discloses: wherein the CS chip (400) includes a first CS stack (first stack 210 and 208) disposed on the first handle substrate (402), the first CS stack comprising a first plurality of CS layers (first stack 210 includes the constituent layers of OA device 110, including cladding layers, carrier confinement layers, and gain layer 212 and coupling layer 208, [0062]) that includes the first CS layer (208), FIG. 4A, [0058].
Koch [0071] discloses the substrate may include multiple active regions, each containing corresponding patterns of active material stack 210 disposed on coupling layer 208, indicating the CS chip includes a first CS stack comprising a first plurality of CS layers.
Regarding Claim 3, The combination of Koch, Yonehara, and Cheng discloses the method of claim 2.
Koch discloses: wherein the first plurality of CS layers (layers of the first active stack 210 and 208) includes a gain layer (212) comprising a quantum element (212 includes quantum-dot laser, quantum wells, quantum-well layers, quantum wires, quantum dashes, and the like), FIG. 4B, [0062], [0063].
Regarding Claim 4, The combination of Koch, Yonehara, and Cheng discloses the method of claim 2.
Koch discloses: wherein the method (method 300, FIG. 3, [0071]) further includes processing the first CS stack to form a first optically active device (operation 303: patterning 210 to define the shape of OA device 110, FIG. 3, [0071]) that is optically coupled with the first layer (206), FIG. 2A-2E, [0054], [0082].
Koch [0082] discloses OA device 110 is optically coupled to silicon waveguide 116 and [0054] discloses the silicon waveguide 116 is formed by patterning silicon device layer 206, indicating the OA device 110 is optically coupled to the waveguide 116 formed from the first layer 206.
Regarding Claim 5, The combination of Koch, Yonehara, and Cheng discloses the method of claim 4.
Koch discloses: wherein the first CS stack (first stack 210 and 208) is processed to define the first optically active device as a laser (210 includes constituent layers of optically active device 110 which is a quantum-dot laser), [0062].
Regarding Claim 6 (Amended), The combination of Koch, Yonehara, and Cheng discloses the method of claim 4.
Koch discloses: wherein the CS chip (400) is provided such that it includes a second CS stack (second stack 210 with coupling layer 208) comprising a second plurality of CS layers (layers of the second stack 210 and 208), [0071].
Koch [0071] discloses the substrate may include multiple active regions, each containing corresponding patterns of active material stack 210 disposed on coupling layer 208, indicating the CS chip includes a second CS stack comprising a second plurality of CS layers.
and wherein the process (method 300, FIG. 3, [0071]) further includes processing the second CS stack to define a second optically active device (operation 303, patterning stack 210 to define the shape of the second OA device 110, FIG. 3, [0071]) that is selected from the group consisting of a laser, an optical amplifier, an electro-absorption modulator, and a phase modulator (a laser, an optical amplifier, an electro-absorption modulator, and a phase modulator, [0062]).
Regarding Claim 7, The combination of Koch, Yonehara, and Cheng discloses the method of claim 4.
Koch discloses: wherein the CS chip (400) is provided such that it includes a second CS stack (second stack 210 and 208) comprising a second plurality of CS layers (layers of the second stack 210 and 208), [0071].
Koch [0071] discloses the substrate having multiple active regions, each containing corresponding patterns of active material stack 210, indicating the CS chip includes a second CS stack comprising a second plurality of CS layers.
and wherein the method (operation 300, FIG. 3, [0071]) further includes processing the second CS stack (second stack 210 and 208) to form a second optically active device (operation 303: patterning 210 to define the shape of OA device 110, FIG. 3, [0071]) that is optically coupled with the first layer (206), FIG. 2A-2E, [0054], [0082].
Koch [0082] discloses OA device 110 is optically coupled to silicon waveguide 116 and [0054] discloses the silicon waveguide 116 is formed by patterning silicon device layer 206, indicating the OA device 110 is optically coupled to the waveguide 116 formed from the first layer 206.
Regarding Claim 8, The combination of Koch, Yonehara, and Cheng discloses the method of claim 1.
Koch discloses: wherein the host substrate (108) is provided such that (1) the first layer comprises single-crystal silicon (first layer 206 is a layer of single-crystal silicon) and is disposed on a second handle substrate (202), [0053];
and (2) the first layer is patterned to define at least one silicon waveguide (the silicon waveguide 116 is formed by patterning first layer 206), FIG. 2E, [0054].
Regarding Claim 12 (Amended), Koch discloses a method (method of forming an integrated-optics system, [0029]) including:
providing a compound-semiconductor (CS) chip (photonic substrate 400) that includes a plurality of CS layers (active material stack 210 includes the constituent layers of OA device 110, including cladding layers, carrier confinement layers, and gain layer 212 and coupling layer 208, [0062]) that collectively define a CS stack (stack 210 and 208), the CS stack being disposed on a first handle substrate (sacrificial substrate 402) comprising a conventional gallium arsenide wafer in the depicted example, FIG. 4A, [0058], [0059].
providing a host substrate (substrate 108) that is a silicon-on-insulator substrate (108) including a silicon handle substrate (handle substrate 202 is a conventional silicon wafer), a buried oxide layer (204), and a device layer (206) that comprises single-crystal silicon (silicon device layer 206 is a layer of single-crystal silicon), [0053].
Koch [0053] discloses substrate 108 is a conventional silicon-on-insulator (SOI) substrate comprising handle substrate 202, buried oxide layer (BOX) 204, and silicon device layer 206.
wherein the device layer (206) is patterned to define a first silicon waveguide (116), [0054].
joining the CS chip and the host substrate (CS chip 400 is flipped over and bonded to host substrate 108) such that the CS stack (stack 210 and 208) is between the silicon handle substrate (202) and the first handle substrate (402), FIG. 4B, [0067];
and removing the first handle substrate (402), FIG. 4B, [0068].
Koch does not disclose “the CS stack being disposed on a first handle substrate consisting of germanium; removing the first handle substrate without utilizing a release layer configured to enable separation of the compound semiconductor stack from the substrate.”
In a similar art, Yonehara discloses a semiconductor structure including semiconductor substrate constituting germanium, [0013].
Yonehara discloses: providing a compound-semiconductor (CS) chip (layered CS structure) that includes a plurality of CS layers that collectively define a CS stack (layers 105, 106, 107, 108, and 109), the CS stack being disposed on a first handle substrate (germanium substrate 101) consisting of germanium, FIG. 11, [0050], [0051].
Yonehara [0013], [0050] discloses germanium substrate 101 on which the compound semiconductor stack is grown and later separated, indicating 101 functions as a handle substrate.
Yonehara discloses that a method as taught reduces production cost since germanium substrates can be produced in large size [0063]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Koch’s method in order to reduce the production cost as disclosed by Yonehara [0063].
In a similar art, Cheng discloses a method of manufacturing a semiconductor structure [0001].
Cheng discloses removal of the primary substrate 10 and the epitaxial buffer layer 20 by grinding approximately 90 percent of the primary substrate 10 and thereafter selectively etching a remaining portion of the primary substrate 10 and the epitaxial buffer layer 20 with etching stopping at the etch selectivity layer 22, FIG. 9A, [0022].
The combination of Koch and Cheng discloses: removing the first handle substrate (Cheng: 10), without utilizing a release layer configured to enable separation of the compound semiconductor stack (Koch: stack 210 and 208) from the substrate (Cheng: 10, FIG. 9A, [0022]).
Cheng discloses that a method as taught for removal of the handle substrate without utilizing a release layer simplifies the manufacturing process [0022]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Koch and Yonehara’s method in order to simplify the manufacturing process as disclosed by Cheng [0022].
Regarding Claim 13, The combination of Koch, Yonehara, and Cheng discloses the method of claim 12.
Koch discloses: wherein the plurality of CS layers (active material stack 210 includes the constituent layers of OA device 110, including cladding layers, carrier confinement layers, and gain layer 212 and coupling layer 208, [0062]) includes a gain layer comprising a quantum element (gain layer 212 comprising a plurality of quantum dots), [0063].
Regarding Claim 14, The combination of Koch, Yonehara, and Cheng discloses method of claim 13.
Koch discloses: wherein the quantum element is a quantum dot (gain layer 212 comprising a plurality of quantum dots), [0063].
Regarding Claim 15 (Amended), The combination of Koch, Yonehara, and Cheng discloses the method of claim 12.
Koch discloses: further including processing the CS stack (first stack 210 and 208) to define a first optically active device (operation 303: patterning active material 210 to define the optically active device OA110, FIG. 3, [0071]) that is optically coupled with the first silicon waveguide (116), FIG. 2A-2E, [0082].
Regarding Claim 16 (Amended), The combination of Koch, Yonehara, and Cheng discloses the method of claim 15.
Koch discloses: wherein the CS stack (first stack 210 and 208) is processed to define the first optically active device as a laser (first optically active device OA 110 is a quantum-dot laser), [0062].
Regarding Claim 17 (Amended), The combination of Koch, Yonehara, and Cheng discloses the method of claim 15.
Koch discloses: wherein the CS chip (400) is provided such that it includes a second CS stack comprising a second plurality of CS layers (second stack 210 and 208 with plurality of CS layers), [0071].
Koch [0071] discloses the substrate having multiple active regions, each containing corresponding patterns of active material stack 210, indicating the CS chip includes a second CS stack comprising a second plurality of CS layers.
and wherein the process (method 300, FIG. 3, [0071]) further includes processing the second CS stack to define a second optically active device (operation 303: patterning 210 to define the shape of OA device 110, FIG. 3, [0071]) that is selected from the group consisting of a laser, an optical amplifier, an electro-absorption modulator, and a phase modulator (a laser, an optical amplifier, an electro-absorption modulator, and a phase modulator, [0062]).
Regarding Claim 18 (Amended), The combination of Koch, Yonehara, and Cheng discloses method of claim 17.
Koch discloses: wherein the host substrate (108) is provided such that the device layer (206) is patterned to define a second silicon waveguide (116), FIG. 2E, [0054].
and wherein the second CS stack (second stack 210 and 208) is processed such that the second optically active device (operation 303: patterning 210 to define the shape of OA device 110, FIG. 3, [0071]) is optically coupled with the second silicon waveguide (116), FIG. 2A-2E, [0082]. Koch [0082] discloses OA device 110 is optically coupled to silicon waveguide 116 via passive waveguide 114.
Regarding Claim 19 (Amended), The combination of Koch, Yonehara, and Cheng discloses the method of claim 12.
Koch discloses: wherein the CS stack (stack 210 and 208) and host substrate (108) are joined such that a first layer of the CS stack (208) is joined with the first silicon waveguide (116 formed in 206) at a bonding interface, FIG. 4B, [0054], [0067].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
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/Krishna J Palaniswamy/
Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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