DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/09/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species A, and Claims 1-10 and 12-19 in the reply filed on 01/26/2026 is acknowledged. Claims 11 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/26/2026.
Claim Objections
Claims 6 and 17-19 are objected to because of the following informalities:
Claim 6 recites “wherein the process further includes processing second CS stack”; this should be written as “wherein the process further includes processing the second CS stack.”
Claim 17 recites “wherein the process further includes processing second CS stack”; this should be written as “wherein the process further includes processing the second CS stack.”
Claim 18 recites “wherein host substrate is provided such that the device layer is patterned to define a second silicon waveguide”; this should be written as “wherein the host substrate is provided such that the device layer is patterned to define a second silicon waveguide.”
Claim 19 recites “wherein the CS stack and host substrate are joined such that a first layer of the CS stack is joined with the first waveguide at a bonding interface”; this should be written as “wherein the CS stack and the host substrate are joined such that a first layer of the CS stack is joined with the first silicon waveguide at a bonding interface.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15 -18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites the limitation " the first CS stack" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 9 and 12 - 19 are rejected under 35 U.S.C. 103 as being unpatentable over Koch et al. (US20210215874A1; hereinafter Koch) in view of Yonehara et al. (US20060166468A1; hereinafter Yonehara).
Regarding Claim 1, Koch discloses a method (method of forming an integrated-optics system, [0029]) including:
providing a compound-semiconductor (CS) chip (photonic substrate 400) that includes a first CS layer (208) disposed on a first handle substrate (sacrificial substrate 402) comprising a conventional gallium arsenide wafer in the depicted example, FIG. 4A reproduced below, [0058], [0059];
providing a host substrate (substrate 108) including a first layer (silicon device layer 206) that comprises a first material that is selected from the group consisting of a dielectric layer (buried oxide layer (BOX) 204) and an indirect-bandgap semiconductor (206 is a layer of single-crystal silicon an indirect-bandgap semiconductor), FIG. 2A, [0053];
joining the CS chip and the host substrate (CS chip 400 is flipped over and bonded to host substrate 108) such that the first CS layer (208) is between the host substrate (108) and the first handle substrate (402), FIG. 4B reproduced below, [0067];
and removing the first handle substrate (402), FIG. 4B, [0068].
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Koch: FIGS. 4A, 4B
Koch discloses the first CS layer 208 disposed on a first handle substrate 402 comprising a conventional gallium arsenide wafer (FIG. 4A, [0058], [0059]) but does not disclose “a first handle substrate comprising germanium.”
In a similar art, Yonehara discloses a semiconductor structure including semiconductor substrate constituting germanium, [0013].
Yonehara discloses: providing a compound-semiconductor (CS) chip (layered CS structure) that includes a first CS layer (layer 105) disposed on a first handle substrate (germanium substrate 101) comprising germanium, FIG. 11 reproduced below, [0050], [0051].
Yonehara [0013], [0050] discloses germanium substrate 101 on which the compound semiconductor stack is grown and later separated, indicating 101 functions as a handle substrate.
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Yonehara: FIG. 11
Yonehara discloses that a method as taught with repeated use of the germanium substrate significantly reduces a proportion of the substrate cost in the production cost [0062]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Koch’s method in order to reduce the production cost as disclosed by Yonehara [0062].
Regarding Claim 2, The combination of Koch and Yonehara discloses the method of claim 1.
Koch discloses: wherein the CS chip (400) includes a first CS stack (first stack 210 and 208) disposed on the first handle substrate (402), the first CS stack comprising a first plurality of CS layers (first stack 210 includes the constituent layers of OA device 110, including cladding layers, carrier confinement layers, and gain layer 212 and coupling layer 208, [0062]) that includes the first CS layer (208), FIG. 4A, [0058].
Koch [0071] discloses the substrate may include multiple active regions, each containing corresponding patterns of active material stack 210 disposed on coupling layer 208, indicating the CS chip includes a first CS stack comprising a first plurality of CS layers.
Regarding Claim 3, The combination of Koch and Yonehara discloses the method of claim 2.
Koch discloses: wherein the first plurality of CS layers (layers of the first active stack 210 and 208) includes a gain layer (212) comprising a quantum element (212 includes quantum-dot laser, quantum wells, quantum-well layers, quantum wires, quantum dashes, and the like), FIG. 4B, [0062], [0063].
Regarding Claim 4, The combination of Koch and Yonehara discloses the method of claim 2.
Koch discloses: wherein the method (method 300, FIG. 3, [0071]) further includes processing the first CS stack to form a first optically active device (operation 303: patterning 210 to define the shape of OA device 110, FIG. 3, [0071]) that is optically coupled with the first layer (206), FIG. 2A-2E, [0054], [0082].
Koch [0082] discloses OA device 110 is optically coupled to silicon waveguide 116 and [0054] discloses the silicon waveguide 116 is formed by patterning silicon device layer 206, indicating the OA device 110 is optically coupled to the waveguide 116 formed from the first layer 206.
Regarding Claim 5, The combination of Koch and Yonehara discloses the method of claim 4.
Koch discloses: wherein the first CS stack (first stack 210 and 208) is processed to define the first optically active device as a laser (210 includes constituent layers of optically active device 110 which is a quantum-dot laser), [0062].
Regarding Claim 6, The combination of Koch and Yonehara discloses the method of claim 4.
Koch discloses: wherein the CS chip (400) is provided such that it includes a second CS stack (second stack 210 with coupling layer 208) comprising a second plurality of CS layers (layers of the second stack 210 and 208), [0071].
Koch [0071] discloses the substrate may include multiple active regions, each containing corresponding patterns of active material stack 210 disposed on coupling layer 208, indicating the CS chip includes a second CS stack comprising a second plurality of CS layers.
and wherein the process (method 300, FIG. 3, [0071]) further includes processing second CS stack to define a second optically active device (operation 303, patterning stack 210 to define the shape of the second OA device 110, FIG. 3, [0071]) that is selected from the group consisting of a laser, an optical amplifier, an electro-absorption modulator, and a phase modulator (a laser, an optical amplifier, an electro-absorption modulator, and a phase modulator, [0062]).
Regarding Claim 7, The combination of Koch and Yonehara discloses the method of claim 4.
Koch discloses: wherein the CS chip (400) is provided such that it includes a second CS stack (second stack 210 and 208) comprising a second plurality of CS layers (layers of the second stack 210 and 208), [0071].
Koch [0071] discloses the substrate having multiple active regions, each containing corresponding patterns of active material stack 210, indicating the CS chip includes a second CS stack comprising a second plurality of CS layers.
and wherein the method (operation 300, FIG. 3, [0071]) further includes processing the second CS stack (second stack 210 and 208) to form a second optically active device (operation 303: patterning 210 to define the shape of OA device 110, FIG. 3, [0071]) that is optically coupled with the first layer (206), FIG. 2A-2E, [0054], [0082].
Koch [0082] discloses OA device 110 is optically coupled to silicon waveguide 116 and [0054] discloses the silicon waveguide 116 is formed by patterning silicon device layer 206, indicating the OA device 110 is optically coupled to the waveguide 116 formed from the first layer 206.
Regarding Claim 8, The combination of Koch and Yonehara discloses the method of claim 1.
Koch discloses: wherein the host substrate (108) is provided such that (1) the first layer comprises single-crystal silicon (first layer 206 is a layer of single-crystal silicon) and is disposed on a second handle substrate (202), [0053]
and (2) the first layer is patterned to define at least one silicon waveguide (the silicon waveguide 116 is formed by patterning first layer 206), FIG. 2E, [0054].
Regarding Claim 9, The combination of Koch and Yonehara discloses the method of claim 8.
Koch discloses: wherein the CS chip (400) is provided such that the first CS layer (208) comprises a compound semiconductor selected from the group consisting of gallium arsenide, indium phosphide, indium gallium arsenide, aluminum gallium arsenide, and indium gallium arsenide phosphide (208 comprises a compound semiconductor such as gallium arsenide, indium phosphide, indium gallium arsenide, indium gallium arsenide phosphide, and the like, [0059]).
Regarding Claim 12, Koch discloses a method (method of forming an integrated-optics system, [0029]) including:
providing a compound-semiconductor (CS) chip (photonic substrate 400) that includes a plurality of CS layers (active material stack 210 includes the constituent layers of OA device 110, including cladding layers, carrier confinement layers, and gain layer 212 and coupling layer 208, [0062]) that collectively define a CS stack (stack 210 and 208), the CS stack being disposed on a first handle substrate (sacrificial substrate 402) comprising a conventional gallium arsenide wafer in the depicted example, FIG. 4A, [0058], [0059].
providing a host substrate (substrate 108) that is a silicon-on-insulator substrate (108) including a silicon handle substrate (handle substrate 202 is a conventional silicon wafer), a buried oxide layer (204), and a device layer (206) that comprises single-crystal silicon (silicon device layer 206 is a layer of single-crystal silicon), [0053].
Koch [0053] discloses substrate 108 is a conventional silicon-on-insulator (SOI) substrate comprising handle substrate 202, buried oxide layer (BOX) 204, and silicon device layer 206.
wherein the device layer (206) is patterned to define a first silicon waveguide (116), [0054].
joining the CS chip and the host substrate (CS chip 400 is flipped over and bonded to host substrate 108) such that the CS stack (stack 210 and 208) is between the silicon handle substrate (202) and the first handle substrate (402), FIG. 4B, [0067];
and removing the first handle substrate (402), FIG. 4B, [0068].
Koch does not disclose “the CS stack being disposed on a first handle substrate consisting of germanium.”
In a similar art, Yonehara discloses a semiconductor structure including semiconductor substrate constituting germanium, [0013].
Yonehara discloses: providing a compound-semiconductor (CS) chip (layered CS structure) that includes a plurality of CS layers that collectively define a CS stack (layers 105, 106, 107, 108, and 109), the CS stack being disposed on a first handle substrate (germanium substrate 101) consisting of germanium, FIG. 11, [0050], [0051].
Yonehara [0013], [0050] discloses germanium substrate 101 on which the compound semiconductor stack is grown and later separated, indicating 101 functions as a handle substrate.
Yonehara discloses that a method as taught with repeated use of the germanium substrate significantly reduces a proportion of the substrate cost in the production cost [0062]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Koch’s method in order to reduce the production cost as disclosed by Yonehara [0062].
Regarding Claim 13, The combination of Koch and Yonehara discloses the method of claim 12.
Koch discloses: wherein the plurality of CS layers (active material stack 210 includes the constituent layers of OA device 110, including cladding layers, carrier confinement layers, and gain layer 212 and coupling layer 208, [0062]) includes a gain layer comprising a quantum element (gain layer 212 comprising a plurality of quantum dots), [0063].
Regarding Claim 14, The combination of Koch and Yonehara discloses method of claim 13.
Koch discloses: wherein the quantum element is a quantum dot (gain layer 212 comprising a plurality of quantum dots), [0063].
Regarding Claim 15, The combination of Koch and Yonehara discloses the method of claim 12.
Koch discloses: further including processing the first CS stack (first stack 210 and 208) to define a first optically active device (operation 303: patterning active material 210 to define the optically active device OA110, FIG. 3, [0071]) that is optically coupled with the first silicon waveguide (116), FIG. 2A-2E, [0082].
Regarding Claim 16, The combination of Koch and Yonehara discloses the method of claim 15.
Koch discloses: wherein the first CS stack (first stack 210 and 208) is processed to define the first optically active device as a laser (first optically active device OA 110 is a quantum-dot laser), [0062].
Regarding Claim 17, The combination of Koch and Yonehara discloses the method of claim 15.
Koch discloses: wherein the CS chip (400) is provided such that it includes a second CS stack comprising a second plurality of CS layers (second stack 210 and 208 with plurality of CS layers), [0071].
Koch [0071] discloses the substrate having multiple active regions, each containing corresponding patterns of active material stack 210, indicating the CS chip includes a second CS stack comprising a second plurality of CS layers.
and wherein the process (method 300, FIG. 3, [0071]) further includes processing second CS stack to define a second optically active device (operation 303: patterning 210 to define the shape of OA device 110, FIG. 3, [0071]) that is selected from the group consisting of a laser, an optical amplifier, an electro-absorption modulator, and a phase modulator (a laser, an optical amplifier, an electro-absorption modulator, and a phase modulator, [0062]).
Regarding Claim 18, The combination of Koch and Yonehara discloses method of claim 17.
Koch discloses: wherein the host substrate (108) is provided such that the device layer (206) is patterned to define a second silicon waveguide (116), FIG. 2E, [0054].
and wherein the second CS stack (second stack 210 and 208) is processed such that the second optically active device (operation 303: patterning 210 to define the shape of OA device 110, FIG. 3, [0071]) is optically coupled with the second silicon waveguide (116), FIG. 2A-2E, [0082]. Koch [0082] discloses OA device 110 is optically coupled to silicon waveguide 116 via passive waveguide 114.
Regarding Claim 19, The combination of Koch and Yonehara discloses the method of claim 12.
Koch discloses: wherein the CS stack (stack 210 and 208) and host substrate (108) are joined such that a first layer of the CS stack (208) is joined with the first waveguide (116 formed in 206) at a bonding interface, FIG. 4B, [0054], [0067].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Koch in view of Yonehara, further in view of Parker et al. (US20200162156A1; hereinafter Parker).
Regarding Claim 10, The combination of Koch and Yonehara discloses the method of claim 1.
Koch discloses: wherein the host substrate (108) is provided such that (1) the first layer (206) comprises single-crystal silicon and is disposed on a second handle substrate (202), and (2) the first layer (206) is patterned to define at least one waveguide (116), FIG. 2E, [0053], [0054].
The combination of Koch and Yonehara does not disclose “the first layer comprises silicon nitride.”
In a similar art, Parker discloses photonic integrated circuits [0001].
Parker discloses a semiconductor-on-insulator (SOI) substrate including a semiconductor device layer that may comprise silicon nitride disposed on top of an insulating layer [0016].
Parker discloses: the first layer (semiconductor device layer) comprises silicon nitride and is disposed on a second handle substrate (silicon substrate), [0016].
Parker discloses that a method as taught improves the vertical optical confinement of the device [0016]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Koch and Yonehara’s method in order to improve the vertical optical confinement as disclosed by Parker [0016].
Conclusion
Any inquiry concerning this communication or earlier communications from the
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899