DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/10/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-8 and 12-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claims 6 and 17 objected to because of the following informalities:
Claims 6 and 17 recite “wherein the process further includes processing the second CS stack”; this should be written as “wherein the method further includes processing the second CS stack.”
. Appropriate correction is required
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 8 and 12 - 19 are rejected under 35 U.S.C. 103 as being unpatentable over Koch et al. (US20210215874A1; hereinafter Koch) in view of McLaurin et al. (US20150140710A1; hereinafter McLaurin).
Regarding Claim 1, Koch discloses a method (method of forming an integrated-optics system, [0029]) including:
providing a compound-semiconductor (CS) chip (photonic substrate 400) that includes a CS stack (stack 210 and 208) comprising a first CS layer (208) disposed on a first handle substrate (sacrificial substrate 402) comprising a conventional gallium arsenide wafer in the depicted example, FIG. 4A reproduced below, [0058], [0059];
providing a host substrate (substrate 108) including a first layer (silicon device layer 206) that comprises a first material that is selected from the group consisting of a dielectric layer (buried oxide layer (BOX) 204) and an indirect-bandgap semiconductor (206 is a layer of single-crystal silicon an indirect-bandgap semiconductor), FIG. 2A, [0053];
joining the CS chip and the host substrate (CS chip 400 is flipped over and bonded to host substrate 108) such that the first CS layer (208) is between the host substrate (108) and the first handle substrate (402), FIG. 4B reproduced below, [0067];
and removing the first handle substrate (402), FIG. 4B, [0068].
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Koch: FIGS. 4A, 4B
Koch discloses the first CS layer 208 disposed on a first handle substrate 402 comprising a conventional gallium arsenide wafer (FIG. 4A, [0058], [0059]) but does not disclose “a first handle substrate comprising germanium.”
In a similar art, McLaurin discloses methods for fabricating semiconductor laser diodes [0058].
The combination of Koch and McLaurin discloses: providing a compound-semiconductor (CS) chip (Koch: photonic substrate 400) that includes a CS stack comprising a first CS layer disposed on a first handle substrate (Koch: CS stack 210 and 208 disposed on sacrificial substrate 402) comprising germanium (McLaurin: [0065], [0070], [0240]).
McLaurin FIG. 6, [0065] discloses a process flow for epitaxial preparation in which the compound semiconductor layers - cladding layers 101, active region 102, and p-GaN and p-side cladding 103 overlie the substrate 100. McLaurin FIG. 10b, [0070] discloses the compound semiconductor layers 101, 102, 103 are transferred from the substrate 100 to the carrier wafer 106. Therefore, the substrate 100 is interpreted as the handle substrate.
McLaurin [0240] further discloses the substrates may include germanium or gallium arsenide. It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize a first handle substrate comprising germanium, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Therefore, all the claimed limitations are considered met.
Regarding Claim 2, The combination of Koch and McLaurin discloses the method of claim 1.
Koch discloses: wherein the CS chip (400) includes a first CS stack (first stack 210 and 208) disposed on the first handle substrate (402), the first CS stack comprising a first plurality of CS layers (first stack 210 includes the constituent layers of OA device 110, including cladding layers, carrier confinement layers, and gain layer 212 and coupling layer 208, [0062]) that includes the first CS layer (208), FIG. 4A, [0058].
Koch [0071] discloses the substrate may include multiple active regions, each containing corresponding patterns of active material stack 210 disposed on coupling layer 208, indicating the CS chip includes a first CS stack comprising a first plurality of CS layers.
Regarding Claim 3, The combination of Koch and McLaurin discloses the method of claim 2.
Koch discloses: wherein the first plurality of CS layers (layers of the first active stack 210 and 208) includes a gain layer (212) comprising a quantum element (212 includes quantum-dot laser, quantum wells, quantum-well layers, quantum wires, quantum dashes, and the like), FIG. 4B, [0062], [0063].
Regarding Claim 4, The combination of Koch and McLaurin discloses the method of claim 2.
Koch discloses: wherein the method (method 300, FIG. 3, [0071]) further includes processing the first CS stack to form a first optically active device (operation 303: patterning 210 to define the shape of OA device 110, FIG. 3, [0071]) that is optically coupled with the first layer (206), FIG. 2A-2E, [0054], [0082].
Koch [0082] discloses OA device 110 is optically coupled to silicon waveguide 116 and [0054] discloses the silicon waveguide 116 is formed by patterning silicon device layer 206, indicating the OA device 110 is optically coupled to the waveguide 116 formed from the first layer 206.
Regarding Claim 5, The combination of Koch and McLaurin discloses the method of claim 4.
Koch discloses: wherein the first CS stack (first stack 210 and 208) is processed to define the first optically active device as a laser (210 includes constituent layers of optically active device 110 which is a quantum-dot laser), [0062].
Regarding Claim 6, The combination of Koch and McLaurin discloses the method of claim 4.
Koch discloses: wherein the CS chip (400) is provided such that it includes a second CS stack (second stack 210 with coupling layer 208) comprising a second plurality of CS layers (layers of the second stack 210 and 208), [0071].
Koch [0071] discloses the substrate may include multiple active regions, each containing corresponding patterns of active material stack 210 disposed on coupling layer 208, indicating the CS chip includes a second CS stack comprising a second plurality of CS layers.
and wherein the process (method 300, FIG. 3, [0071]) further includes processing a second CS stack (second stack 210 and 208) to define a second optically active device (operation 303, patterning stack 210 to define the shape of the second OA device 110, FIG. 3, [0071]) that is selected from the group consisting of a laser, an optical amplifier, an electro-absorption modulator, and a phase modulator (a laser, an optical amplifier, an electro-absorption modulator, and a phase modulator, [0062]).
Koch [0071] discloses the substrate having multiple active regions, each containing corresponding patterns of active material stack 210, indicating the CS chip includes a second CS stack comprising a second plurality of CS layers.
Regarding Claim 7, The combination of Koch and McLaurin discloses the method of claim 4.
Koch discloses: wherein the CS chip (400) is provided such that it includes a second CS stack (second stack 210 and 208) comprising a second plurality of CS layers (layers of the second stack 210 and 208), [0071].
Koch [0071] discloses the substrate having multiple active regions, each containing corresponding patterns of active material stack 210, indicating the CS chip includes a second CS stack comprising a second plurality of CS layers.
and wherein the method (operation 300, FIG. 3, [0071]) further includes processing the second CS stack (second stack 210 and 208) to form a second optically active device (operation 303: patterning 210 to define the shape of OA device 110, FIG. 3, [0071]) that is optically coupled with the first layer (206), FIG. 2A-2E, [0054], [0082].
Koch [0082] discloses OA device 110 is optically coupled to silicon waveguide 116 and [0054] discloses the silicon waveguide 116 is formed by patterning silicon device layer 206, indicating the OA device 110 is optically coupled to the waveguide 116 formed from the first layer 206.
Regarding Claim 8, The combination of Koch and McLaurin discloses the method of claim 1.
Koch discloses: wherein the host substrate (108) is provided such that (1) the first layer comprises single-crystal silicon (first layer 206 is a layer of single-crystal silicon) and is disposed on a second handle substrate (202), [0053]
and (2) the first layer is patterned to define at least one silicon waveguide (the silicon waveguide 116 is formed by patterning first layer 206), FIG. 2E, [0054].
Regarding Claim 12, Koch discloses a method (method of forming an integrated-optics system, [0029]) including:
providing a compound-semiconductor (CS) chip (photonic substrate 400) that includes a plurality of CS layers (active material stack 210 includes the constituent layers of OA device 110, including cladding layers, carrier confinement layers, and gain layer 212 and coupling layer 208, [0062]) that collectively define a CS stack (stack 210 and 208), the CS stack being disposed on a first handle substrate (sacrificial substrate 402) consisting a conventional gallium arsenide wafer in the depicted example, FIG. 4A, [0058], [0059].
providing a host substrate (substrate 108) that is a silicon-on-insulator substrate (108) including a silicon handle substrate (handle substrate 202 is a conventional silicon wafer), a buried oxide layer (204), and a device layer (206) that comprises single-crystal silicon (silicon device layer 206 is a layer of single-crystal silicon), [0053].
Koch [0053] discloses substrate 108 is a conventional silicon-on-insulator (SOI) substrate comprising handle substrate 202, buried oxide layer (BOX) 204, and silicon device layer 206.
wherein the device layer (206) is patterned to define a first silicon waveguide (116), [0054].
joining the CS chip and the host substrate (CS chip 400 is flipped over and bonded to host substrate 108) such that the CS stack (stack 210 and 208) is between the silicon handle substrate (202) and the first handle substrate (402), FIG. 4B, [0067];
and removing the first handle substrate (402), FIG. 4B, [0068].
Koch discloses the first CS layer 208 disposed on a first handle substrate 402 consisting a conventional gallium arsenide wafer (FIG. 4A, [0058], [0059]) but does not disclose “a first handle substrate consisting of germanium.”
In a similar art, McLaurin discloses methods for fabricating semiconductor laser diodes [0058].
The combination of Koch and McLaurin discloses: providing a compound-semiconductor (CS) chip (Koch: photonic substrate 400) that includes a plurality of CS layers (Koch: photonic substrate 400 including active material stack 210 includes the constituent layers of OA device 110, including cladding layers, carrier confinement layers, and gain layer 212 and coupling layer 208, [0062]) that collectively define a CS stack, the CS stack being disposed on a first handle substrate (Koch: CS stack 210 and 208 disposed on sacrificial substrate 402) consisting of germanium (McLaurin, [0065], [0070], [0240]).
McLaurin FIG. 6, [0065] discloses a process flow for epitaxial preparation in which the compound semiconductor layers - cladding layers 101, active region 102, and p-GaN and p-side cladding 103 overlie substrate 100. McLaurin FIG. 10b, [0070] discloses the compound semiconductor layers 101, 102, 103 are transferred from the substrate 100 to the carrier wafer 106. Therefore, the substrate 100 is interpreted as the handle substrate.
McLaurin [0240] further discloses the substrates may include germanium or gallium arsenide. It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize a first handle substrate consisting of germanium, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Therefore, all the claimed limitations are considered met.
Regarding Claim 13, The combination of Koch and McLaurin discloses the method of claim 12.
Koch discloses: wherein the plurality of CS layers (active material stack 210 includes the constituent layers of OA device 110, including cladding layers, carrier confinement layers, and gain layer 212 and coupling layer 208, [0062]) includes a gain layer comprising a quantum element (gain layer 212 comprising a plurality of quantum dots), [0063].
Regarding Claim 14, The combination of Koch and McLaurin discloses method of claim 13.
Koch discloses: wherein the quantum element is a quantum dot (gain layer 212 comprising a plurality of quantum dots), [0063].
Regarding Claim 15, The combination of Koch and McLaurin discloses the method of claim 12.
Koch discloses: further including processing the CS stack (first stack 210 and 208) to define a first optically active device (operation 303: patterning active material 210 to define the optically active device OA110, FIG. 3, [0071]) that is optically coupled with the first silicon waveguide (116), FIG. 2A-2E, [0082].
Regarding Claim 16, The combination of Koch and McLaurin discloses the method of claim 15.
Koch discloses: wherein the CS stack (first stack 210 and 208) is processed to define the first optically active device as a laser (first optically active device OA 110 is a quantum-dot laser), [0062].
Regarding Claim 17, The combination of Koch and McLaurin discloses the method of claim 15.
Koch discloses: wherein the CS chip (400) is provided such that it includes a second CS stack comprising a second plurality of CS layers (second stack 210 and 208 with plurality of CS layers), [0071].
Koch [0071] discloses the substrate having multiple active regions, each containing corresponding patterns of active material stack 210, indicating the CS chip includes a second CS stack comprising a second plurality of CS layers.
and wherein the process (method 300, FIG. 3, [0071]) further includes processing the second CS stack to define a second optically active device (operation 303: patterning 210 to define the shape of OA device 110, FIG. 3, [0071]) that is selected from the group consisting of a laser, an optical amplifier, an electro-absorption modulator, and a phase modulator (a laser, an optical amplifier, an electro-absorption modulator, and a phase modulator, [0062]).
Regarding Claim 18, The combination of Koch and McLaurin discloses method of claim 17.
Koch discloses: wherein the host substrate (108) is provided such that the device layer (206) is patterned to define a second silicon waveguide (116), FIG. 2E, [0054].
and wherein the second CS stack (second stack 210 and 208) is processed such that the second optically active device (operation 303: patterning 210 to define the shape of OA device 110, FIG. 3, [0071]) is optically coupled with the second silicon waveguide (116), FIG. 2A-2E, [0082]. Koch [0082] discloses OA device 110 is optically coupled to silicon waveguide 116 via passive waveguide 114.
Regarding Claim 19, The combination of Koch and McLaurin discloses the method of claim 12.
Koch discloses: wherein the CS stack (stack 210 and 208) and host substrate (108) are joined such that a first layer of the CS stack (208) is joined with the first silicon waveguide (116 formed in 206) at a bonding interface, FIG. 4B, [0054], [0067].
Conclusion
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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