DETAILED ACTION
This application, 18/232,510 attorney docket P201911703US02, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to IBM, is a Divisional of 17/477,532, filed 09/17/2021, now U.S. Patent # 11764298. Claims 1-10 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Specification
The disclosure is objected to because of the following informalities: paragraph [0001] has a typographical error: VVFET instead of VTFET.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement. The claims contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
The method claimed requires forming the buried power rail before forming the buried oxide (BOX) and transistors, but the disclosure and drawings only support forming the power rail (as shown as 132 in figure 15A [0101]) after the BOX and transistors are completed, and the support substrate is removed from the backside of the BOX. Examiner notes that paragraph [0007] of the specification describes a structure, not the method of forming the structure and cannot be used to support enablement of a method. One skilled is a semiconductor process engineer who designs a process sequence for manufacturing VFET devices. The method requires forming a metal/conductive layer before forming the device and it is not clear how the metals will survive the process of forming and diffusing the semiconductor regions.
Allowable Subject Matter
Claims 1-10 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(a) set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach or make obvious the method of claim 1 which includes forming a buried power rail and forming a BOX on the power rail, then forming VTFETs over the BOX.
Claims 2-10 depend from claim 1 and include the same novel feature.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. 2019/0280120 to Kim et al. teaches forming a VFET, but forms the back contact after the device is formed.
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/JOHN A BODNAR/ Primary Examiner, Art Unit 2893