DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 12 and 19 have been amended; claims 13-15 and 20 have been cancelled; claims 21-24 have been newly added; and claims 1-12, 16-18, and 21-24 are currently pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites “separating each of the plurality of gate structures into a respective set of discrete segments.” Claim 22 recites that this separating step “includes forming gaps to cut the plurality of dummy gate structures each into gate segments.” Under claim 21, however, the plurality gate structures replace the plurality of dummy gate structures. It is therefore unclear how the separating of “the plurality of gate structures” is performed by cutting the dummy gate structures, which are not the claimed gate structures and are subsequently removed. Further, it is unclear whether the “gate segments” of claim 22 are the same as, or different from, the “discrete
segments” and the “first segment” and “second segment” of claim 19. For the purpose of
examination, claim 22 is interpreted as requiring that gaps are formed to cut each of the dummy
gate structures into dummy gate segments, and that the discrete segments of the gate structures
correspond to the dummy gate segments they replace.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al.
(US 2009/0053899 A1, hereinafter “Liu”) in view of Torii (US 20110101462 A1,
hereinafter “Torii”) and Liaw (US 2011/0069527 A1 hereinafter “Liaw”).
In regards to claim 19, Liu discloses (See, for example, annotated Fig. 1 included below) a
method for fabricating memory devices, comprising: forming a plurality of active regions (110)
parallel with one another, wherein the plurality of active regions (110) extend along a first lateral
direction (1st); forming a plurality of gate structures (120) parallel with one another,
wherein the plurality of gate structures (120) extend along a second lateral direction (2nd)
perpendicular to the first lateral direction (1st), wherein each of the plurality of gate structures
(120) overlays the plurality of active regions (110); and
separating (via, for example, GAP1 and GAP2) each of the plurality of gate structures
into a respective set of discrete segments (for example, 1001A, 1002B…);
wherein at least a first one of the plurality of gate structures (1001) comprises a first
segment (1001A), and at least a second one of the plurality of gate structures (1002”), disposed
adjacent the first gate structure (1001), comprises a second segment (1002B);
wherein the first segment (1001A) is shifted away from the second segment (1002B)
along the second lateral direction (2nd); and
wherein a number of the first subset of transistors (See, for example, transistors in
active regions 12a, 12b, 12e and 12f) is equal to a number of the second subset of transistors
(See, for example, transistors in active regions 12c, 12d, 12g and 12h).
Liu is silent about the first segment and the second segment have the same length; and wherein a first subset of the plurality of transistors have a first threshold voltage, and a second subset of the plurality of transistors have a second threshold voltage different from the first threshold voltage
Torii discloses (See, for example, Figs. 1-3) the first segment (20a, on 12a) and the second segment (20a, on 12c) have the same length (same channel length, See, for example, Fig. 3); and wherein a first subset of the plurality of transistors (See, for example, 34) have a first threshold voltage, and a second subset of the plurality of transistors (see, for example, 36) have a second threshold voltage different from the first threshold voltage (PMPOS and NMOS ).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Liu by Torii because this would help improve carrier mobility so that the ON-current of the transistor is improved.
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Liu as modified above further fails to explicitly teach that wherein an intersection of the at least one of the plurality of active regions and a corresponding one of the plurality of gate structures operatively form a Read-Only-Memory (ROM) cell.
Liaw while disclosing a ROM cell teaches (See, for example, Fig. 2) an intersection of the at least one of the plurality of active regions (116) and a corresponding one of the plurality of gate structures (word line gate 104) operatively form a Read-Only-Memory (ROM) cell (See, for example, Par [0021]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Liu by Liaw because Liaw explicitly recognizes
that managing the layout-dependent effects on gate structures in ROM arrays including the poly pacing effect (PSE), STI stress effects, and OD extension-induced threshold voltage variations is critical for achieving device matching and reliable ROM operation
In regards to claim 23, Liu as modified by Torii and Liaw teaches (See, for example, Fig. 2, Liaw) that forming interconnect structures (source contacts 111, drain contacts 110, M1 lines 106/112, vias 108a/108b) between the plurality of gate structures (104).
Claims 21-22 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Torii and Liaw as applied to claim 19 above, and further in view of Xie et al. (US 2018/0342427 A1, hereinafter “Xie”).
In regards to claims 21, 22 and 24, Liu as modified above discloses all limitations of claim 19 except that
wherein forming the plurality of gate structures includes forming a plurality of dummy gate structures traversing the plurality of active regions and replacing the plurality of dummy gate structures with the plurality of gate structures (claim 21);
wherein separating each of the plurality of gate structures into a respective set of discrete segments includes forming gaps to cut the plurality of dummy gate structures each into gate segments (claim 22); and
wherein forming a plurality of active regions includes forming channel layers and sacrificial layers alternatively stacked on one another (claim 24).
Xie while disclosing integrated circuit design teaches (See, for example, Figs. 3A-3C and 5)
wherein forming the plurality of gate structures (dummy gates 122) includes forming a plurality
of dummy gate structures traversing the plurality of active regions (nanosheet stacks 104, See
Par [0051]) and replacing the plurality of dummy gate structures (122) with the plurality of gate
structures (high-k layer 130, work function metals 132/154, gate metal 156, See Pars [0066], [0060])(claim 21);
wherein separating each of the plurality of gate structures into a respective set of discrete
segments includes forming gaps to cut the plurality of dummy gate structures (122) each into gate segments (nanosheet stacks 104, gate cut isolation regions 128, See also Par [0091]) (claim 22); and
wherein forming a plurality of active regions (104) includes forming channel layers (nanosheet 118) and sacrificial layers (120) alternatively stacked on one another (See, Par [0052]) (claim 24).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Liu as modified by Torii and Liaw by Xie because forming nanosheet gate-all-around transistors by a replacement metal gate process to improve the operating speed of the FETS, and to increase the density of FETs on an integrated circuit (IC).
Allowable Subject Matter
Claims 1-12, and 16-18 are allowed over the prior arts of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
