Listed by the USPTO as WOLDEGEORGIS, ERMIAS T
Tech Center 2800 • Art Units: 2821 2893
This examiner grants 71% of resolved cases
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18660335 | SEMICONDUCTOR DEVICES INCLUDING CAPACITORS | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18391835 | SEMICONDUCTOR DEVICE INCLUDING SPACER STRUCTURE HAVING AIR GAP | Final Rejection | Samsung Electronics Co., Ltd. |
| 18505412 | HEAT DISSIPATION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18450836 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF | Final Rejection | Samsung Electronics Co., Ltd. |
| 18138339 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME | Final Rejection | SAMSUNG ELECTRONICS CO., LTD. |
| 18631472 | Organic electroluminescent device | Final Rejection | The Regents of the University of Michigan |
| 18243462 | ORGANIC LIGHT EMITTING DIODE AND ORGANIC LIGHT EMITTING DEVICE | Final Rejection | LG Display Co., Ltd. |
| 18020494 | DISPLAY DEVICE | Final Rejection | LG Display Co., Ltd. |
| 18762142 | METHOD OF MANUFACTURING DISPLAY DEVICE AND DISPLAY DEVICE | Non-Final OA | Samsung Display Co., LTD. |
| 18663696 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME | Non-Final OA | Samsung Display Co., LTD. |
| 18628716 | DISPLAY DEVICE AND METHOD FOR FABRICATION THEREOF | Non-Final OA | Samsung Display Co., LTD. |
| 18582115 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME | Non-Final OA | Samsung Display Co., LTD. |
| 18533509 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE | Final Rejection | Samsung Display Co., Ltd. |
| 18496918 | DISPLAY DEVICE | Final Rejection | Samsung Display Co., LTD. |
| 18483459 | ORGANIC PHOTODETECTOR AND ELECTRONIC APPARATUS INCLUDING THE SAME | Non-Final OA | Samsung Display Co., Ltd. |
| 18806900 | SOLID-STATE IMAGING ELEMENT AND ELECTRONIC EQUIPMENT | Non-Final OA | SONY SEMICONDUCTOR SOLUTIONS CORPORATION |
| 18552067 | DISPLAY PANEL AND DISPLAY APPARATUS | Final Rejection | BOE TECHNOLOGY GROUP CO., LTD. |
| 18029883 | TO-BE-EVAPORATED SUBSTRATES, DISPLAY SUBSTRATES AND MANUFACTURING METHODS THEREOF | Final Rejection | BOE Technology Group Co., Ltd. |
| 18089491 | LIQUID METAL WELLS FOR INTERCONNECT ARCHITECTURES | Non-Final OA | Intel Corporation |
| 18071257 | SHAPE MEMORY POLYMER (SMP) GLASS CORE PACKAGE FOR MODULATING WARPAGE | Final Rejection | Intel Corporation |
| 18013749 | EXCLUSION RING FOR SUBSTRATE PROCESSING | Final Rejection | Lam Research Corporation |
| 17826776 | MEMORY DEVICE INCLUDING CONTACT STRUCTURES HAVING MULTI-LAYER DIELECTRIC LINER | Final Rejection | Micron Technology, Inc. |
| 18639503 | SEMICONDUCTOR MEMORY DEVICE | Non-Final OA | Kioxia Corporation |
| 18632485 | ACOUSTIC DEVICE AND MODULE INCLUDING THE SAME | Non-Final OA | Murata Manufacturing Co., Ltd. |
| 18609318 | OPTICAL MODULE AND FLEXIBLE SUBSTRATE | Final Rejection | SUMITOMO ELECTRIC INDUSTRIES, LTD. |
| 18651018 | FABRICATION METHOD FOR FORMING HIGH VOLTAGE RESISTOR NETWORKS OVER SILICON SUBSTRATES FOR USE WITHIN MULTICHIP MODULE ASSEMBLIES | Non-Final OA | Texas Instruments Incorporated |
| 18381269 | SUBSTRATE STAGE, SUBSTRATE PROCESSING APPARATUS, AND TEMPERATURE CONTROL METHOD | Final Rejection | Tokyo Electron Limited |
| 18632599 | SCALED STACKED FET USING COMBINED STRUCTURES IN ADJACENT CELLS | Non-Final OA | INTERNATIONAL BUSINESS MACHINES CORPORATION |
| 18610646 | FORMING METAL LINE AND VIA STRUCTURE | Final Rejection | INTERNATIONAL BUSINESS MACHINES CORPORATION |
| 18091968 | BACKSIDE-CONNECTING VIA WITH NANOSHEET SPACERS FOR TRANSISTORS | Final Rejection | INTERNATIONAL BUSINESS MACHINES CORPORATION |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy70.9% of resolved applications examined by Ermias T Woldegeorgis were allowed (766 resolved cases), compared with 89.3% across Art Unit 2821 over the last five years.
This examiner's interview lift is +12.1 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Ermias T Woldegeorgis took 1,058 days on average from filing to allowance.
Ermias T Woldegeorgis examines applications in Art Unit 2821 in Tech Center 2800 (Semiconductors, Circuits & Optics).
