DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/19/2026 has been entered.
Claims 9-22 and 30-32 are pending. Claims 1-8 and 23-29 have been canceled. Claims 9, 13, 15, 18, 19, and 30-32 have been amended.
Election/Restrictions
Applicant’s election without traverse of invention Group II and Species A (FIG. 9) in the reply filed on 11/28/2025 is acknowledged.
Claim 30 reciting “the low-potential voltage line is disposed on the same layer as the source electrode and the drain electrode” pertains to a feature of non-elected Species B as shown in FIG. 10. The low-potential voltage line VL2 is disposed on the same layer as the source electrode SE and the drain electrode DE in FIG. 10. However, in the elected species show in FIG. 9, the high-potential voltage line VL1 is disposed on the same layer as the source electrode SE and the drain electrode DE.
Therefore, claim 30 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/28/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-13, 15-22, and 31-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (WO 2023/0352643 A1; corresponding US document US 2023/0352643 A1 is cited below for translation purposes; herein after Cho), in view of Jean et al. US 2021/0367102 A1 (Jean) and Hong et al. US 2023/0032600 A1 (Hong).
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In re claim 9, Cho discloses (e.g. FIGs. 10-16) a display device 2000 comprising:
a substrate 2010;
a buffer layer 2030 disposed on the substrate;
a power line 2020 (¶ 119) disposed on the substrate;
a first connection electrode 2080 (first wiring electrode, see FIG. 11, ¶ 147) and a second connection electrode (second wiring electrode not shown, ¶ 149) disposed over the substrate; and
a light-emitting element 2050 including (see FIGs. 15-16) a first electrode 2055 connected to the first connection electrode 2080 (¶ 147) and a second electrode 2051 connected to the second connection electrode (second wiring electrode, not shown, electrically connected to electrode 2051, ¶ 149),
wherein the light-emitting element 2050 includes (FIGs. 15-16):
an undoped semiconductor layer 2056 (¶ 133) including a first inner side surface (inner side surface exposed in recess 2050R) and a first outer side surface (exterior side surface of 2050);
a first semiconductor layer 2054 disposed on the undoped semiconductor layer 2056;
a light-emitting layer 2053 disposed on the first semiconductor layer 2054; and
a second semiconductor layer 2052 disposed on the light-emitting layer 2053.
Cho discloses the light emitting diode 2050 include a recess 2050R formed through the undoped semiconductor layer 2056.
Cho does not explicitly disclose a superlattice layer disposed on the undoped semiconductor layer 2056, the superlattice layer including a second inner side surface and a second outer side surface.
Jean discloses a display device (FIGs. 7-8) comprising a light emitting element LS including (FIG. 3) an undoped semiconductor layer 18 and a superlattice layer (superlattice structure 19 between BS and 15, not shown, ¶ 56; or superlattice DS formed by alternating layers 12/13 in FIG. 4), a trench T reaching layer the n-type layer 15 (¶ 83) and penetrating the superlattice layer and the undoped semiconductor layer 18, a first semiconductor layer 15 disposed on the superlattice layer; a light-emitting layer 16 disposed on the first semiconductor layer; and a second semiconductor layer 17 disposed on the light-emitting layer.
Jean discloses the superlattice layer is provided to adjust stress and reduce crystal defects in the device (¶ 56).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form a superlattice layer between Cho’s undoped layer 2056 and the first conductivity type layer 2054 to mitigate stress and reduce defects as taught by Jean, and forming the recess 2050R to penetrate through the superlattice layer to expose the first conductivity type layer 2054 for electrical contact access. As such, the superlattice layer includes a second inner side surface (inner side surface exposed by recess 2050R reaching layer 2054) and a second outer side surface (exterior side surface of 2050);
Cho discloses the display can be an active matrix display including pixel cells 2040 separated by partition wall 2060 (¶ 113), and including the first connection electrode 2080 connected to the first electrode 2055 of the light emitting diode and the second connection electrode connected to the second electrode 2051 of the light-emitting diode (¶ 147,149).
Cho does not explicitly disclose the details of the active matrix driving circuit including a driving transistor disposed on the buffer layer, wherein the driving transistor comprises: an active layer disposed over the buffer layer; a gate insulating layer disposed over the active layer; a gate electrode disposed on the gate insulating layer; a source electrode and a drain electrode disposed over the gate electrode; and a plurality of insulating layers disposed between the gate electrode and each of the source electrode and the drain electrode, wherein the first connection electrode is electrically connected to at least one of the source electrode and the drain electrode, and wherein the second connection electrode is electrically connected to the power line.
Hong discloses (e.g. FIG. 8) a display device comprising:
a substrate 11;
a buffer layer 12 disposed on the substrate 11;
a power line VDL1 disposed on the substrate 11;
a driving transistor T1 (¶ 76) disposed on the buffer layer 12,
wherein the driving transistor T1 comprises:
an active layer ACT1 disposed over the buffer layer 12;
a gate insulating layer 13 disposed over the active layer ACT1;
a gate electrode G1 disposed on the gate insulating layer 13;
a source electrode S1 and a drain electrode D1 disposed over the gate electrode G1; and
a plurality of insulating layers 15 (stacked structure, ¶ 117) disposed between the gate electrode G1 and each of the source electrode S1 and the drain electrode D1,
a first connection electrode 21 and a second connection electrode 22 disposed over the substrate; and
a light-emitting element 30 including a first electrode 26 connected to the first connection electrode 21 and a second electrode 17 connected to the second connection electrode 22,
wherein the first connection electrode 21 is electrically connected to at least one of the source electrode S1 and the drain electrode D1 (¶ 135), and
wherein the second connection electrode 22 is electrically connected to the power line VDL1 (directly or indirectly electrically connected through light-emitting diode EL and transistor T1).
Hong discloses the driving transistor T1 provides driving current to the light-emitting diode (¶ 76).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Cho’s active matrix display by including driving transistors to control driving signal to the light-emitting diode as taught by Hong.
In re claim 10, Jean discloses (e.g. FIGs. 3-4 & 7-8) wherein the first inner side surface of the undoped semiconductor layer 18 is flush with the second inner side surface of the superlattice layer (DS in FIG. 4 or superlattice structure between BS and 15, not shown, ¶ 56). The trench T is formed by etching through the layers until layer 15 is exposed. Therefore, the inner side surfaces the overlying layers formed by the trench are flush.
In re claim 11, Cho discloses (e.g. FIGs. 15-16) wherein the light-emitting element further includes a protective layer 2057+2058, wherein the protective layer 2057+2058 is disposed on at least the first inner side surface of the undoped semiconductor layer 2056, the second inner side surface of the superlattice layer (superlattice taught by Jean, wherein the recess is formed to extend through the superlattice layer to expose layer 2054), outer side surfaces of the light-emitting element 2050, and on a bottom surface of the undoped semiconductor layer 2056.
Jean discloses (e.g. FIGs. 8A-8B) wherein the light-emitting element further includes a protective layer (including 132 and 176,178), wherein the protective layer is disposed on at least the first inner side surface of the undoped semiconductor layer 18 (since trench is formed to extend through the layer to expose layer 15), the second inner side surface of the superlattice layer (since trench is formed to extend through the layer to expose layer 15), outer side surfaces of the light-emitting element LS, and on a bottom surface of the undoped semiconductor layer (protection layer 132 or 176,178 is disposed on a bottom surface of layer 18).
In re claim 12, Cho discloses (e.g. FIGs. 15-16) wherein the first semiconductor layer 2054 is in direct contact with the first electrode 2055, and the second semiconductor layer 2052 is in direct contact with the second electrode 2051.
Jean discloses (e.g. FIGs. 7-8) wherein the first semiconductor layer 15 is in direct contact with the first electrode 142A, and the second semiconductor layer 17 is in direct contact with the second electrode 142B.
In re claim 13, Cho discloses a planarization layer (¶ 126).
Hong discloses (e.g. FIG. 8) a first planarization layer 19 disposed on the driving transistor (¶ 129).
In re claim 15, Hong discloses (e.g. FIG. 4) wherein the active layer ACT1 of the driving transistor T1 includes an oxide semiconductor layer or a polysilicon semiconductor layer (¶ 109).
In re claim 16, Cho discloses (e.g. FIGs. 10 & 15-16), the light-emitting element 2050 is a micro-LED having a width that is less than or equal to 100 µm (¶ 3).
Jean discloses the light-emitting element is a micro-LED. In particular, Jean discloses (¶ 66) thickness of device 100 is tens to hundreds µm, which is ≤ 1/10 LX. As such, LX can hundreds to thousands µm. For a row of 8 pixels as shown in FIG. 5, each pixel has a width in x-direction that is about 12.5-125 µm. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to that the width of light-emitting element within each pixels would have a width that is less than about 12.5-125 µm.
As such, the claimed micro-LED having a width that is less than or equal to about 100 µm would be obvious over Cho and Jean. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 17, Cho discloses (e.g. FIGs. 15-16) wherein each of the first electrode 2055 and the second electrode 2051 includes one or more layers made of at least one of ITO, Mo, Al, Cu, Ni, Ti, Au, W, Pt, Ir, or Cr or an alloy thereof (¶ 134,142).
Jean discloses (e.g. FIGs. 7-8) wherein each of the first electrode 142A and the second electrode 142B includes one or more layers made of at least one of ITO, Mo, Al, Cu, Ni, Ti, Au, W, Pt, Ir, or Cr or an alloy thereof (¶ 69).
In re claim 18, Hong discloses (e.g. FIGs. 2-9) wherein the power line VDL1 is a high-potential voltage line VDL1 (¶ 89) disposed on the substrate 11, and wherein the display device further comprises a low-potential voltage line VSL1 (¶ 89) disposed on the substrate 11.
In re claim 19, Hong discloses (e.g. FIGs. 2) further comprising:
a plurality of auxiliary high-potential voltage lines VIL connected to (directly or indirectly) and intersecting a plurality of high-potential voltage lines VDL (¶ 89), the plurality of high-potential voltage lines VDL including the high-potential voltage line VDL1, to form a mesh structure; and
an auxiliary low-potential voltage line (another one of VIL) connected to (directly or indirectly) a plurality of low-potential voltage lines VSL (¶ 89), the plurality of low-potential voltage lines VSL including the low-potential voltage lines VSL1.
In re claim 20, Jean disclose the superlattice layer is formed between layers 15 and BS (¶ 56) and may either be above or below the undoped semiconductor layer 18. As such, the height from the superlattice layer to the light emitting layer 16 is at most the combined thickness of layers 19+15+18. Jean does not explicitly disclose the height from the superlattice layer to the light-emitting layer 16 relative to a width of the undoped semiconductor layer 18. However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Jean’s light-emitting element such that a height from the superlattice layer that is formed between layers 15 and BS to the light-emitting layer 16 is smaller than a width of the undoped semiconductor layer 18. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 21, Cho discloses (e.g. FIGs. 12-16) wherein a recess 2050R is formed in the undoped semiconductor layer 2056, and the recess 2050R exposes a portion of a surface of the first semiconductor layer 2054.
Jean discloses (e.g. FIGs. 7-8) wherein a recess T (which penetrates through layers to reach layer 15) is formed in the undoped semiconductor layer 18 and the superlattice layer (formed between BS and layer 15, ¶ 56), and the recess T exposes a portion of a surface of the first semiconductor layer 15.
In re claim 22, Cho discloses (e.g. FIGs. 15-16) wherein the undoped semiconductor layer 2056, the superlattice layer (formed between 2056 and 2054 as taught by Jean), the first semiconductor layer 2054, the light-emitting layer 2053, and the second semiconductor layer 2052 are stacked sequentially.
Jean discloses (e.g. FIG. 3) wherein the undoped semiconductor layer 18, the superlattice layer (formed between BS and layer 15, ¶ 56), the first semiconductor layer 15, the light-emitting layer 16, and the second semiconductor layer 17 are stacked sequentially. The layers maybe sequentially stacked in any order.
In re claim 31, Hong discloses (e.g. FIG. 2) wherein the high-potential voltage line VDL1 is electrically connected to a high-potential voltage pad WPD_VDD (¶ 70) disposed in a first pad area of the substrate (an area of pad WPD_VDD), and
wherein the low-potential voltage line VSL1 is electrically connected to a low-potential voltage pad WPD_VSS (¶ 70) disposed in a second pad area of the substrate (an area of pad WPD_VSS).
In re claim 32, Hong discloses (e.g. FIG. 2) further comprising:
a data pad WPD_DT electrically connected to a data line DTL disposed on the substrate (¶ 70);
a gate pad (an end connection of a scan line SCL) electrically connected to a gate driver SDR disposed on the substrate (¶ 67); and
a reference voltage pad (another one of WPD_VSS) electrically connected to a reference voltage line (another one of VSL, e.g. VSL2) disposed on the substrate.
No specific “reference voltage pad” or “reference voltage line” has been claimed that would distinguish over pad WPD_VSS and a voltage line VSL.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Cho, Jean, and Hong as applied to claim 9 above, and further in view of Seo et al. US 2022/0352268 A1 (Seo).
In re claim 14, Cho discloses the display can be an active matrix display including pixel cells 2040 separated by partition wall 2060 (¶ 113), and including the first connection electrode 2080 connected to the first electrode 2055 of the light emitting diode 2050 and the second connection electrode connected to the second electrode 2051 of the light-emitting diode 2050 (¶ 147,149).
Cho does not explicitly disclose a second planarization layer disposed between the first connection electrode and the second connection electrode, the second planarization layer surrounding an outer side surface of the light-emitting element.
However, Seo discloses an active matrix driving circuit including a driving transistor T1-T3, a first planarization layer 130 disposed on the driving transistor T1-T3, light-emitting elements EL connected between a first connection electrode PE and a second connection electrode CE, the second planarization layer PLL surrounding an outer side surface of the light-emitting element LE. Seo discloses forming the second planarization layer PLL to planarize the top surface of the display (¶ 131-132).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Cho’s light-emitting diode 2050 between the first connection electrode and the second connection electrode, and provide a second planarization layer between the first connection electrode and the second connection electrode to provide a planarized display surface as taught by Seo.
Response to Arguments
Applicant’s arguments with respect to claim(s) 9-22 and 31-32 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights