DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention Group II and Species A (FIG. 9), encompassing claims 9-22, in the reply filed on 11/28/2025 is acknowledged.
Claims 1-8 and 23-29 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/28/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9-12, 17-19, and 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jean et al. US 2021/0367102 A1 (Jean).
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In re claim 9, Jean discloses (e.g. FIGs. 3-8) a display device (no specific “display device” claimed that would structurally distinguish over any of the device displaying light as taught by Jean) comprising:
a first connection electrode 144A and a second connection electrode 144B disposed on a substrate 154; and
a light-emitting element LS including a first electrode 142A connected to the first connection electrode 144A and a second electrode 142B connected to the second connection electrode 144B,
wherein the light-emitting element LS includes:
a undoped semiconductor layer 18 (e.g. FIG. 3, ¶ 55) including a first inner side surface (inner side surface exposed by trench T reaching layer 15, ¶ 83) and a first outer side surface (exterior side surface of LS);
a superlattice layer (superlattice structure 19 between BS and 15, not shown, ¶ 56; or superlattice DS formed by alternating layers 12/13 in FIG. 4) disposed on the undoped semiconductor layer 18, the superlattice layer including a second inner side surface (inner side surface exposed by trench T reaching layer 15, ¶ 83) and a second outer side surface (exterior side surface of LS);
a first semiconductor layer 15 disposed on the superlattice layer;
a light-emitting layer 16 disposed on the first semiconductor layer; and
a second semiconductor layer 17 disposed on the light-emitting layer.
In re claim 10, Jean discloses (e.g. FIGs. 3-4 & 7-8) wherein the first inner side surface of the undoped semiconductor layer 18 is flush with the second inner side surface of the superlattice layer (DS in FIG. 4 or superlattice structure between BS and 15, not shown, ¶ 56). The trench T is formed by etching through the layers until layer 15 is exposed. Therefore, the inner side surfaces the overlying layers formed by the trench are flush.
In re claim 11, Jean discloses (e.g. FIGs. 8A-8B) wherein the light-emitting element further includes a protective layer (including 132 and 176,178), wherein the protective layer is disposed on at least the first inner side surface of the undoped semiconductor layer 18 (since trench is formed to extend through the layer to expose layer 15), the second inner side surface of the superlattice layer (since trench is formed to extend through the layer to expose layer 15), outer side surfaces of the light-emitting element LS, and on a bottom surface of the undoped semiconductor layer (protection layer 132 or 176,178 is disposed on a bottom surface of layer 18).
In re claim 12, Jean discloses (e.g. FIGs. 7-8) wherein the first semiconductor layer 15 is in direct contact with the first electrode 142A, and the second semiconductor layer 17 is in direct contact with the second electrode 142B.
In re claim 17, Jean discloses (e.g. FIGs. 7-8) wherein each of the first electrode 142A and the second electrode 142B includes one or more layers made of at least one of ITO, Mo, Al, Cu, Ni, Ti, Au, W, Pt, Ir, or Cr or an alloy thereof (¶ 69).
In re claim 18, Jean discloses (e.g. FIGs. 5-8) further comprising: a high-potential voltage line (wiring patterns, e.g. 146A, ¶ 74-75) disposed on the substrate 154 and electrically connected to the first electrode 142A; and a low-potential voltage line (another wiring patterns, e.g. 146B or third wiring pattern now shown, ¶ 74-75) disposed on the substrate 154 and electrically connected to the second electrode 142B. No specific “high-potential” and “low-potential” is claimed. Furthermore, the recitation to the “high-potential” and “low-potential” pertains to intended use and functions of the voltage lines. No specific voltage lines have otherwise been claimed that would structurally distinguish over wiring patterns taught by Jean that are used to supply electrical signal to the light-emitting elements and the wiring patterns are capable of function as “high-potential voltage line” and “low-potential voltage line”. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)
In re claim 19, Jean discloses (e.g. FIGs. 5-6) wherein the “high-potential” voltage line (e.g. one of 146A,146B) and the “low-potential” voltage line (e.g. third wiring pattern connecting adjacent light-emitting elements, now shown, ¶ 75) intersect each other to form a mesh structure.
In re claim 21, Jean discloses (e.g. FIGs. 7-8) wherein a recess T (which penetrates through layers to reach layer 15) is formed in the undoped semiconductor layer 18 and the superlattice layer (formed between BS and layer 15, ¶ 56), and the recess T exposes a portion of a surface of the first semiconductor layer 15.
In re claim 22, Jean discloses (e.g. FIG. 3) wherein the undoped semiconductor layer 18, the superlattice layer (formed between BS and layer 15, ¶ 56), the first semiconductor layer 15, the light-emitting layer 16, and the second semiconductor layer 17 are stacked sequentially. The layers maybe sequentially stacked in any order.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Jean as applied to claim 9 above, and further in view of Seo et al. US 2022/0352268 A1 (Seo).
In re claim 13, Jean discloses the claimed invention including an array of light emitting pixels PX having a light-emitting element as recited in claim 9. However, Jean does not explicitly disclose the display device further comprising: a driving transistor disposed on the substrate; and a first planarization layer disposed on the driving transistor.
However, Seo discloses (e.g. FIG. 4) a display device comprising a pixel array of light-emitting elements LE disposed on a substrate 110, and further comprising: a driving transistor T1-T3 disposed on the substrate 110; and a first planarization layer 130 disposed on the driving transistor T1-T3. Seo teaches the transistors T1-T3 are used as driving elements of the display device to control the light emission (¶ 90,100,105).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide driving transistors under Jean’s light-emitting elements for driving the light emitting pixels as taught by Seo, such that the driving transistor locally provide driving signals to the individual light-emitting elements. Furthermore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide a first planarization layer on the driving transistor to provide a planarized surface for forming the overlying light-emitting elements.
In re claim 14, Jean discloses (e.g. FIGs. 7-8) further comprising: a second planarization layer 134+136 disposed between the first connection electrode 144A and the second connection electrode 144B, the second planarization layer 134+136 surrounding an outer side surface of the light-emitting element LS.
In re claim 15, Seo discloses (e.g. FIG. 4) wherein the driving transistor T1-T3 includes an oxide semiconductor layer or a polysilicon semiconductor layer (¶ 105).
Claims 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jean as applied to claim 9 above.
In re claim 16, Jean discloses the light-emitting element is a micro-LED. In particular, Jean discloses (¶ 66) thickness of device 100 is tens to hundreds µm, which is ≤ 1/10 LX. As such, LX can hundreds to thousands µm. For a row of 8 pixels as shown in FIG. 5, each pixel has a width in x-direction that is about 12.5-125 µm. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to that the width of light-emitting element within each pixels would have a width that is less than about 12.5-125 µm. As such, the claimed micro-LED having a width that is less than or equal to about 100 µm would be obvious over Jean. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 20, Jean disclose the superlattice layer is formed between layers 15 and BS (¶ 56) and may either be above or below the undoped semiconductor layer 18. As such, the height from the superlattice layer to the light emitting layer 16 is at most the combined thickness of layers 19+15+18. Jean does not explicitly disclose the height from the superlattice layer to the light-emitting layer 16 relative to a width of the undoped semiconductor layer 18. However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Jean’s light-emitting element such that a height from the superlattice layer that is formed between layers 15 and BS to the light-emitting layer 16 is smaller than a width of the undoped semiconductor layer 18. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2017/0117257 A1 teaches (FIGs. 18-19) a display device including a light emitting element having a trench extending through the undoped semiconductor layer 2153a to expose the semiconductor layer 2153.
US 2023/0352643 A1 teaches (FIGs. 10 & 16) a display device including a light emitting element having a trench extending through the undoped semiconductor layer 2056 to expose the semiconductor layer 2054.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896