DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of species I, claims 1-20, in the reply filed on January 22, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 10, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because:
“28” in Figs. 3B is not labeled;
Fig. 3B shows that “28” formed on sidewalls (only along x-direction) of “20”; however, Figs. 4B-6B, 22B, 27B show that “28” also formed on additional sidewalls (along y-direction) of “20”;
“30” in center portion is missing in Fig. 4B;
“40” in Fig. 5B-7B should read “42”;
“25” in Fig. 8B should read “20”;
Figs. 8B, 12B, 28B, 29B, 31B and 32B fail to show “28” exposed from “48” (as shown in Figs. 8A, 28A, 29A, 31A and 32A, respectively);
Fig. 9A does not correspond to Fig. 9B and [0072] (“a gate dielectric layer 60 is formed over the exposed fin structures 20, which are channel regions, and the surrounding areas”;
“60” in Figs. 10B, 23B is not labeled;
Figs. 12B-14B, 15B-17B, 18A, 24B, 31B-34B fail to show gate structures (i.e. “65”/ “60”/ “45” as shown in Fig. 10B);
“75” is not shown (“70” should read “75”) in Figs. 15B and 16B;
“80” should read “84” in Figs. 17B, 24B and 33B;
“82” and “75” in Figs. 24B and 34B are not labeled;
“25” in Figs. 28B and 29B should read “120”;
a shading between “65” and “45” in Figs. 30A-30B is not labeled;
“30” and “120” in Fig. 31B and 32B are not labeled;
“80” in Fig. 33B should read “70” and “70” should be a single rectangle box and surrounded by “50”;
“80” and “75” in Fig. 34B should read “84” and “82” respectively; and the box between “50” and “75” should be labeled as “75”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “94” (Fig. 30B”). Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: Typographical error. Changing “11BB” to “11B” ([0073], line 1), is suggested.
Appropriate correction is required.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 2, 14, 15 are objected to because of the following informalities: “,” should read “:” after “comprising” (claims 2 and 14, line 1); “the third and fourth semiconductor layers” should read “the third semiconductor and the fourth semiconductor layer” (claim 14). Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no support in the original specification (in the prior-filed application #15/966761, filed on April 30, 2018) for the claim limitations of “forming an fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure”, as recited in claims 1, 11 and 19 (note: paragraph [0119] discloses that “the fin structures 121 include multiple layers of the first semiconductor layer 120 and the second semiconductor layers 125 alternately stacked”).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantially” in claims 1 and 19 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Claim 6 recites the limitation “the fourth semiconductor layer” in line 2. There is insufficient antecedent basis for this limitation in the claim. It is believed claim 6 was intended to depend on claim 2; however, appropriate correction is required.
The claimed limitation of “a source/drain region”, as recited in claims 11 and 19, line 6, is unclear as to whether said limitation is the same as or different from “a source/drain region”, as recited in claims 11 and 19, line 3.
The claimed limitation of “the source/drain region”, as recited in claims 11 and 19, line 8, is unclear as to which source/drain region applicant refer: “a source/drain region”, as recited in claims 11 and 19, line 3 and/or 6.
The claimed limitation of “… reflow …”, as recited in claim 11, is unclear as to what applicant means.
Claim 19 recites the limitation "the source/drain regions" in line 1. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “a source/drain region”, as recited in claim 19.
The claimed limitation of “multiple fins”, as recited in claim 20, is unclear as to whether said limitation is the same as or different from “a fin structure” and/or “a bottom fin structure”, as recited in claim 19.
The claimed limitation of “portions of multiple fins”, as recited in claim 20, is unclear as to whether said limitation is in one-to-one or multiple-to-one relationship between “portion” and “fin” applicant refers.
The claimed limitation of “portions of semiconductor wires”, as recited in claim 20, is unclear as to whether said limitation is in one-to-one or multiple-to-one relationship between “portion” and “semiconductor wire” applicant refers.
The claimed limitation of “an isolation insulating layer”, as recited in claim 20, is unclear as to whether said limitation is the same as or different from “an isolation insulating layer”, as recited in claim 19.
The claimed limitation of “the isolation insulating layer”, as recited in claim 20, line 3, is unclear as to which isolation insulating layer applicant refer: “an isolation insulating layer”, as recited in claim 19 and/or claim 20, line 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 5 and 9-20, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Glass et al. (2014/0001520) in view of Lieten (2010/0159676).
As for claims 1, 11 and 19, Glass et al. show in Figs. 2, 5A-5D and related text a method of manufacturing a semiconductor device 500, the method comprising:
forming a fin structure, in which first semiconductor layers 565 and second semiconductor layers 560A/560B are alternately stacked over a bottom fin structure 550, a source/drain region of the fin structure protruding from an isolation insulating layer 520 (Fig. 5A);
forming an interlayer dielectric (ILD) layer 522 over the fin structure (Fig. 5A);
forming an opening in the ILD layer such that a source/drain region of the fin structure is exposed in the opening (Fig. 5B);
removing the first semiconductor layers from the source/drain region of the fin structure is exposed in the opening (Fig. 5C);
forming a third semiconductor layer (buffer layer (not shown)) and/or (inner portion of) 517 to fully wrap around each of the first semiconductor layers within the opening (Fig. 5D; [0021]-[0022]; [0042]-[0043]);
forming a fourth semiconductor layer (outer portion of) 517 over the third semiconductor layer (Fig. 5D); and
forming a conductive contact layer 529 on the fourth semiconductor layer (Fig. 5D).
Glass et al. do not disclose performing a heating process to make an upper surface of the third semiconductor layer substantially flat (claims 1 and 19); and performing a heating process to reflow the third semiconductor layer (claim 11).
Lieten teaches in Fig. 2 and related text: performing a heating process to make an upper surface of the epitaxial layer substantially flat ([0058]).
Glass et al. and Lieten are analogous art because they are directed to a method of forming an epitaxial semiconductor film and one of ordinary skill in the art would have had a reasonable expectation of success to modify Glass et al. with the specified feature(s) of Lieten because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include performing a heating process, as taught by Lieten, in Glass et al.’s device, in order to improve the electrical quality of the device.
Therefore, the combined device shows:
As for claims 1 and 19, performing a heating process to make an upper surface of the third semiconductor layer substantially flat.
As for claim 11, performing a heating process to reflow the third semiconductor layer
As for claim 3, the combined device shows the third epitaxial semiconductor layer is Ge or Si1-xGex, where 0.3 < x < 1 (Glass: [0021]-[0022]; [0042]-[0043])
As for claim 5, the combined device shows the third semiconductor layer is epitaxially formed at a substrate temperature in a range from 350 C to 410 °C (Glass: [0044]), and
the heating process is performed at the substrate temperature in a range from 410 °C to 470 °C (Lieten: [0058]).
As for claim 9, the combined device shows no void is formed at a bottom or sides of the third semiconductor layer (Glass: Fig. 5D).
As for claim 10, the combined device shows side faces of the third semiconductor layer and side faces of the conductive contact are in (electrical and thermal) contact with an inner wall of the opening (Glass: Fig. 5D).
As for claims 12-13, Glass et al. and Lieten disclosed substantially the entire claimed invention, as applied to claim 11 above, except after the heating process is performed, a thickness variation of the third semiconductor layer in the opening is less than or equal to 5 nm; and the thickness variation of the first epitaxial semiconductor layer in the opening is more than or equal to 0.2 nm.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the thickness variation of the first epitaxial semiconductor layer in the opening being less than or equal to 5nm and more than or equal to 0.2 nm, in order to optimize the performance of the device. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
As for claim 14, the combined device shows after the fourth semiconductor layer is formed and before the conductive contact is formed, annealing the third and fourth semiconductor layers (Glass: [0059]).
As for claim 15, the combined device shows the annealing operation is performed by a laser annealing method (Glass: Figs. 5C-5D combined with Lieten: Fig. 2).
As for claim 16, the combined device shows the forming the third semiconductor layer, the performing the heating process and the forming the fourth semiconductor layer are performed in a same manufacturing apparatus (Glass: Figs. 5C-5D combined with Lieten: Fig. 2).
As for claim 17, the combined device shows the heating process and the forming the fourth semiconductor layer are performed at a same substrate temperature (Glass: Figs. 5C-5D combined with Lieten: Fig. 2).
As for claim 18, Glass et al. and Lieten disclosed substantially the entire claimed invention, as applied to claim 11 above, except a growth rate of the third semiconductor layer is in a range from 5 nm/min to 15 nm/min.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include a growth rate of the third semiconductor layer is in a range from 5 nm/min to 15 nm/min, in order to optimize the performance of the device. Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
As for claim 20, the combined device shows the source/drain regions are (i) portions of multiple fins protruding from an isolation insulating layer, or (ii) portions of semiconductor wires horizontally extending over the isolation insulating layer (Glass: Fig. 5A-5D).
Claim(s) 4, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Glass et al. (2014/0001520) and Lieten (2010/0159676) in view of Glass et al. (2019/0341300, hereinafter Glass’300).
Glass et al. and Lieten disclosed substantially the entire claimed invention, as applied to claim 1 above, except the third semiconductor layer is doped with phosphorous.
Glass’300 teaches in Figs. 1, 2A-2H’ and related text the third semiconductor layer is doped with phosphorous.
Glass et al., Lieten and Glass’300 are analogous art because they are directed to a method of forming an epitaxial semiconductor film and one of ordinary skill in the art would have had a reasonable expectation of success to modify Glass et al. and Lieten with the specified feature(s) of Glass’300 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the third semiconductor layer being doped with phosphorous, as taught by Glass’300, in Glass et al. and Lieten's device, in order to form an N-type semiconductor device. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Allowable Subject Matter
Claims 2 and 6-8 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of “after the heating process is performed and before the conductive contact is formed, forming a fourth semiconductor layer over the third semiconductor layer and an upper surface of the interlayer dielectric layer”, as recited in claim 2.
Claims 2-8 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM.
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/MEIYA LI/Primary Examiner, Art Unit 2811
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