DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1, namely, Fig. 18, claims 1-11 and 14 are drawn to Group I and Species 1, in the reply filed on 11/25/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. 20170148856.
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Regarding claim 1, figs. 1 and 7 of Choi discloses a display device comprising:
a substrate 100 comprising a display area DA in which emission areas (area of 200s) are arranged, a main non-display area NA around the display area, a hole area A1 surrounded by the display area, and an additional non-display area A3 between the hole area A1 and the display area A2;
a circuit layer (layer of TFT/130 and 107’) on the substrate and comprising pixel drivers 130s respectively corresponding to the emission areas (area of 200);
a light emitting element layer (layer of 200) on the circuit layer and comprising light emitting elements 200s respectively corresponding to the emission areas;
a sealing layer 300 on the light emitting element layer;
a through portion TH in the hole area and penetrating at least the substrate; and
sealing auxiliary structures (as labeled by examiner above) in the additional non-display area and sequentially surrounding the hole area, wherein each of the sealing auxiliary structures comprises:
a first main layer 610B1;
a first cover layer 620B1 on the first main layer;
a second main layer 610B2 on the first cover layer;
a second cover layer 620B2 on the second main layer;
a first undercut portion in which the first cover layer protrudes from the first main layer; and
a second undercut portion in which the second cover layer protrudes from the second main layer.
Regarding claim 2, fig. 7 of Choi discloses wherein the light emitting element layer comprises:
an anode 210 on the circuit layer and corresponding to each of the emission areas;
a pixel defining layer on the circuit layer, corresponding to a non-emission area around each of the emission areas, and covering edges of the anode;
a first common layer 223 on the anode;
a light emitting layer 222 on the first common layer;
a second common layer 223 on the pixel defining layer and the light emitting layer and corresponding to the display area (par [0069]); and
a cathode 230 on the second common layer and corresponding to the display area,
wherein each of the light emitting elements has a structure in which the light emitting layer is between the anode and the cathode, and the second common layer and the cathode extend to the additional non-display area (see fig. 7) and are separated by the first undercut portion and the second undercut portion of each of the sealing auxiliary structures.
Regarding claim 3, fig. 7 of Choi discloses wherein the circuit layer comprises:
a semiconductor layer 131 on the substrate;
a first conductive layer 132/151’ on a gate insulating layer 103 covering the semiconductor layer;
a second conductive layer 152’ on an interlayer insulating layer 105 covering the first conductive layer;
a third conductive layer (source and drain electrode layer 133/134) on a first planarization layer covering the second conductive layer (covers the sides); and
a second planarization 106 covering the third conductive layer,
wherein the second conductive layer comprises the first main layer and the first cover layer (multiple layers – par [0098]), and
the third conductive layer comprises the second main layer and the second cover layer (Ti/Al/Ti – par [0098]).
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Regarding claim 4, Choi discloses claim 3. Fig. 7 of Choi discloses wherein the additional non-display area comprises:
a sub-encapsulation area (as labeled by examiner above) adjacent to the hole area and surrounding the hole area; and
a wiring bypass area (area around TH so that wiring can surround the TH) between the sub-encapsulation area and the display area,
and the circuit layer further comprises wirings (that between 210 and 134) electrically connected to the pixel drivers,
wherein some of the wirings (as labeled by examiner above) intersecting the hole area and the additional non-display area bypass the hole area along edges of the hole area in the wiring bypass area, and the first planarization layer and the second planarization layer extend to the wiring bypass area.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Lee et al. 20220020955.
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Regarding claim 5, Choi discloses claim 4, Choi a sub-dam portion DM1 comprising one or more sub-dams (portions of 107’ below some of the wirings) in a sub-dam area (area of portions of 107’ below some of the wirings) of the sub-encapsulation area adjacent to the wiring bypass area and sequentially surround the hole area.
Choi does not disclose further comprising: a main dam portion comprising one or more main dams in a main dam area of the main non-display area adjacent to the display area and sequentially surround edges of the display area; and wherein the first planarization layer, the second planarization layer, and the pixel defining layer are spaced apart from the main dam area and the sub-dam area.
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However, fig. 4 of Lee discloses a display device comprising a main dam portion comprising one or more main dams (DM2) in a main dam area of a main non-display area NA adjacent to the display area DA and sequentially surround edges of the display area; and wherein a first planarization layer 181, the second planarization layer 182, and the pixel defining layer are spaced apart from the main dam area and the sub-dam area.
In view of such teaching, it would have been obvious to form a device of Choi further comprising a main dam portion comprising one or more main dams in a main dam area of the main non-display area adjacent to the display area and sequentially surround edges of the display area; and wherein the first planarization layer, the second planarization layer, and the pixel defining layer are spaced apart from the main dam area and the sub-dam area such as taught by Lee in order to protect the display form moisture leakage to the display.
Regarding claim 6, fig. 4 of Lee discloses wherein a sealing layer 390 comprises: a first inorganic layer 391 covering the light emitting element layer and comprising an inorganic insulating material; an organic layer 392 on the first inorganic layer and comprising an organic insulating material; and a second inorganic layer 393 covering the organic layer and comprising the inorganic insulating material, wherein the organic layer corresponds to an area between the main dam portion and the sub-dam portion and overlaps the light emitting element layer.
As such it would have been obvious to form a device of Choi and Lee further comprising wherein the sealing layer comprises: a first inorganic layer covering the light emitting element layer and comprising an inorganic insulating material; an organic layer on the first inorganic layer and comprising an organic insulating material; and a second inorganic layer covering the organic layer and comprising the inorganic insulating material.
Furthermore, it would have been obvious to form a device comprising wherein the organic layer corresponds to an area between the main dam portion and the sub-dam portion and overlaps the light emitting element layer and the first inorganic layer and the second inorganic layer contact each other in the main dam area and the sub-dam area in order to protect the display form unwanted elements.
Regarding claim 7, the resulting structure would have been one wherein the first inorganic layer contacts (indirectly) a portion of the first main layer exposed by the first undercut portion of each of the sealing auxiliary structures and contacts (indirectly) a portion of the second main layer exposed by the second undercut portion of each of the sealing auxiliary structures.
Regarding claim 8, fig. 7 of Choi discloses further comprising an etch stop portion (620A/610A)) in an area between the sealing auxiliary structures, wherein the sealing auxiliary structures and the etch stop portion are on the interlayer insulating layer (on the sides).
Regarding claim 9, fig. 7 of Choi discloses wherein the etch stop portion comprises a portion of the first main layer 610A) on the interlayer insulating layer 620A.
Regarding claim 10, par [0098] of Choi discloses wherein each of the first main layer and the second main layer comprises at least one of aluminum (Al) or copper (Cu), and each of the first cover layer and the second cover layer comprises at least one of titanium (Ti) or molybdenum (Mo).
Regarding claim 11 (see rejection of claim 3), Choi discloses wherein the second conductive layer further comprises a first bottom layer between the interlayer insulating layer and the first main layer, the third conductive layer further comprises a second bottom layer between the first planarization layer and the second main layer, each of the sealing auxiliary structures further comprises the first bottom layer and the second bottom layer, and the second bottom layer of each of the sealing auxiliary structures is between the first cover layer and the second main layer.
Regarding claim 14, par [0098] of Choi wherein each of the first main layer and the second main layer comprises at least one of aluminum (Al) or copper (Cu), each of the first cover layer and the second cover layer comprises at least one of titanium (Ti) or molybdenum (Mo), and each of the first bottom layer, and the second bottom layer comprises at least one of titanium (Ti) or molybdenum (Mo).
Conclusion
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893