DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Snider et al. (U.S. Patent Number 5,729,752) and Riley (U.S. Patent Application Publication Number 2005/0238035).
Regarding Claim 1, Snider discloses a device (Figure 4, item 505) comprising:
a plurality of connectors (Figure 4, items 518-520, Column 4, lines 34-38);
a plurality of switches (Figure 4, items 536/538/540, Column 5, lines 13-18); and
a plurality of compute elements (Figure 4, items 515-517), wherein each of the plurality of compute elements is connected to each of the plurality of switches (Figure 4, Column 3, lines 44-45), and
a first subset of the plurality of switches is directly connected via a first mechanism to a first subset of the plurality of the connectors comprising at least two connectors (Figure 4, Column 5, lines 13-18; i.e., first subset of switches 538 is directly connected to first subset of connectors 518 and 519 via on-board wiring [the claimed “first mechanism”]), and
a second subset of the plurality of switches is directly connected via a second mechanism to a second subset of the plurality of the connectors comprising at least two connectors (Figure 4, Column 5, lines 13-18; i.e., second subset of switches 540 is directly connected to second subset of connectors 519 and 520 via on-board wiring [the claimed “second mechanism”]); and
wherein the first and second mechanisms comprise an on-board fanout wiring structure (Figure 4; i.e., the wiring structure shown between the various switches 536-540 and connectors 518-520) that aggregates signal paths (i.e., each signal path from the various switches 536-540 comes into each connector 518-520 and is therefore are “aggregated”) from subsets of switches (i.e., different subsets of switches 536-540) into subsets of connectors (i.e., different subsets of connectors 518-520) such that the connectors convey aggregated switch traffic through an interconnect (Figure 4, Column 3, lines 44-64; i.e., the connectors 518-520 convey “aggregated switch traffic” through each interconnect 523, 546, and 524 because all of the data that comes from the switches 536-540 ultimately is sent over those interconnects 523, 546, and 524).
Snider does not expressly disclose wherein the first subset of the plurality of the connectors is mutually exclusive with the second subset of the plurality of the connectors.
In the same field of endeavor (e.g., multi-processor switching techniques), Riley teaches wherein the first subset of the plurality of the connectors is mutually exclusive with the second subset of the plurality of the connectors (Figure 1A, paragraphs 0019-0021; i.e., a first switch 114 is connected to a first subset of connectors 06 and 37, while a second switch 118 is connected to a second subset of connectors 15 and 34; each of these subsets of connectors are mutually exclusive with respect to one another).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Riley’s teachings of multi-processor switching techniques with the teachings of Snider, for the purpose of further expanding the data transmission capabilities of the device. More specifically, by increasing the number of connectors to which the switches connect to, additional devices can receive data from the device.
Regarding Claim 2, Snider discloses wherein the device is a Printed Circuit Board (PCB) that connects to other PCBs via the plurality of connectors, as part of a High-Performance Computing (HPC) system (Column 2, lines 13-20).
Regarding Claims 3 and 17, Snider discloses where the first plurality of switches is half of the plurality of switches and the first subset of the plurality of connectors is half of the plurality of connectors (Column 2, lines 37-40; i.e., it is possible that there are only two switches and two connectors on the circuit board; in that case, one of the switches would be equivalent to the claimed “first subset of the plurality of switches” and one of the connectors would be equivalent to the claimed “first subset of the plurality of connectors”).
Regarding Claim 4, Snider discloses wherein the device is a Printed Circuit Board (PCB) that connects to other PCBs via the plurality of connectors (Column 2, line 65 – Column 3, line 6) and each connector of the plurality of connectors connects to two other PCBs (Column 3, lines 23-26; i.e., each connector 518-520 [Figure 5] connects to both a connector of another circuit board directly as well as another connector of the other circuit board indirectly through the switches 536/538/540).
Regarding Claim 5, Snider discloses where the first plurality of switches and second plurality of switches is each one quarter of the plurality of switches and the first subset of the plurality of connectors and second plurality of connectors is each one quarter of the plurality of connectors (Column 5, lines 13-18; i.e., Snider states that there is “at least one switching means” on each circuit board, which can be taken to mean four switches; further, a first switch and a second switch can each be interpreted as “one quarter of the plurality of switches; a similar analysis can be applied to the “at least one connecting means” discussed in the reference [see Column 4, lines 35-38]).
Regarding Claim 6, Snider discloses where the device is a Printed Circuit Board (PCB) and each of the plurality of connectors connects to 4 other PCBs (Figure 4; i.e., each connector on each circuit board 501-507 directly connects to one other circuit board; in addition, each connector also connects to at least three other circuit boards indirectly through the various other connectors and switches).
Regarding Claims 7 and 18, Snider discloses where each of the plurality of compute elements is one of: a Graphics Processing Units (GPUs), Central Processing Units (CPUs), Tensor Processing Units (TPUs), Neural Processing Units (NPUs), Vision Processing Units (VPUs), Field Programmable Gate Arrays (FPGAs), or a Microprocessor (Column 3, lines 37-43).
Regarding Claim 8, Snider discloses wherein the first and second mechanisms are each fanouts (Figure 4; i.e., as shown in the figure, each of the various switches [e.g., 530/532/534] can be a single source that connects to plural destinations [i.e., a fanout topology]).
Regarding Claim 16, Snider discloses high-performance computing system comprising:
a plurality of circuit boards (Figure 4, items 501-507) each including a plurality of compute elements (Figure 4, items 515-517), a plurality of switches (Figure 4, items 536/538/540), and a plurality of connectors (Figure 4, items 518-520, Column 3, lines 35-37 and Column 4, lines 34-38; i.e., all boards 501-507 can have the same components),
where each of the plurality of circuit boards is connected (Figure 4; i.e., each connector on each circuit board 501-507 directly connects to one other circuit board; in addition, each connector also connects to at least three other circuit boards indirectly through the various other connectors and switches)
wherein each of the plurality of compute elements is connected to each of the plurality of switches (Figure 4, Column 3, lines 44-45), and
a first subset of the plurality of switches is directly connected to a first subset of the plurality of the connectors comprising at least two connectors via a first mechanism (Figure 4, Column 5, lines 13-18; i.e., first subset of switches 538 is directly connected to first subset of connectors 518 and 519 via on-board wiring [the claimed “first mechanism”]), and
a second subset of the plurality of switches is directly connected to a second subset of the plurality of the connectors comprising at least two connectors via a second mechanism on its respective circuit board of the plurality of circuit boards (Figure 4, Column 5, lines 13-18; i.e., second subset of switches 540 is directly connected to second subset of connectors 519 and 520 via on-board wiring [the claimed “second mechanism”]); and
wherein the first and second mechanisms comprise an on-board fanout wiring structure (Figure 4; i.e., the wiring structure shown between the various switches 536-540 and connectors 518-520) that aggregates signal paths (i.e., each signal path from the various switches 536-540 comes into each connector 518-520 and is therefore are “aggregated”) from subsets of switches (i.e., different subsets of switches 536-540) into subsets of connectors (i.e., different subsets of connectors 518-520) such that the connectors convey aggregated switch traffic through an interconnect (Figure 4, Column 3, lines 44-64; i.e., the connectors 518-520 convey “aggregated switch traffic” through each interconnect 523, 546, and 524 because all of the data that comes from the switches 536-540 ultimately is sent over those interconnects 523, 546, and 524).
Snider does not expressly disclose wherein the first subset of the plurality of the connectors is mutually exclusive with the second subset of the plurality of the connectors.
In the same field of endeavor, Riley teaches wherein the first subset of the plurality of the connectors is mutually exclusive with the second subset of the plurality of the connectors (Figure 1A, paragraphs 0019-0021; i.e., a first switch 114 is connected to a first subset of connectors 06 and 37, while a second switch 118 is connected to a second subset of connectors 15 and 34; each of these subsets of connectors are mutually exclusive with respect to one another).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 16.
Claims 9, 10, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Snider and Rowley et al. (U.S. Patent Application Publication Number 2019/0012280).
Regarding Claim 9, Snider discloses a device (Figure 4, item 505) comprising:
a plurality of connectors (Figure 4, items 519 and 520);
a plurality of switches of a first quantity greater than 1 (Figure 4, items 538 and 540; i.e., the first quantity being 2); and
a plurality of compute elements (Figure 4, items 515-517), where each of the plurality of compute elements is directly connected via a mechanism to each of the plurality of switches (Figure 4, Column 3, lines 44-45), and the plurality of switches is each directly connected to the plurality of the connectors (Figure 4; i.e., each switch 538 and 540 is directly connected to the plurality of connectors 519 and 520), and each of the plurality of the connectors connects to a quantity of devices (Figure 4, Column 3, lines 35-52; i.e., each connector 519 and 520 connects to the other devices 502 and 503);
wherein the device includes an on-board fanout wiring structure (Figure 4; i.e., the wiring structure shown between the various switches 536-540 and connectors 518-520) that aggregates signal paths (i.e., each signal path from the various switches 536-540 comes into each connector 518-520 and is therefore are “aggregated”) from subsets of switches (i.e., different subsets of switches 536-540) into subsets of connectors such that the connectors (i.e., different subsets of connectors 518-520) convey aggregated switch traffic through an interconnect (Figure 4, Column 3, lines 44-64; i.e., the connectors 518-520 convey “aggregated switch traffic” through each interconnect 523, 546, and 524 because all of the data that comes from the switches 536-540 ultimately is sent over those interconnects 523, 546, and 524).
Snider does not expressly disclose wherein the quantity of devices is equal to the first quantity (e.g., 2).
In the same field of endeavor (e.g., fanout connection techniques), Rowley teaches each of the plurality of the connectors (Figure 2A, items 225) connects to a quantity (e.g., 2) of devices (Figure 2A, items 230) equal to the first quantity (paragraphs 0022-0023; i.e., each of the interface devices 225 [the claimed “connectors”] is capable of communicating with plural devices 230 using plural channels 227).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Rowley’s teachings of fanout connection techniques with the teachings of Snider, for the purpose of increasing the communication capacity of the system, which would allow for increased capabilities such as processing and storage (see Rowley, paragraph 0023).
Regarding Claim 10, Snider discloses wherein the device is a Printed Circuit Board (PCB) that connects to other PCBs via the plurality of connectors and each connector of the plurality of connectors connects to one other PCB (Column 2, lines 13-20).
Regarding Claim 13, Snider discloses wherein the device is a Printed Circuit Board (PCB) that connects to other PCBs via the plurality of connectors, as part of a High-Performance Computing (HPC) system (Column 2, lines 13-20).
Regarding Claim 14, Snider discloses where each of the plurality of compute elements is one of: a Graphics Processing Units (GPUs), Central Processing Units (CPUs), Tensor Processing Units (TPUs), Neural Processing Units (NPUs), Vision Processing Units (VPUs), Field Programmable Gate Arrays (FPGAs), or a Microprocessor (Column 3, lines 37-43).
Regarding Claim 15, Snider discloses wherein the mechanism is a fanout (Figure 4; i.e., as shown in the figure, each of the various switches [e.g., 530/532/534] can be a single source that connects to plural destinations [i.e., a fanout topology]).
Claim 11 are rejected under 35 U.S.C. 103 as being unpatentable over Snider and Rowley as applied to Claim 10, and further in view of Yao et al. (U.S. Patent Application Publication Number 2019/0109800).
Regarding Claim 11, Snider and Rowley do not expressly disclose wherein the PCB and the other PCB are from a plurality of PCBs in a rack in a datacenter.
In the same field of endeavor (e.g., networking circuit boards), Yao teaches wherein the PCB and the other PCB are from a plurality of PCBs in a rack in a datacenter (paragraphs 0010-0011).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Yao’s teachings of networking circuit boards with the teachings of Snider and Rowley, for the purpose of providing increased density and space efficiency, improved cooling and airflow management, easier maintenance and repair access, high reliability and performance, standardized connections, and the ability to scale capacity rapidly by simply adding more populated racks as needed; essentially optimizing the use of valuable data center space while maintaining high operational efficiency.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Snider, Rowley, and Yao as applied to Claim 11, and further in view of Starmer et al. (U.S. Patent Application Publication Number 2007/0260417).
Regarding Claim 12, Snider, Rowley, and Yao do not expressly disclose wherein the rack has a routing device which routes tasks to a plurality of compute elements on each of the plurality of PCBs in the rack.
In the same field of endeavor (e.g., networking circuit boards), Starmer teaches wherein the rack has a routing device (Figure 1, item 22) which routes tasks (paragraph 0026) to a plurality of compute elements (paragraph 0031; i.e., there may be plural computers within rack 16) on each of the plurality of PCBs (i.e., as stated in the rejection of Claim 11 above, Yao teaches the plurality of PCBs in a rack) in the rack (Figure 1, item 16; i.e., Starmer appears to show the routing device 22 as separate from the rack 16, however it would have been obvious to one of ordinary skill in the art to have placed the routing device 22 within the rack 22 for the purpose of minimizing the amount of floor space required for the various devices in the data center; further, Starmer states that various elements in the figures can be integrated [see paragraph 0079]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Starmer’s teachings of networking circuit boards with the teachings of Snider, Rowley, and Yao, for the purpose of providing improved organization, better cable management, enhanced cooling, increased security, and easier access for maintenance and monitoring, all while maximizing space utilization within the data center environment.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Snider and Riley as applied to Claim 16, and further in view of Starmer.
Regarding Claim 19, Snider and Riley do not expressly disclose a routing device connected to the plurality of circuit boards which routes tasks to the plurality of compute elements.
In the same field of endeavor (e.g., networking circuit boards), Starmer teaches a routing device (Figure 1, item 22) connected to the plurality of circuit boards (Figure 1, item 16, paragraph 0031; i.e., there may be plural computers within rack 16) which routes tasks to the plurality of compute elements (paragraph 0026).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Starmer’s teachings of networking circuit boards with the teachings of Snider and Riley, for the purpose of providing improved organization, better cable management, enhanced cooling, increased security, and easier access for maintenance and monitoring, all while maximizing space utilization within the data center environment.
Regarding Claim 20, Starmer teaches wherein the routing device communicates with the plurality of compute elements and performs throttling to manage the bandwidth and processing loads of the plurality of circuit boards and compute elements (paragraphs 0027 and 0041; i.e., the routing system 22 together with the load balancing controller 30 can adjust the bandwidth and load on each rack 16-20 by reallocating the virtual machines 42-62).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses devices with fanout connections for high performance computers.
Response to Arguments
Applicant's arguments filed 3/3/26 have been fully considered but they are not persuasive.
Regarding Claim 1, Applicant argues “neither Snider nor Riley disclose or suggest a device wherein the first and second mechanisms comprise an on-board fanout wiring structure that aggregates signal paths from subsets of switches into subsets of connectors such that the connectors convey aggregated switch traffic through an interconnect as expressly recited in amended independent claims 1 and 16.” Response, page 9. The examiner disagrees. Contrary to Applicant’s argument, Snider does in fact disclose the argued feature. The on-board wiring shown between the switches 536-540 and the connectors 518-520 (Figure 4) is equivalent to the claimed “fanout wiring structure”. Further, Snider discloses that the connectors 518-520 convey “aggregated switch traffic” through each interconnect 523, 546, and 524 because all of the data that comes from the switches 536-540 ultimately is sent over those interconnects 523, 546, and 524. See Snider, Figure 4, Column 3, lines 44-64. Accordingly, it can be seen that Snider does in fact disclose the argued feature.
Applicant makes a similar argument with regards to Claim 9 and therefore the above discussion applies to that claim as well.
Therefore, the claims stand as previously rejected.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN, ESQ. whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175