DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 19, 2026 has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on January 19, 2026. Claim 9 has been amended. New claims 10-13 have been added. Claims 1-8 have been canceled. Currently, claims 9-13 are pending.
Response to Arguments
Applicant's arguments filed on January 19, 2026 have been fully considered but they are not persuasive. Applicant asserts that the newly added claim limitation, “wherein a thickness of the first amorphous silicon layer is smaller than the thickness difference between the first region and the channel region and the thickness difference between the second region and the channel region” is not taught by prior art. The Examiner disagrees with the assertion.
Watanabe teaches a doped semiconductor layer 5 (equivalent to the instant application’s second amorphous silicon film) with a thickness range of 20nm to 70nm. Watanabe further defines the thickness t1 of the gap portion C of the semiconductor layer 4 (60nm to 150nm) and thickness t2 of the recessed portions of the semiconductor layer 4 (30nm-70nm). The difference between the t1 and t2 maybe in the range of more than 20nm (e.g., 90nm -70nm) and less than 70nm (e.g., 100nm -30nm).
By replacing Watanabe’s layer 5 with Wu’s multilayer structure 110 which includes sub-layers 106a, 106b and 108. Wu’s 108 (equivalent to the instant application’s first amorphous silicon layer) has a thickness of about 200 Angstroms (20nm). This thickness is consistently smaller than the thickness difference calculated from Watanabe (t1-t2, which maybe more than 20nm and less than 70nm). Therefore, the combined teachings of Watanabe and Wu show that the thickness of the first amorphous silicon layer is smaller than the calculated thickness difference, thus reading on the claim limitation.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9-13 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 9, the claim recites, “wherein the thickness of the channel region is 800 A to 1500 A”, which lacks written description support because the specification does not clearly show the inventor had possession of the exact fixed range of 800A to 1500 A. The specification provides an approximate range of 800A to 1500 A which suggests a range around these values. Converting an approximate range into a fixed, absolute range constitutes a change in technical meaning of the boundaries. This change implies precision that the inventor did not actually disclose at the time of filing.
Claims 10-13 depend upon claim 9 and do not rectify the problem therefore, they are also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe et al. (US 2002/0146871 A1; hereafter Watanabe) in view of Wu et al. (US 2012/0139043 A1; hereafter Wu).
Regarding claim 9, Watanabe teaches a manufacturing method for a thin-film transistor (see e.g., Figures 5 and 6A-6C), the manufacturing method comprising:
forming a gate electrode (see e.g., gate electrode 2, Para [0111], Figures 5 and 6A-6C) and a first insulation layer (see e.g., gate insulating film 3, Para [0112], Figures 5 and 6A-6C), in this order, on a substrate (see e.g., gate electrode 2 and the gate insulating film 3 are formed on the substrate 1, Paras [0111], Figures 5 and 6A-6C);
depositing, directly on the first insulation layer, a first amorphous silicon film (see e.g., the semiconductor film 4, which maybe an amorphous silicon layer, is deposited directly on the gate insulating film 3, Paras [0059], [0112], Figures 5 and 6A-6C), and a second insulation layer in this order (see e.g., channel protection film 8 deposited on the semiconductor layer 4, Para [0112], Figures 5 and 6A-6C), wherein the first amorphous silicon film is non-doped (see e.g., the semiconductor layer 4 is non-doped, Paras [0059], [0106]);
forming a channel stopper by patterning the second insulation layer on a first portion of the first amorphous silicon film, wherein the first portion is to be a channel region (see e.g., the channel protection film 8 is patterned so that the channel protection film 8 remains on the portion of the semiconductor layer 4 at the gap portion, Para [0114], Figures 5 and 6A-6C);
forming a recess in the first amorphous silicon film by etching a second portion of the first amorphous silicon film, wherein the second portion is not covered by the channel stopper (see e.g., the thickness of the semiconductor layer 4 not covered by the channel protection film 8 is reduced by etching, Para [0114], Figures 5 and 6A-6C), thereby forming, above the gate electrode, a body layer from the first amorphous silicon film (see e.g., the semiconductor layer 4 above the gate electrode has a gap portion C, Para [0114], Figures 5 and 6A-6C), wherein the body layer comprises a first region (see e.g., one side of the semiconductor layer 4 not covered by the channel protection film 8, Figures 5 and 6A-6C), a second region (see e.g., another side of the semiconductor layer 4 not covered by the channel protection film 8, Figures 5 and 6A-6C), and the channel region being positioned between the first region and the second region (see e.g., the gap portion C under the channel protection film 8, Figures 5 and 6A-6C), a thickness of the channel region is greater than a thickness of each of the first region and the second region (see e.g., the thickness t1 of the gap portion C of the semiconductor layer 4 under the channel protection film 8 is greater than the thickness t2 of the portions not under the channel protection film 8, Para [0114], Figures 5 and 6A-6C);
depositing a second amorphous silicon film …..above the body layer and the channel stopper, wherein the first amorphous silicon layer contains impurities (see e.g., doped semiconductor layer 5 is deposited to cover the channel protection film 8 and the semiconductor layer 4, Paras [0060], [0117], Figures 5 and 6A-6C);
depositing a conductor layer on the second amorphous silicon film (see e.g., conductor for source and drain electrodes 6 is deposited on the doped semiconductor layer 5, Para [0117], Figures 5 and 6A-6C); and
forming, from the second amorphous silicon film, a first contact layer that is positioned on the first region and a second contact layer that is positioned on the second region (see e.g., the doped semiconductor layer 5 is etched so that it remains on the recessed portions of the semiconductor layer 4, Para [0118], Figures 5 and 6A-6C), and forming, from the conductor layer, a source electrode that is in direct contact with the first amorphous silicon layer of the first contact layer and that is electrically connected to the first region via the first contact layer (see e.g., the conductor for the source and drain electrodes 6 is etched to form the source electrode in contact with one of the recessed portions of the semiconductor layer 4 via one of the etched portions of doped semiconductor layer 5, Para [0118], Figures 5 and 6A-6C) and a drain electrode that is in direct contact with the first amorphous silicon layer of the second contact layer and that is electrically connected to the second region via the second contact layer, by patterning the conductor layer and the second amorphous silicon film (e.g., the conductor for the source and drain electrodes 6 is etched to form the drain electrode in contact with another of the recessed portions of the semiconductor layer 4 via another of the etched portions of doped semiconductor layer 5, Para [0118], Figures 5 and 6A-6C),
wherein the thickness of the channel region is 800 A to 1500 A (see e.g., The thickness t1 of the gap portion C of the semiconductor layer 4 is 60 nm-150 nm, Paras [0113] – [0114], Figures 5 and 6A-6C),
wherein the thickness of each of the first region and the second region is 30% to 70% of the thickness of the channel region, (see e.g., the thickness t1 of the gap portion C of the semiconductor layer 4 is 60nm – 150nm and the thickness t2 of the recessed portions of the semiconductor layer 4 is about 30nm-70nm. If for example, t1 is 60nm and t2 is 30nm, in this case the thickness t2 would be 50 % the thickness t1, Paras [0113] – [0114])
wherein a thickness of each of the first contact layer and the second contact layer is greater than a thickness difference between the first region and the channel region and a thickness difference between the second region and the channel region (see e.g., the thickness of the doped semiconductor layer 5 is between 20nm to 70nm. The thickness t1 of the gap portion C of the semiconductor layer 4 is 60nm – 150nm and the thickness t2 of the recessed portions of the semiconductor layer 4 is about 30nm-70nm. For example, if thickness of the doped semiconductor layer 5 is 70nm, t1 is 60nm and t2 40nm then the difference t1-t2 will be 20nm. In this case the thickness of the doped semiconductor layer 5 that is, 70nm is greater than the difference t1-t2 and reads on the claimed limitation, Paras [0113], [0114], [0117]).
Watanabe does not explicitly teach
“a second amorphous silicon film comprising a first amorphous silicon layer as an uppermost layer thereof
wherein a thickness of the first amorphous silicon layer is smaller than the thickness difference between the first region and the channel region and the thickness difference between the second region and the channel region”.
In a similar field of endeavor Wu teaches
a second amorphous silicon film comprising a first amorphous silicon layer as an uppermost layer thereof (see e.g., the TFT has a semiconductor stacked layer 110, the ohmic contact layer, including the second semiconductor layer 108, a doped amorphous silicon layer, as an uppermost layer, Para [0029], Figure 1)
wherein a thickness of the first amorphous silicon layer is smaller than the thickness difference between the first region and the channel region and the thickness difference between the second region and the channel region
Wu teaches the second semiconductor layer 108 has a thickness of about 20nm (see e.g., Para [0051]). This thickness is consistently smaller than the thickness difference calculated from Watanabe (t1-t2, which maybe more than 20nm and less than 70nm). Therefore, the combined teachings of Watanabe and Wu show that the thickness of the first amorphous silicon layer is smaller than the calculated thickness difference, thus reading on the claim limitation.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement thinner specific layer in a multilayered ohmic contact layer to improve the device, as demonstrated by the improved drive current and contact resistivity achieved by such structures.
Regarding claim 13, Watanabe, as modified by Wu, teaches the limitations of claim 9 as mentioned above. Watanabe does not explicitly teach
“wherein the second amorphous silicon film further comprises one or more fourth amorphous silicon layers, each of the one or more fourth amorphous silicon layers consisting of a non-doped intrinsic amorphous silicon”.
In a similar field of endeavor Wu teaches
wherein the second amorphous silicon film further comprises one or more fourth amorphous silicon layers, each of the one or more fourth amorphous silicon layers consisting of a non-doped intrinsic amorphous silicon (see e.g., the TFT has a semiconductor stacked layered 110 including a third semiconductor layer 106a such as a non-doped amorphous silicon, Para [0027], Figure 1).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wu’s teachings of wherein the second amorphous silicon film further comprises one or more fourth amorphous silicon layers, each of the one or more fourth amorphous silicon layers consisting of a non-doped intrinsic amorphous silicon in the method of Watanabe in order to improve the device, as demonstrated by the improved drive current and contact resistivity achieved by such structures.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe et al. (US 2002/0146871 A1; hereafter Watanabe) in view of Wu et al. (US 2012/0139043 A1; hereafter Wu) and further in view of Ohta et al. (WO 2020031309 A1; hereafter Ohta).
Regarding claim 10, Watanabe, as modified by Wu, teaches the limitations of claim 9 as mentioned above. Watanabe does not explicitly teach
“wherein the second amorphous silicon film further comprises one or more third amorphous silicon layers, each of the one or more third amorphous silicon layers containing impurities in a concentration lower than a concentration of the first amorphous silicon layer and higher than a concentration of a surface of each of the first region and the second region joining with the first contact layer or the second contact layer, and a thickness of a third amorphous silicon layer located directly below the first amorphous silicon layer among the one or more third amorphous silicon layers is smaller than the thickness difference between the first region and the channel region and the thickness difference between the second region and the channel region”.
In a similar field of endeavor Ohta teaches
wherein the second amorphous silicon film further comprises one or more third amorphous silicon layers (see e.g., the contact layer C includes N two-layer structures S(n). Each of the two- layer structures S(n) has a second amorphous silicon layer 72(n) and a third amorphous silicon layer 73(n), Figures 6a-6d), each of the one or more third amorphous silicon layers containing impurities in a concentration lower than a concentration of the first amorphous silicon layer and higher than a concentration of a surface of each of the first region and the second region joining with the first contact layer or the second contact layer (see e.g., the third amorphous silicon layer 73(n) has an impurity concentration of C3 which is lower than the impurity concentration C1 of first amorphous silicon layer 71 and higher than the surface concentration of semiconductor layer 4 formed from active layer 40 which is non-doped and may have impurity at a very low concentration),
and a thickness of a third amorphous silicon layer located directly below the first amorphous silicon layer among the one or more third amorphous silicon layers is smaller than the thickness difference between the first region and the channel region and the thickness difference between the second region and the channel region.
Ohta teaches the thickness of the third amorphous silicon layer 73(n) directly below the first amorphous silicon layer 71 is 10nm (see e.g., Figures 6a-6d). This thickness is consistently smaller than the thickness difference calculated from Watanabe (t1-t2, which maybe more than 10nm and less than 70nm). Therefore, the combined teachings of Watanabe and Ohta show that the thickness of the first amorphous silicon layer is smaller than the calculated thickness difference, thus reading on the claim limitation.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement thinner specific layer in a multilayered ohmic contact layer to improve the device, as demonstrated by the improved drive current and contact resistivity achieved by such structures.
Regarding claim 11, Watanabe as modified by Wu and Ohta, teaches the limitations of claim 10 as mentioned above. Watanabe does not explicitly teach
“wherein a thickness of another third amorphous silicon layer located at a lowermost layer of the second amorphous silicon film among the one or more third amorphous silicon layers is greater than the thickness of the first amorphous silicon layer and the thickness of the third amorphous silicon layer located directly below the first amorphous silicon layer”.
In a similar field of endeavor Ohta teaches
wherein a thickness of another third amorphous silicon layer located at a lowermost layer of the second amorphous silicon film among the one or more third amorphous silicon layers is greater than the thickness of the first amorphous silicon layer and the thickness of the third amorphous silicon layer located directly below the first amorphous silicon layer (see e.g., the lowermost layer of the multilayer structure, the contact layer may further include a fourth amorphous silicon layer 74 having an impurity concentration of C4. Figure 6c shows the thickness of fourth amorphous silicon layer 74 to be 30nm which is greater than the thickness of the first amorphous silicon layer 71 (15nm) and the third amorphous silicon layer 73(1) (10nm) which is directly below the first amorphous silicon layer 71).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Ohta’s teachings of wherein a thickness of another third amorphous silicon layer located at a lowermost layer of the second amorphous silicon film among the one or more third amorphous silicon layers is greater than the thickness of the first amorphous silicon layer and the thickness of the third amorphous silicon layer located directly below the first amorphous silicon layer in the method of Watanabe in order to improve the device, as demonstrated by the improved drive current and contact resistivity achieved by such structures.
Regarding claim 12, Watanabe as modified by Wu and Ohta, teaches the limitations of claim 10 as mentioned above. Watanabe does not explicitly teach
“wherein a concentration of impurities contained in the first amorphous silicon layer is greater than or equal to 100 times and less than or equal to 10000 times a concentration of impurities contained in the surface of each of the first region and the second region”.
In a similar field of endeavor Ohta teaches
wherein a concentration of impurities contained in the first amorphous silicon layer is greater than or equal to 100 times and less than or equal to 10000 times a concentration of impurities contained in the surface of each of the first region and the second region (see e.g., the semiconductor layer 4 formed from active layer 40 which is non-doped and may have a relatively low impurity concentration. However, the first amorphous semiconductor layer 71 has a concentration C1 which may be not less than 5×10.sup.19 atoms/cm.sup.3 and not more than 1×10.sup.23 atoms/cm.sup.3.).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Ohta’s teachings of wherein a concentration of impurities contained in the first amorphous silicon layer is greater than or equal to 100 times and less than or equal to 10000 times a concentration of impurities contained in the surface of each of the first region and the second region in the method of Watanabe for the purpose of creating the necessary impurity regions to allow for the basic function of the transistor.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893