DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1-11, 16, 20 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2021/0013333). (hereinafter, Yang) in view Lan et al. (US 2021/0327873), (hereinafter, Lan).
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RE Claim 1, Yang discloses in FIGS. 1-9 a high-electron mobility transistor and a method of making the same including a trench isolation structure adjacent and surrounding the channel layer and the barrier layer to apply stress and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of the high electron mobility transistor. Yang discloses a structure comprising:
a substrate 102/104. Examiner notes that the HEMT stack is formed above the insulating layer 104, thus the stacked 102 “silicon”/104 “oxide layer” represent the substrate upon which the HEMT is being formed, hence meeting the claimed limitation and definition of a substrate;
a device “HEMT” region 126 on the substrate 102, referring to FIG. 1, the device region 126 including a first section of a layer stack 106/108/110/112 that includes a plurality of semiconductor layers 106/108/110/112, the layer stack 106/108/110/112 having a top surface “of the layer 112”, referring to FIG. 4, and each semiconductor layer comprising a compound semiconductor material, referring to FIG. 4 above;
an isolation structure 128 surrounding the first section of the layer stack 106/108/110/112, the isolation structure penetrating from the top surface “of the layer 112” of the layer stack fully through the layer stack 106/108/110/112 to the substrate 102/104, referring to FIGS. 4 and 8; and
a device “HEMT” in the device region 126, referring to FIG. 1, by virtue of having source, drain and gate 120, 122 and 118 respectively [abstract].
Yang does not disclose:
an interconnect structure on the substrate; and
a passive device in the interconnect structure, wherein the isolation structure is disposed between the passive device and the substrate.
However, in the same field of endeavor, Lan discloses heterogeneous integrated wideband high electron mobility transistor power amplifier with a single-crystal acoustic resonator/filter with a compound III-V semiconductor HEMT device in the “device region” and a method of making the same, wherein an interconnect structure 450 “integrated passive device” over the substrate 402, referring to FIG. 4; and
a passive device 460 “inductive-capacitor (LC) filter as the IPD” including “MIM” capacitor 470, an inductor 480 embedded in the interconnect structure 450 formed over the “device region”, hence the HEMT, referring to FIG. 4 [0056 and 0077].
Therefore, it would have been obvious for one of ordinary skill in the art prior to the effective filing date of the instant application to have passive device embedded in an interconnect structure of Yang similar to Lan circuitry, wherein the isolation structure is disposed between the passive device and the substrate of Yang in order to enable high quality “Q-ratio” broad band filtering. Examiner notes that Lan is used OLNY to show that a passive device 460 “inductive-capacitor (LC) filter as the IPD” including “MIM” capacitor 470, an inductor 480 embedded in the interconnect structure 450 is well-known BEOL feature that can be formed over the “device region”, hence over the HEMT of Lan and by a similar token over Yang HEMT structure including the isolation region 128, hence obvious to have passive device 460 “inductive-capacitor (LC) filter as the IPD” including “MIM” capacitor 470, an inductor 480 embedded in the interconnect structure disposed over the isolation structure.
RE Claim 2, Yang discloses a structure, wherein the high-mobility field-effect transistor includes a source contact 120, a drain contact 122, and a gate 118.
Yang does not disclose a structure, wherein the high-mobility field-effect transistor including a source ohmic contact, a drain ohmic contact, and a gate.
However, in the same field of endeavor, Lan discloses heterogeneous integrated wideband high electron mobility transistor power amplifier with a single-crystal acoustic resonator/filter with a compound III-V semiconductor HEMT device and a method of making the same, wherein source/drain ohmic contacts of the source/drain regions of the compound semiconductor HEMT active device 410.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to use ohmic contacts for the source/drain in order to achieve better electrical connectivity.
RE Claim 3, Yang discloses structure, wherein the isolation structure 128 includes a first portion, bounded by arrows in I, II, III and IV, having a first aspect ratio and a second portion bounded by arrows in I, II, III and IV, having a second aspect ratio different from the first aspect ratio, referring to FIGS. 8 and 9.
RE Claim 4, Yang discloses a structure, wherein the first portion, bounded by arrows in I, II, III and IV, and the second portion, bounded by arrows in I, II, III and IV, of the isolation structure 128 adjoin different portions of the device region, referring to FIGS. 8 and 9.
RE Claim 5, Yang discloses a structure, wherein the first portion and the second portion of the isolation structure have equal heights, referring to FIG. 4.
RE Claim 6, Yang discloses a structure, wherein the layer stack includes a first recess “trench” 124 penetrating through the layer stack 106/108/110/112 to the substrate 102/104 and a second recess “trench” 124 penetrating through the layer stack 106/108/110/112 to the substrate 102/104, the first portion of the isolation structure 128 is disposed in the first recess “trench”, and the second portion 128 of the isolation structure is disposed in the second recess “trench” 124, referring to FIGS. 2, 4, 8 and 9.
RE Claim 7, Yang discloses a structure, wherein the isolation structure 128 has a top surface that is substantially coplanar with the top surface “of the layer 112” of the layer stack, referring to FIG. 4.
RE Claim 8, Yang discloses a structure, wherein the layer stack includes a second section and a first channel between the first section and the second section, and the first portion of the isolation structure is disposed in the first recess “trench”, referring to the annotated FIG. 8 above sections I-V.
RE Claim 9, Yang discloses a structure, wherein the layer stack includes a third section and a second channel 24 between the first section and the third section, and the second portion of the isolation structure 128 is disposed in the second recess “trench” 24, referring to FIG. 8 as annotated above sections I-V.
RE Claim 10, Yang discloses a structure, wherein the layer stack 106/108/110/112 includes a recess “trench” 24 penetrating through the layer stack to the substrate 102/104, the channel adjoins the device region 126, referring to the planar view of FIGS. 8 and 9, and the isolation structure comprises a layer in the recess “trench” 24.
RE Claim 11, Yang discloses a structure, wherein the layer of the isolation structure 128 comprises a dielectric material “silicon nitride” [0033].
RE Claim 16, Yang discloses a structure, wherein the compound semiconductor material of at least one of the plurality of semiconductor layers comprises gallium nitride, referring to the annotated FIG. 1 above.
RE Claim 20, Yang discloses in FIGS. 1-9 a high-electron mobility transistor and a method of making the same including a trench isolation structure adjacent and surrounding the channel layer and the barrier layer to apply stress and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of the high electron mobility transistor. Yang discloses a method comprising:
forming a device region 126 on a substrate 102/104, wherein the device region 126 includes a section of a layer stack 106/108/110/112, the layer stack includes a plurality of semiconductor layers 106/108/110/112, and each semiconductor layer comprises a compound semiconductor material, referring to FIG. 2;
forming an isolation structure 128 disposed about the device region 126 of the layer stack 106/108/110/112, wherein the isolation structure 128 penetrates through the layer stack 106/108/110/112 to the substrate 102/104; and
forming a device “HEMT” in the device region 126.
Yang does not disclose:
forming an interconnect structure on the substrate; and
forming a passive device in the interconnect structure, wherein the isolation structure is disposed between the passive device and the substrate.
However, in the same field of endeavor, Lan discloses heterogeneous integrated wideband high electron mobility transistor power amplifier with a single-crystal acoustic resonator/filter with a compound III-V semiconductor HEMT device in the “device region” and a method of making the same, wherein forming, as BEOL “back-end of the line process sequence, hence after forming the HEMT device structure”, an interconnect structure 450 “integrated passive device” over the substrate 402, referring to FIG. 4; and
forming a passive device 460 “inductive-capacitor (LC) filter as the IPD” including “MIM” capacitor 470, an inductor 480 embedded in the interconnect structure 450 formed over the “device region”, hence the HEMT, referring to FIG. 4 [0056 and 0077].
Therefore, it would have been obvious for one of ordinary skill in the art prior to the effective filing date of the instant application to from passive device embedded in an interconnect structure of Yang similar to Lan circuitry, wherein forming the isolation structure is disposed between the passive device and the substrate of Yang in order to enable high quality “Q-ratio” broad band filtering. Examiner notes that Lan is used OLNY to show that a passive device 460 “inductive-capacitor (LC) filter as the IPD” including “MIM” capacitor 470, an inductor 480 embedded in the interconnect structure 450 is well-known BEOL feature that can be formed over the “device region”, hence over the HEMT of Lan and by a similar token over Yang HEMT structure including the isolation region 128, hence obvious to have passive device 460 “inductive-capacitor (LC) filter as the IPD” including “MIM” capacitor 470, an inductor 480 embedded in the interconnect structure disposed over the isolation structure.
RE Claim 21, Yang does not disclose structure, wherein the passive device does not overlie a portion of the layer stack.
However, in the same field of endeavor, Lan discloses heterogeneous integrated wideband high electron mobility transistor power amplifier with a single-crystal acoustic resonator/filter with a compound III-V semiconductor HEMT device in the “device region” and a method of making the same, wherein the passive device “MIM” capacitor 470, an inductor 480 embedded in the interconnect structure 450 formed over the “device region” HEMT does not overlie a portion of the HEMT layer stack, i.e. HEMT region.
Therefore, it would have been obvious for one of ordinary skill in the art prior to the effective filing date of the instant application to from passive device without overlie a portion of the layer stack, i.e. HEMT device layers in order reduce the capacitive loading effects.
Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2021/0013333). (hereinafter, Yang) in view Lan et al. (US 2021/0327873), (hereinafter, Lan) and in further view of Moens et al. (US 2016/0043218), (hereinafter, Moens).
RE Claims 12-13, Yang does not disclose a structure, wherein the layer of the isolation structure 128 comprises a polycrystalline semiconductor material or a metal.
However, in the same field of endeavor, Moens discloses a compound III-V semiconductor HEMT device and a method of making the same, wherein an isolation trench 40 is formed in a stacked semiconductor layers 18/20/22/24 [0046], wherein the layer of the isolation structure 42 comprises material 48 comprising polysilicon or metal [0047], referring to FIG. 3.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to use the polysilicon or metal material for the isolation structure 128 in order to achieve better device isolation and reducing leakage current.
RE Claim 14, Yang discloses a structure, wherein the recess “trench” 24 has a sidewall, the device region 126 adjoins the sidewall, referring to FIG. 4.
Yang does not disclose a structure, wherein the isolation structure 128 comprises a dielectric liner on the device region at the sidewall of the recess “trench” 24.
However, However, in the same field of endeavor, Moens discloses a compound III-V semiconductor HEMT device and a method of making the same, wherein the isolation structure 42 comprises a dielectric “insulating” liner 46 “silicon nitride or aluminum oxide” on the device region at the sidewall of the recess “trench” 40.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to use a dielectric “insulating” liner for the on the device region at the sidewall of the recess “trench” 24 of Yang in order to isolate the metal/polysilicon isolation structure form the semiconductor region of the device region.
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2021/0013333). (hereinafter, Yang) in view of Lan et al. (US 2021/0327873), (hereinafter, Lan) and in further view of Lin et al. (US 11,049,799), (hereinafter, Lin).
RE Claim 17, Yang discloses a structure, wherein the device region 126 is surrounded by a plurality of recess “trench” 24 in a patterned area, referring to FIGS. 4, 8 and 9.
However, Yang discloses a structure, wherein the plurality of recess “trench” 24 occupy 40 percent to 90 percent of the patterned area.
However, it would have been obvious to one having ordinary skill in the art prior the effective filing date of the instant application, absent unexpected results, to have channels 24 occupy 40 percent to 90 percent of the patterned area as claimed, since it has been held that discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996).
RE Claim 18, Yang discloses a structure, wherein the layer stack includes a recess “trench” 24 penetrating through the layer stack 106/108/110/112 to the substrate 102/104, the channel 24 adjoins the substrate 102/104.
Yang does not disclose a damaged region of semiconductor material in the substrate adjacent to the recess “trench” 24.
However, in a related art, Lin discloses a compound “GaN-based” semiconductor device and a method of making the same, wherein an isolation trench 170 penetrating through semiconductor stacked layer 110, wherein a damage region 120 of the semiconductor material 110, formed by breaking the crystal lattice structure of the semiconductor material is formed by ion irradiation. Examiner notes that the damaged region is formed adjacent to a sidewall of the channel 24, hence meeting the claimed limitation of Claim 19.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to form a damaged region of semiconductor material 106/108/110/112 in the substrate adjacent to the channel 24 of Yang in as a well-known in the art for forming isolation region in semiconductor material in order to reduce leakage current in the semiconductor device.
Response to Arguments
Applicant's arguments filed 01/15/2026 have been fully considered but they are not persuasive. Applicant argue that “Lan discloses a passive device, Lan fails to teach a person having ordinary skill in the art how to position the passive device relative to an isolation structure. Lan fails to disclose an isolation structure as a reference for positioning the passive device. Hence, Lan necessarily fails to teach a person having ordinary skill in the art that the isolation structure 128 in Yang would be disposed between the passive device in Lan and the substrate in Yang, and also necessarily fails to teach a person having ordinary skill in the art that the passive device in Lan can be disposed over an isolation structure analogous to the isolation structure 128 in Yang.” It appears that applicant is alluding to that the features of Lan cannot bodily incorporated into the structure of Yang. Lan is relied upon to teach that, at the BEOL process, hence after forming a HEMT device, an interconnect structure formed over the device “HEMT” region with included passive devices such as capacitors and inductors can be included in HEMT integrated devices, while Yang was utilized as the primary reference disclosing the details of the HEMT device structure. Therefore, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Furthermore, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Therefore, the rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, DUTTA et al. (US 2021/0391321) disclose a semiconductor device having metamorphic high electron mobility transistor (HEMT)-heterojunction bipolar transistor (HBT) integration on a semiconductor substrate. An example semiconductor device generally includes a semiconductor substrate, a bipolar junction transistor (BJT) disposed above the semiconductor substrate and comprising indium, and a HEMT disposed above the semiconductor substrate and comprising indium; wherein various back-end-of-line (BEOL) fabrication processes, when passive electrical devices are formed and the various electrical devices are electrically interconnected with local interconnects, conductive layers, and conductive vias.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898